atomic.cc revision 9342
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/atomic.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/ExecFaulting.hh" 518232Snate@binkert.org#include "debug/SimpleCPU.hh" 523348Sbinkertn@umich.edu#include "mem/packet.hh" 533348Sbinkertn@umich.edu#include "mem/packet_access.hh" 548926Sandreas.hansson@arm.com#include "mem/physical.hh" 554762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592623SN/A 602623SN/Ausing namespace std; 612623SN/Ausing namespace TheISA; 622623SN/A 632623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 645606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 652623SN/A{ 662623SN/A} 672623SN/A 682623SN/A 692623SN/Avoid 702623SN/AAtomicSimpleCPU::TickEvent::process() 712623SN/A{ 722623SN/A cpu->tick(); 732623SN/A} 742623SN/A 752623SN/Aconst char * 765336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 772623SN/A{ 784873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 792623SN/A} 802623SN/A 812623SN/Avoid 822623SN/AAtomicSimpleCPU::init() 832623SN/A{ 842623SN/A BaseCPU::init(); 858921Sandreas.hansson@arm.com 868921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 878921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 888921Sandreas.hansson@arm.com 899058Satgutier@umich.edu if (FullSystem && !params()->defer_registration) { 908779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 918779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 928779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 938779Sgblack@eecs.umich.edu // initialize CPU, including PC 948779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 958779Sgblack@eecs.umich.edu } 962623SN/A } 978706Sandreas.hansson@arm.com 985714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 995712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1005712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1015712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1022623SN/A} 1032623SN/A 1045529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1056078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1065487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1075487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1089095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1099095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 1108926Sandreas.hansson@arm.com fastmem(p->fastmem) 1112623SN/A{ 1122623SN/A _status = Idle; 1132623SN/A} 1142623SN/A 1152623SN/A 1162623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1172623SN/A{ 1186775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1196775SBrad.Beckmann@amd.com deschedule(tickEvent); 1206775SBrad.Beckmann@amd.com } 1212623SN/A} 1222623SN/A 1232623SN/Avoid 1242623SN/AAtomicSimpleCPU::serialize(ostream &os) 1252623SN/A{ 1269342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 1272915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1286078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1293145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1302623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1312623SN/A tickEvent.serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1379342SAndreas.Sandberg@arm.com Drainable::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1396078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 1403145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1412915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1422915Sktlim@umich.edu} 1432915Sktlim@umich.edu 1449342SAndreas.Sandberg@arm.comunsigned int 1459342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drain(DrainManager *drain_manager) 1469342SAndreas.Sandberg@arm.com{ 1479342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1489342SAndreas.Sandberg@arm.com return 0; 1499342SAndreas.Sandberg@arm.com} 1509342SAndreas.Sandberg@arm.com 1512915Sktlim@umich.eduvoid 1529342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1532915Sktlim@umich.edu{ 1545220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1555220Ssaidi@eecs.umich.edu return; 1565220Ssaidi@eecs.umich.edu 1574940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1585220Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 1593324Shsul@eecs.umich.edu 1609342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 1615220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1625606Snate@binkert.org if (!tickEvent.scheduled()) 1635606Snate@binkert.org schedule(tickEvent, nextCycle()); 1642915Sktlim@umich.edu } 1657897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1662623SN/A} 1672623SN/A 1682623SN/Avoid 1692798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1702623SN/A{ 1719342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1722798Sktlim@umich.edu _status = SwitchedOut; 1732623SN/A 1742798Sktlim@umich.edu tickEvent.squash(); 1752623SN/A} 1762623SN/A 1772623SN/A 1782623SN/Avoid 1792623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1802623SN/A{ 1818737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 1822623SN/A 1832623SN/A assert(!tickEvent.scheduled()); 1842623SN/A 1852680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1862623SN/A // running and schedule its tick event. 1876221Snate@binkert.org ThreadID size = threadContexts.size(); 1886221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 1892680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1909342SAndreas.Sandberg@arm.com if (tc->status() == ThreadContext::Active && 1919342SAndreas.Sandberg@arm.com _status != BaseSimpleCPU::Running) { 1929342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 1935606Snate@binkert.org schedule(tickEvent, nextCycle()); 1942623SN/A break; 1952623SN/A } 1962623SN/A } 1979342SAndreas.Sandberg@arm.com if (_status != BaseSimpleCPU::Running) { 1983512Sktlim@umich.edu _status = Idle; 1993512Sktlim@umich.edu } 2005169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2015712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2025712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2035712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2042623SN/A} 2052623SN/A 2062623SN/A 2072623SN/Avoid 2089180Sandreas.hansson@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2092623SN/A{ 2104940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2114940Snate@binkert.org 2122623SN/A assert(thread_num == 0); 2132683Sktlim@umich.edu assert(thread); 2142623SN/A 2152623SN/A assert(_status == Idle); 2162623SN/A assert(!tickEvent.scheduled()); 2172623SN/A 2182623SN/A notIdleFraction++; 2199180Sandreas.hansson@arm.com numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend); 2203686Sktlim@umich.edu 2213430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2229179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2239342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2242623SN/A} 2252623SN/A 2262623SN/A 2272623SN/Avoid 2288737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2292623SN/A{ 2304940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2314940Snate@binkert.org 2322623SN/A assert(thread_num == 0); 2332683Sktlim@umich.edu assert(thread); 2342623SN/A 2356043Sgblack@eecs.umich.edu if (_status == Idle) 2366043Sgblack@eecs.umich.edu return; 2376043Sgblack@eecs.umich.edu 2389342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2392626SN/A 2402626SN/A // tick event may not be scheduled if this gets called from inside 2412626SN/A // an instruction's execution, e.g. "quiesce" 2422626SN/A if (tickEvent.scheduled()) 2435606Snate@binkert.org deschedule(tickEvent); 2442623SN/A 2452623SN/A notIdleFraction--; 2462623SN/A _status = Idle; 2472623SN/A} 2482623SN/A 2492623SN/A 2502623SN/AFault 2518444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2528444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 2532623SN/A{ 2543169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2554870Sstever@eecs.umich.edu Request *req = &data_read_req; 2562623SN/A 2572623SN/A if (traceData) { 2582623SN/A traceData->setAddr(addr); 2592623SN/A } 2602623SN/A 2614999Sgblack@eecs.umich.edu //The block size of our peer. 2626227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 2634999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 2647520Sgblack@eecs.umich.edu int fullSize = size; 2652623SN/A 2664999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 2674999Sgblack@eecs.umich.edu //across a cache line boundary. 2687520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 2694999Sgblack@eecs.umich.edu 2707520Sgblack@eecs.umich.edu if (secondAddr > addr) 2717520Sgblack@eecs.umich.edu size = secondAddr - addr; 2724999Sgblack@eecs.umich.edu 2734999Sgblack@eecs.umich.edu dcache_latency = 0; 2744999Sgblack@eecs.umich.edu 2757520Sgblack@eecs.umich.edu while (1) { 2768832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 2774999Sgblack@eecs.umich.edu 2784999Sgblack@eecs.umich.edu // translate to physical address 2796023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 2804999Sgblack@eecs.umich.edu 2814999Sgblack@eecs.umich.edu // Now do the access. 2826623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 2834999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 2848949Sandreas.hansson@arm.com req->isLLSC() ? MemCmd::LoadLockedReq : 2858949Sandreas.hansson@arm.com MemCmd::ReadReq); 2867520Sgblack@eecs.umich.edu pkt.dataStatic(data); 2874999Sgblack@eecs.umich.edu 2888105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 2894999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 2904999Sgblack@eecs.umich.edu else { 2918931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 2928931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 2934999Sgblack@eecs.umich.edu else 2944999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 2954999Sgblack@eecs.umich.edu } 2964999Sgblack@eecs.umich.edu dcache_access = true; 2975012Sgblack@eecs.umich.edu 2984999Sgblack@eecs.umich.edu assert(!pkt.isError()); 2994999Sgblack@eecs.umich.edu 3006102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3014999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3024999Sgblack@eecs.umich.edu } 3034968Sacolyte@umich.edu } 3044986Ssaidi@eecs.umich.edu 3054999Sgblack@eecs.umich.edu //If there's a fault, return it 3066739Sgblack@eecs.umich.edu if (fault != NoFault) { 3076739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3086739Sgblack@eecs.umich.edu return NoFault; 3096739Sgblack@eecs.umich.edu } else { 3106739Sgblack@eecs.umich.edu return fault; 3116739Sgblack@eecs.umich.edu } 3126739Sgblack@eecs.umich.edu } 3136739Sgblack@eecs.umich.edu 3144999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3154999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3164999Sgblack@eecs.umich.edu { 3176078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3186078Sgblack@eecs.umich.edu assert(!locked); 3196078Sgblack@eecs.umich.edu locked = true; 3206078Sgblack@eecs.umich.edu } 3214999Sgblack@eecs.umich.edu return fault; 3224968Sacolyte@umich.edu } 3233170Sstever@eecs.umich.edu 3244999Sgblack@eecs.umich.edu /* 3254999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3264999Sgblack@eecs.umich.edu */ 3274999Sgblack@eecs.umich.edu 3284999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3297520Sgblack@eecs.umich.edu data += size; 3304999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3317520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3324999Sgblack@eecs.umich.edu //And access the right address. 3334999Sgblack@eecs.umich.edu addr = secondAddr; 3342623SN/A } 3352623SN/A} 3362623SN/A 3377520Sgblack@eecs.umich.edu 3382623SN/AFault 3398444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3408444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3412623SN/A{ 3423169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3434870Sstever@eecs.umich.edu Request *req = &data_write_req; 3442623SN/A 3452623SN/A if (traceData) { 3462623SN/A traceData->setAddr(addr); 3472623SN/A } 3482623SN/A 3494999Sgblack@eecs.umich.edu //The block size of our peer. 3506227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3514999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3527520Sgblack@eecs.umich.edu int fullSize = size; 3532623SN/A 3544999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3554999Sgblack@eecs.umich.edu //across a cache line boundary. 3567520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3574999Sgblack@eecs.umich.edu 3584999Sgblack@eecs.umich.edu if(secondAddr > addr) 3597520Sgblack@eecs.umich.edu size = secondAddr - addr; 3604999Sgblack@eecs.umich.edu 3614999Sgblack@eecs.umich.edu dcache_latency = 0; 3624999Sgblack@eecs.umich.edu 3634999Sgblack@eecs.umich.edu while(1) { 3648832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3654999Sgblack@eecs.umich.edu 3664999Sgblack@eecs.umich.edu // translate to physical address 3676023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 3684999Sgblack@eecs.umich.edu 3694999Sgblack@eecs.umich.edu // Now do the access. 3704999Sgblack@eecs.umich.edu if (fault == NoFault) { 3714999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3724999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3734999Sgblack@eecs.umich.edu 3746102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3754999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3764999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3774999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3784999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3794999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 3804999Sgblack@eecs.umich.edu assert(res); 3814999Sgblack@eecs.umich.edu req->setExtraData(*res); 3824999Sgblack@eecs.umich.edu } 3834999Sgblack@eecs.umich.edu } 3844999Sgblack@eecs.umich.edu 3856623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 3868949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 3877520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3884999Sgblack@eecs.umich.edu 3898105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 3904999Sgblack@eecs.umich.edu dcache_latency += 3914999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 3924999Sgblack@eecs.umich.edu } else { 3938931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3948931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3954999Sgblack@eecs.umich.edu else 3964999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3974999Sgblack@eecs.umich.edu } 3984999Sgblack@eecs.umich.edu dcache_access = true; 3994999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4004999Sgblack@eecs.umich.edu 4014999Sgblack@eecs.umich.edu if (req->isSwap()) { 4024999Sgblack@eecs.umich.edu assert(res); 4037520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 4044999Sgblack@eecs.umich.edu } 4054999Sgblack@eecs.umich.edu } 4064999Sgblack@eecs.umich.edu 4074999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4084999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4094878Sstever@eecs.umich.edu } 4104040Ssaidi@eecs.umich.edu } 4114040Ssaidi@eecs.umich.edu 4124999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4134999Sgblack@eecs.umich.edu //stop now. 4144999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4154999Sgblack@eecs.umich.edu { 4166078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4176078Sgblack@eecs.umich.edu assert(locked); 4186078Sgblack@eecs.umich.edu locked = false; 4196078Sgblack@eecs.umich.edu } 4206739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4216739Sgblack@eecs.umich.edu return NoFault; 4226739Sgblack@eecs.umich.edu } else { 4236739Sgblack@eecs.umich.edu return fault; 4246739Sgblack@eecs.umich.edu } 4253170Sstever@eecs.umich.edu } 4263170Sstever@eecs.umich.edu 4274999Sgblack@eecs.umich.edu /* 4284999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4294999Sgblack@eecs.umich.edu */ 4304999Sgblack@eecs.umich.edu 4314999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4327520Sgblack@eecs.umich.edu data += size; 4334999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4347520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4354999Sgblack@eecs.umich.edu //And access the right address. 4364999Sgblack@eecs.umich.edu addr = secondAddr; 4372623SN/A } 4382623SN/A} 4392623SN/A 4402623SN/A 4412623SN/Avoid 4422623SN/AAtomicSimpleCPU::tick() 4432623SN/A{ 4444940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4454940Snate@binkert.org 4465487Snate@binkert.org Tick latency = 0; 4472623SN/A 4486078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 4492623SN/A numCycles++; 4502623SN/A 4513387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4523387Sgblack@eecs.umich.edu checkForInterrupts(); 4532626SN/A 4545348Ssaidi@eecs.umich.edu checkPcEventQueue(); 4558143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 4568143SAli.Saidi@ARM.com if (_status == Idle) 4578143SAli.Saidi@ARM.com return; 4585348Ssaidi@eecs.umich.edu 4595669Sgblack@eecs.umich.edu Fault fault = NoFault; 4605669Sgblack@eecs.umich.edu 4617720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4627720Sgblack@eecs.umich.edu 4637720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 4647720Sgblack@eecs.umich.edu !curMacroStaticInst; 4657720Sgblack@eecs.umich.edu if (needToFetch) { 4665894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 4676023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 4686023Snate@binkert.org BaseTLB::Execute); 4695894Sgblack@eecs.umich.edu } 4702623SN/A 4712623SN/A if (fault == NoFault) { 4724182Sgblack@eecs.umich.edu Tick icache_latency = 0; 4734182Sgblack@eecs.umich.edu bool icache_access = false; 4744182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 4752662Sstever@eecs.umich.edu 4767720Sgblack@eecs.umich.edu if (needToFetch) { 4779023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 4785694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 4795694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 4805694Sgblack@eecs.umich.edu // this code should be uncommented. 4815669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 4829023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 4835669Sgblack@eecs.umich.edu //{ 4845669Sgblack@eecs.umich.edu icache_access = true; 4858949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 4865669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 4872623SN/A 4888931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 4898931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 4905669Sgblack@eecs.umich.edu else 4915669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 4924968Sacolyte@umich.edu 4935669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 4944968Sacolyte@umich.edu 4955669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 4965669Sgblack@eecs.umich.edu // into the CPU object's inst field. 4975669Sgblack@eecs.umich.edu //} 4985669Sgblack@eecs.umich.edu } 4994182Sgblack@eecs.umich.edu 5002623SN/A preExecute(); 5013814Ssaidi@eecs.umich.edu 5025001Sgblack@eecs.umich.edu if (curStaticInst) { 5034182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5044998Sgblack@eecs.umich.edu 5054998Sgblack@eecs.umich.edu // keep an instruction count 5064998Sgblack@eecs.umich.edu if (fault == NoFault) 5074998Sgblack@eecs.umich.edu countInst(); 5087655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5095001Sgblack@eecs.umich.edu delete traceData; 5105001Sgblack@eecs.umich.edu traceData = NULL; 5115001Sgblack@eecs.umich.edu } 5124998Sgblack@eecs.umich.edu 5134182Sgblack@eecs.umich.edu postExecute(); 5144182Sgblack@eecs.umich.edu } 5152623SN/A 5163814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5174539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5184539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5193814Ssaidi@eecs.umich.edu instCnt++; 5203814Ssaidi@eecs.umich.edu 5215487Snate@binkert.org Tick stall_ticks = 0; 5225487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5235487Snate@binkert.org stall_ticks += icache_latency; 5245487Snate@binkert.org 5255487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5265487Snate@binkert.org stall_ticks += dcache_latency; 5275487Snate@binkert.org 5285487Snate@binkert.org if (stall_ticks) { 5299180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 5309180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 5319180Sandreas.hansson@arm.com // period 5329180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 5339180Sandreas.hansson@arm.com clockPeriod(); 5342623SN/A } 5352623SN/A 5362623SN/A } 5374377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5384182Sgblack@eecs.umich.edu advancePC(fault); 5392623SN/A } 5402623SN/A 5415487Snate@binkert.org // instruction takes at least one cycle 5429179Sandreas.hansson@arm.com if (latency < clockPeriod()) 5439179Sandreas.hansson@arm.com latency = clockPeriod(); 5445487Snate@binkert.org 5452626SN/A if (_status != Idle) 5467823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 5472623SN/A} 5482623SN/A 5492623SN/A 5505315Sstever@gmail.comvoid 5515315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 5525315Sstever@gmail.com{ 5535315Sstever@gmail.com dcachePort.printAddr(a); 5545315Sstever@gmail.com} 5555315Sstever@gmail.com 5565315Sstever@gmail.com 5572623SN/A//////////////////////////////////////////////////////////////////////// 5582623SN/A// 5592623SN/A// AtomicSimpleCPU Simulation Object 5602623SN/A// 5614762Snate@binkert.orgAtomicSimpleCPU * 5624762Snate@binkert.orgAtomicSimpleCPUParams::create() 5632623SN/A{ 5645529Snate@binkert.org numThreads = 1; 5658779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 5664762Snate@binkert.org panic("only one workload allowed"); 5675529Snate@binkert.org return new AtomicSimpleCPU(this); 5682623SN/A} 569