atomic.cc revision 9095
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/atomic.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/ExecFaulting.hh" 518232Snate@binkert.org#include "debug/SimpleCPU.hh" 523348Sbinkertn@umich.edu#include "mem/packet.hh" 533348Sbinkertn@umich.edu#include "mem/packet_access.hh" 548926Sandreas.hansson@arm.com#include "mem/physical.hh" 554762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592623SN/A 602623SN/Ausing namespace std; 612623SN/Ausing namespace TheISA; 622623SN/A 632623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 645606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 652623SN/A{ 662623SN/A} 672623SN/A 682623SN/A 692623SN/Avoid 702623SN/AAtomicSimpleCPU::TickEvent::process() 712623SN/A{ 722623SN/A cpu->tick(); 732623SN/A} 742623SN/A 752623SN/Aconst char * 765336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 772623SN/A{ 784873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 792623SN/A} 802623SN/A 812623SN/Avoid 822623SN/AAtomicSimpleCPU::init() 832623SN/A{ 842623SN/A BaseCPU::init(); 858921Sandreas.hansson@arm.com 868921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 878921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 888921Sandreas.hansson@arm.com 899058Satgutier@umich.edu if (FullSystem && !params()->defer_registration) { 908779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 918779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 928779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 938779Sgblack@eecs.umich.edu // initialize CPU, including PC 948779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 958779Sgblack@eecs.umich.edu } 962623SN/A } 978706Sandreas.hansson@arm.com 985714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 995712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1005712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1015712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1022623SN/A} 1032623SN/A 1045529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1056078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1065487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1075487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1089095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1099095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 1108926Sandreas.hansson@arm.com fastmem(p->fastmem) 1112623SN/A{ 1122623SN/A _status = Idle; 1132623SN/A} 1142623SN/A 1152623SN/A 1162623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1172623SN/A{ 1186775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1196775SBrad.Beckmann@amd.com deschedule(tickEvent); 1206775SBrad.Beckmann@amd.com } 1212623SN/A} 1222623SN/A 1232623SN/Avoid 1242623SN/AAtomicSimpleCPU::serialize(ostream &os) 1252623SN/A{ 1262915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1272915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1286078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1293145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1302623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1312623SN/A tickEvent.serialize(os); 1322623SN/A} 1332623SN/A 1342623SN/Avoid 1352623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1362623SN/A{ 1372915Sktlim@umich.edu SimObject::State so_state; 1382915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1396078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 1403145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1412915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1422915Sktlim@umich.edu} 1432915Sktlim@umich.edu 1442915Sktlim@umich.eduvoid 1452915Sktlim@umich.eduAtomicSimpleCPU::resume() 1462915Sktlim@umich.edu{ 1475220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1485220Ssaidi@eecs.umich.edu return; 1495220Ssaidi@eecs.umich.edu 1504940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1515220Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 1523324Shsul@eecs.umich.edu 1535220Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1545220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1555606Snate@binkert.org if (!tickEvent.scheduled()) 1565606Snate@binkert.org schedule(tickEvent, nextCycle()); 1572915Sktlim@umich.edu } 1587897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1592623SN/A} 1602623SN/A 1612623SN/Avoid 1622798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1632623SN/A{ 1645496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1652798Sktlim@umich.edu _status = SwitchedOut; 1662623SN/A 1672798Sktlim@umich.edu tickEvent.squash(); 1682623SN/A} 1692623SN/A 1702623SN/A 1712623SN/Avoid 1722623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1732623SN/A{ 1748737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 1752623SN/A 1762623SN/A assert(!tickEvent.scheduled()); 1772623SN/A 1782680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1792623SN/A // running and schedule its tick event. 1806221Snate@binkert.org ThreadID size = threadContexts.size(); 1816221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 1822680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1832680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1842623SN/A _status = Running; 1855606Snate@binkert.org schedule(tickEvent, nextCycle()); 1862623SN/A break; 1872623SN/A } 1882623SN/A } 1893512Sktlim@umich.edu if (_status != Running) { 1903512Sktlim@umich.edu _status = Idle; 1913512Sktlim@umich.edu } 1925169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1935712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1945712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1955712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1962623SN/A} 1972623SN/A 1982623SN/A 1992623SN/Avoid 2008737Skoansin.tan@gmail.comAtomicSimpleCPU::activateContext(ThreadID thread_num, int delay) 2012623SN/A{ 2024940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2034940Snate@binkert.org 2042623SN/A assert(thread_num == 0); 2052683Sktlim@umich.edu assert(thread); 2062623SN/A 2072623SN/A assert(_status == Idle); 2082623SN/A assert(!tickEvent.scheduled()); 2092623SN/A 2102623SN/A notIdleFraction++; 2115101Ssaidi@eecs.umich.edu numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 2123686Sktlim@umich.edu 2133430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2147823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2152623SN/A _status = Running; 2162623SN/A} 2172623SN/A 2182623SN/A 2192623SN/Avoid 2208737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2212623SN/A{ 2224940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2234940Snate@binkert.org 2242623SN/A assert(thread_num == 0); 2252683Sktlim@umich.edu assert(thread); 2262623SN/A 2276043Sgblack@eecs.umich.edu if (_status == Idle) 2286043Sgblack@eecs.umich.edu return; 2296043Sgblack@eecs.umich.edu 2302623SN/A assert(_status == Running); 2312626SN/A 2322626SN/A // tick event may not be scheduled if this gets called from inside 2332626SN/A // an instruction's execution, e.g. "quiesce" 2342626SN/A if (tickEvent.scheduled()) 2355606Snate@binkert.org deschedule(tickEvent); 2362623SN/A 2372623SN/A notIdleFraction--; 2382623SN/A _status = Idle; 2392623SN/A} 2402623SN/A 2412623SN/A 2422623SN/AFault 2438444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2448444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 2452623SN/A{ 2463169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2474870Sstever@eecs.umich.edu Request *req = &data_read_req; 2482623SN/A 2492623SN/A if (traceData) { 2502623SN/A traceData->setAddr(addr); 2512623SN/A } 2522623SN/A 2534999Sgblack@eecs.umich.edu //The block size of our peer. 2546227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 2554999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 2567520Sgblack@eecs.umich.edu int fullSize = size; 2572623SN/A 2584999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 2594999Sgblack@eecs.umich.edu //across a cache line boundary. 2607520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 2614999Sgblack@eecs.umich.edu 2627520Sgblack@eecs.umich.edu if (secondAddr > addr) 2637520Sgblack@eecs.umich.edu size = secondAddr - addr; 2644999Sgblack@eecs.umich.edu 2654999Sgblack@eecs.umich.edu dcache_latency = 0; 2664999Sgblack@eecs.umich.edu 2677520Sgblack@eecs.umich.edu while (1) { 2688832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 2694999Sgblack@eecs.umich.edu 2704999Sgblack@eecs.umich.edu // translate to physical address 2716023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 2724999Sgblack@eecs.umich.edu 2734999Sgblack@eecs.umich.edu // Now do the access. 2746623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 2754999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 2768949Sandreas.hansson@arm.com req->isLLSC() ? MemCmd::LoadLockedReq : 2778949Sandreas.hansson@arm.com MemCmd::ReadReq); 2787520Sgblack@eecs.umich.edu pkt.dataStatic(data); 2794999Sgblack@eecs.umich.edu 2808105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 2814999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 2824999Sgblack@eecs.umich.edu else { 2838931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 2848931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 2854999Sgblack@eecs.umich.edu else 2864999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 2874999Sgblack@eecs.umich.edu } 2884999Sgblack@eecs.umich.edu dcache_access = true; 2895012Sgblack@eecs.umich.edu 2904999Sgblack@eecs.umich.edu assert(!pkt.isError()); 2914999Sgblack@eecs.umich.edu 2926102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2934999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 2944999Sgblack@eecs.umich.edu } 2954968Sacolyte@umich.edu } 2964986Ssaidi@eecs.umich.edu 2974999Sgblack@eecs.umich.edu //If there's a fault, return it 2986739Sgblack@eecs.umich.edu if (fault != NoFault) { 2996739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3006739Sgblack@eecs.umich.edu return NoFault; 3016739Sgblack@eecs.umich.edu } else { 3026739Sgblack@eecs.umich.edu return fault; 3036739Sgblack@eecs.umich.edu } 3046739Sgblack@eecs.umich.edu } 3056739Sgblack@eecs.umich.edu 3064999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3074999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3084999Sgblack@eecs.umich.edu { 3096078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3106078Sgblack@eecs.umich.edu assert(!locked); 3116078Sgblack@eecs.umich.edu locked = true; 3126078Sgblack@eecs.umich.edu } 3134999Sgblack@eecs.umich.edu return fault; 3144968Sacolyte@umich.edu } 3153170Sstever@eecs.umich.edu 3164999Sgblack@eecs.umich.edu /* 3174999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3184999Sgblack@eecs.umich.edu */ 3194999Sgblack@eecs.umich.edu 3204999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3217520Sgblack@eecs.umich.edu data += size; 3224999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3237520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3244999Sgblack@eecs.umich.edu //And access the right address. 3254999Sgblack@eecs.umich.edu addr = secondAddr; 3262623SN/A } 3272623SN/A} 3282623SN/A 3297520Sgblack@eecs.umich.edu 3302623SN/AFault 3318444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3328444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3332623SN/A{ 3343169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3354870Sstever@eecs.umich.edu Request *req = &data_write_req; 3362623SN/A 3372623SN/A if (traceData) { 3382623SN/A traceData->setAddr(addr); 3392623SN/A } 3402623SN/A 3414999Sgblack@eecs.umich.edu //The block size of our peer. 3426227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3434999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3447520Sgblack@eecs.umich.edu int fullSize = size; 3452623SN/A 3464999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3474999Sgblack@eecs.umich.edu //across a cache line boundary. 3487520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3494999Sgblack@eecs.umich.edu 3504999Sgblack@eecs.umich.edu if(secondAddr > addr) 3517520Sgblack@eecs.umich.edu size = secondAddr - addr; 3524999Sgblack@eecs.umich.edu 3534999Sgblack@eecs.umich.edu dcache_latency = 0; 3544999Sgblack@eecs.umich.edu 3554999Sgblack@eecs.umich.edu while(1) { 3568832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3574999Sgblack@eecs.umich.edu 3584999Sgblack@eecs.umich.edu // translate to physical address 3596023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 3604999Sgblack@eecs.umich.edu 3614999Sgblack@eecs.umich.edu // Now do the access. 3624999Sgblack@eecs.umich.edu if (fault == NoFault) { 3634999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3644999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3654999Sgblack@eecs.umich.edu 3666102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3674999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3684999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3694999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3704999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3714999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 3724999Sgblack@eecs.umich.edu assert(res); 3734999Sgblack@eecs.umich.edu req->setExtraData(*res); 3744999Sgblack@eecs.umich.edu } 3754999Sgblack@eecs.umich.edu } 3764999Sgblack@eecs.umich.edu 3776623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 3788949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 3797520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3804999Sgblack@eecs.umich.edu 3818105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 3824999Sgblack@eecs.umich.edu dcache_latency += 3834999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 3844999Sgblack@eecs.umich.edu } else { 3858931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3868931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3874999Sgblack@eecs.umich.edu else 3884999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3894999Sgblack@eecs.umich.edu } 3904999Sgblack@eecs.umich.edu dcache_access = true; 3914999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3924999Sgblack@eecs.umich.edu 3934999Sgblack@eecs.umich.edu if (req->isSwap()) { 3944999Sgblack@eecs.umich.edu assert(res); 3957520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 3964999Sgblack@eecs.umich.edu } 3974999Sgblack@eecs.umich.edu } 3984999Sgblack@eecs.umich.edu 3994999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4004999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4014878Sstever@eecs.umich.edu } 4024040Ssaidi@eecs.umich.edu } 4034040Ssaidi@eecs.umich.edu 4044999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4054999Sgblack@eecs.umich.edu //stop now. 4064999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4074999Sgblack@eecs.umich.edu { 4086078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4096078Sgblack@eecs.umich.edu assert(locked); 4106078Sgblack@eecs.umich.edu locked = false; 4116078Sgblack@eecs.umich.edu } 4126739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4136739Sgblack@eecs.umich.edu return NoFault; 4146739Sgblack@eecs.umich.edu } else { 4156739Sgblack@eecs.umich.edu return fault; 4166739Sgblack@eecs.umich.edu } 4173170Sstever@eecs.umich.edu } 4183170Sstever@eecs.umich.edu 4194999Sgblack@eecs.umich.edu /* 4204999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4214999Sgblack@eecs.umich.edu */ 4224999Sgblack@eecs.umich.edu 4234999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4247520Sgblack@eecs.umich.edu data += size; 4254999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4267520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4274999Sgblack@eecs.umich.edu //And access the right address. 4284999Sgblack@eecs.umich.edu addr = secondAddr; 4292623SN/A } 4302623SN/A} 4312623SN/A 4322623SN/A 4332623SN/Avoid 4342623SN/AAtomicSimpleCPU::tick() 4352623SN/A{ 4364940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4374940Snate@binkert.org 4385487Snate@binkert.org Tick latency = 0; 4392623SN/A 4406078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 4412623SN/A numCycles++; 4422623SN/A 4433387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4443387Sgblack@eecs.umich.edu checkForInterrupts(); 4452626SN/A 4465348Ssaidi@eecs.umich.edu checkPcEventQueue(); 4478143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 4488143SAli.Saidi@ARM.com if (_status == Idle) 4498143SAli.Saidi@ARM.com return; 4505348Ssaidi@eecs.umich.edu 4515669Sgblack@eecs.umich.edu Fault fault = NoFault; 4525669Sgblack@eecs.umich.edu 4537720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4547720Sgblack@eecs.umich.edu 4557720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 4567720Sgblack@eecs.umich.edu !curMacroStaticInst; 4577720Sgblack@eecs.umich.edu if (needToFetch) { 4585894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 4596023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 4606023Snate@binkert.org BaseTLB::Execute); 4615894Sgblack@eecs.umich.edu } 4622623SN/A 4632623SN/A if (fault == NoFault) { 4644182Sgblack@eecs.umich.edu Tick icache_latency = 0; 4654182Sgblack@eecs.umich.edu bool icache_access = false; 4664182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 4672662Sstever@eecs.umich.edu 4687720Sgblack@eecs.umich.edu if (needToFetch) { 4699023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 4705694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 4715694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 4725694Sgblack@eecs.umich.edu // this code should be uncommented. 4735669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 4749023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 4755669Sgblack@eecs.umich.edu //{ 4765669Sgblack@eecs.umich.edu icache_access = true; 4778949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 4785669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 4792623SN/A 4808931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 4818931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 4825669Sgblack@eecs.umich.edu else 4835669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 4844968Sacolyte@umich.edu 4855669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 4864968Sacolyte@umich.edu 4875669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 4885669Sgblack@eecs.umich.edu // into the CPU object's inst field. 4895669Sgblack@eecs.umich.edu //} 4905669Sgblack@eecs.umich.edu } 4914182Sgblack@eecs.umich.edu 4922623SN/A preExecute(); 4933814Ssaidi@eecs.umich.edu 4945001Sgblack@eecs.umich.edu if (curStaticInst) { 4954182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 4964998Sgblack@eecs.umich.edu 4974998Sgblack@eecs.umich.edu // keep an instruction count 4984998Sgblack@eecs.umich.edu if (fault == NoFault) 4994998Sgblack@eecs.umich.edu countInst(); 5007655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5015001Sgblack@eecs.umich.edu delete traceData; 5025001Sgblack@eecs.umich.edu traceData = NULL; 5035001Sgblack@eecs.umich.edu } 5044998Sgblack@eecs.umich.edu 5054182Sgblack@eecs.umich.edu postExecute(); 5064182Sgblack@eecs.umich.edu } 5072623SN/A 5083814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5094539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5104539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5113814Ssaidi@eecs.umich.edu instCnt++; 5123814Ssaidi@eecs.umich.edu 5135487Snate@binkert.org Tick stall_ticks = 0; 5145487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5155487Snate@binkert.org stall_ticks += icache_latency; 5165487Snate@binkert.org 5175487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5185487Snate@binkert.org stall_ticks += dcache_latency; 5195487Snate@binkert.org 5205487Snate@binkert.org if (stall_ticks) { 5215487Snate@binkert.org Tick stall_cycles = stall_ticks / ticks(1); 5225487Snate@binkert.org Tick aligned_stall_ticks = ticks(stall_cycles); 5235487Snate@binkert.org 5245487Snate@binkert.org if (aligned_stall_ticks < stall_ticks) 5255487Snate@binkert.org aligned_stall_ticks += 1; 5265487Snate@binkert.org 5275487Snate@binkert.org latency += aligned_stall_ticks; 5282623SN/A } 5292623SN/A 5302623SN/A } 5314377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5324182Sgblack@eecs.umich.edu advancePC(fault); 5332623SN/A } 5342623SN/A 5355487Snate@binkert.org // instruction takes at least one cycle 5365487Snate@binkert.org if (latency < ticks(1)) 5375487Snate@binkert.org latency = ticks(1); 5385487Snate@binkert.org 5392626SN/A if (_status != Idle) 5407823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 5412623SN/A} 5422623SN/A 5432623SN/A 5445315Sstever@gmail.comvoid 5455315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 5465315Sstever@gmail.com{ 5475315Sstever@gmail.com dcachePort.printAddr(a); 5485315Sstever@gmail.com} 5495315Sstever@gmail.com 5505315Sstever@gmail.com 5512623SN/A//////////////////////////////////////////////////////////////////////// 5522623SN/A// 5532623SN/A// AtomicSimpleCPU Simulation Object 5542623SN/A// 5554762Snate@binkert.orgAtomicSimpleCPU * 5564762Snate@binkert.orgAtomicSimpleCPUParams::create() 5572623SN/A{ 5585529Snate@binkert.org numThreads = 1; 5598779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 5604762Snate@binkert.org panic("only one workload allowed"); 5615529Snate@binkert.org return new AtomicSimpleCPU(this); 5622623SN/A} 563