atomic.cc revision 8779
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 328105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 368229Snate@binkert.org#include "cpu/simple/atomic.hh" 372623SN/A#include "cpu/exetrace.hh" 388232Snate@binkert.org#include "debug/ExecFaulting.hh" 398232Snate@binkert.org#include "debug/SimpleCPU.hh" 403348Sbinkertn@umich.edu#include "mem/packet.hh" 413348Sbinkertn@umich.edu#include "mem/packet_access.hh" 424762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 437678Sgblack@eecs.umich.edu#include "sim/faults.hh" 442901Ssaidi@eecs.umich.edu#include "sim/system.hh" 458779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 462623SN/A 472623SN/Ausing namespace std; 482623SN/Ausing namespace TheISA; 492623SN/A 502623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 515606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 522623SN/A{ 532623SN/A} 542623SN/A 552623SN/A 562623SN/Avoid 572623SN/AAtomicSimpleCPU::TickEvent::process() 582623SN/A{ 592623SN/A cpu->tick(); 602623SN/A} 612623SN/A 622623SN/Aconst char * 635336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 642623SN/A{ 654873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 662623SN/A} 672623SN/A 682856Srdreslin@umich.eduPort * 696227Snate@binkert.orgAtomicSimpleCPU::getPort(const string &if_name, int idx) 702856Srdreslin@umich.edu{ 712856Srdreslin@umich.edu if (if_name == "dcache_port") 722856Srdreslin@umich.edu return &dcachePort; 732856Srdreslin@umich.edu else if (if_name == "icache_port") 742856Srdreslin@umich.edu return &icachePort; 754968Sacolyte@umich.edu else if (if_name == "physmem_port") { 764968Sacolyte@umich.edu hasPhysMemPort = true; 774968Sacolyte@umich.edu return &physmemPort; 784968Sacolyte@umich.edu } 792856Srdreslin@umich.edu else 802856Srdreslin@umich.edu panic("No Such Port\n"); 812856Srdreslin@umich.edu} 822623SN/A 832623SN/Avoid 842623SN/AAtomicSimpleCPU::init() 852623SN/A{ 862623SN/A BaseCPU::init(); 878779Sgblack@eecs.umich.edu if (FullSystem) { 888779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 898779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 902623SN/A#if FULL_SYSTEM 918779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 928779Sgblack@eecs.umich.edu // initialize CPU, including PC 938779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 948779Sgblack@eecs.umich.edu#endif 958779Sgblack@eecs.umich.edu } 962623SN/A } 974968Sacolyte@umich.edu if (hasPhysMemPort) { 984968Sacolyte@umich.edu bool snoop = false; 994968Sacolyte@umich.edu AddrRangeList pmAddrList; 1004968Sacolyte@umich.edu physmemPort.getPeerAddressRanges(pmAddrList, snoop); 1014968Sacolyte@umich.edu physMemAddr = *pmAddrList.begin(); 1024968Sacolyte@umich.edu } 1035714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1045712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1055712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1065712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1072623SN/A} 1082623SN/A 1092623SN/Abool 1103349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 1112623SN/A{ 1123184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 1132623SN/A return true; 1142623SN/A} 1152623SN/A 1162623SN/ATick 1173349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 1182623SN/A{ 1193310Srdreslin@umich.edu //Snooping a coherence request, just return 1203649Srdreslin@umich.edu return 0; 1212623SN/A} 1222623SN/A 1232623SN/Avoid 1243349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1252623SN/A{ 1263184Srdreslin@umich.edu //No internal storage to update, just return 1273184Srdreslin@umich.edu return; 1282623SN/A} 1292623SN/A 1302623SN/Avoid 1312623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1322623SN/A{ 1333647Srdreslin@umich.edu if (status == RangeChange) { 1343647Srdreslin@umich.edu if (!snoopRangeSent) { 1353647Srdreslin@umich.edu snoopRangeSent = true; 1363647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1373647Srdreslin@umich.edu } 1382626SN/A return; 1393647Srdreslin@umich.edu } 1402626SN/A 1412623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1422623SN/A} 1432623SN/A 1442657Ssaidi@eecs.umich.eduvoid 1452623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1462623SN/A{ 1472623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1482623SN/A} 1492623SN/A 1504192Sktlim@umich.eduvoid 1514192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port) 1524192Sktlim@umich.edu{ 1534192Sktlim@umich.edu Port::setPeer(port); 1544192Sktlim@umich.edu 1558779Sgblack@eecs.umich.edu if (FullSystem) { 1568779Sgblack@eecs.umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 1578779Sgblack@eecs.umich.edu // Ports) 1588779Sgblack@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 1598779Sgblack@eecs.umich.edu } 1604192Sktlim@umich.edu} 1612623SN/A 1625529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1636078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1645487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1655487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1664968Sacolyte@umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1674968Sacolyte@umich.edu physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1682623SN/A{ 1692623SN/A _status = Idle; 1702623SN/A 1713647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1723647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1733647Srdreslin@umich.edu 1742623SN/A} 1752623SN/A 1762623SN/A 1772623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1782623SN/A{ 1796775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1806775SBrad.Beckmann@amd.com deschedule(tickEvent); 1816775SBrad.Beckmann@amd.com } 1822623SN/A} 1832623SN/A 1842623SN/Avoid 1852623SN/AAtomicSimpleCPU::serialize(ostream &os) 1862623SN/A{ 1872915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1882915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1896078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1903145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1912623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1922623SN/A tickEvent.serialize(os); 1932623SN/A} 1942623SN/A 1952623SN/Avoid 1962623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1972623SN/A{ 1982915Sktlim@umich.edu SimObject::State so_state; 1992915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 2006078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 2013145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 2022915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 2032915Sktlim@umich.edu} 2042915Sktlim@umich.edu 2052915Sktlim@umich.eduvoid 2062915Sktlim@umich.eduAtomicSimpleCPU::resume() 2072915Sktlim@umich.edu{ 2085220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 2095220Ssaidi@eecs.umich.edu return; 2105220Ssaidi@eecs.umich.edu 2114940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 2125220Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 2133324Shsul@eecs.umich.edu 2145220Ssaidi@eecs.umich.edu changeState(SimObject::Running); 2155220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 2165606Snate@binkert.org if (!tickEvent.scheduled()) 2175606Snate@binkert.org schedule(tickEvent, nextCycle()); 2182915Sktlim@umich.edu } 2197897Shestness@cs.utexas.edu system->totalNumInsts = 0; 2202623SN/A} 2212623SN/A 2222623SN/Avoid 2232798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2242623SN/A{ 2255496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 2262798Sktlim@umich.edu _status = SwitchedOut; 2272623SN/A 2282798Sktlim@umich.edu tickEvent.squash(); 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2332623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2342623SN/A{ 2354192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2362623SN/A 2372623SN/A assert(!tickEvent.scheduled()); 2382623SN/A 2392680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2402623SN/A // running and schedule its tick event. 2416221Snate@binkert.org ThreadID size = threadContexts.size(); 2426221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 2432680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2442680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2452623SN/A _status = Running; 2465606Snate@binkert.org schedule(tickEvent, nextCycle()); 2472623SN/A break; 2482623SN/A } 2492623SN/A } 2503512Sktlim@umich.edu if (_status != Running) { 2513512Sktlim@umich.edu _status = Idle; 2523512Sktlim@umich.edu } 2535169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2545712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2555712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2565712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2572623SN/A} 2582623SN/A 2592623SN/A 2602623SN/Avoid 2612623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2622623SN/A{ 2634940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2644940Snate@binkert.org 2652623SN/A assert(thread_num == 0); 2662683Sktlim@umich.edu assert(thread); 2672623SN/A 2682623SN/A assert(_status == Idle); 2692623SN/A assert(!tickEvent.scheduled()); 2702623SN/A 2712623SN/A notIdleFraction++; 2725101Ssaidi@eecs.umich.edu numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 2733686Sktlim@umich.edu 2743430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2757823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2762623SN/A _status = Running; 2772623SN/A} 2782623SN/A 2792623SN/A 2802623SN/Avoid 2812623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2822623SN/A{ 2834940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2844940Snate@binkert.org 2852623SN/A assert(thread_num == 0); 2862683Sktlim@umich.edu assert(thread); 2872623SN/A 2886043Sgblack@eecs.umich.edu if (_status == Idle) 2896043Sgblack@eecs.umich.edu return; 2906043Sgblack@eecs.umich.edu 2912623SN/A assert(_status == Running); 2922626SN/A 2932626SN/A // tick event may not be scheduled if this gets called from inside 2942626SN/A // an instruction's execution, e.g. "quiesce" 2952626SN/A if (tickEvent.scheduled()) 2965606Snate@binkert.org deschedule(tickEvent); 2972623SN/A 2982623SN/A notIdleFraction--; 2992623SN/A _status = Idle; 3002623SN/A} 3012623SN/A 3022623SN/A 3032623SN/AFault 3048444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3058444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3062623SN/A{ 3073169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3084870Sstever@eecs.umich.edu Request *req = &data_read_req; 3092623SN/A 3102623SN/A if (traceData) { 3112623SN/A traceData->setAddr(addr); 3122623SN/A } 3132623SN/A 3144999Sgblack@eecs.umich.edu //The block size of our peer. 3156227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3164999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3177520Sgblack@eecs.umich.edu int fullSize = size; 3182623SN/A 3194999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3204999Sgblack@eecs.umich.edu //across a cache line boundary. 3217520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3224999Sgblack@eecs.umich.edu 3237520Sgblack@eecs.umich.edu if (secondAddr > addr) 3247520Sgblack@eecs.umich.edu size = secondAddr - addr; 3254999Sgblack@eecs.umich.edu 3264999Sgblack@eecs.umich.edu dcache_latency = 0; 3274999Sgblack@eecs.umich.edu 3287520Sgblack@eecs.umich.edu while (1) { 3297720Sgblack@eecs.umich.edu req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); 3304999Sgblack@eecs.umich.edu 3314999Sgblack@eecs.umich.edu // translate to physical address 3326023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3334999Sgblack@eecs.umich.edu 3344999Sgblack@eecs.umich.edu // Now do the access. 3356623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 3364999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 3376102Sgblack@eecs.umich.edu req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 3384999Sgblack@eecs.umich.edu Packet::Broadcast); 3397520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3404999Sgblack@eecs.umich.edu 3418105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3424999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3434999Sgblack@eecs.umich.edu else { 3444999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 3454999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 3464999Sgblack@eecs.umich.edu else 3474999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3484999Sgblack@eecs.umich.edu } 3494999Sgblack@eecs.umich.edu dcache_access = true; 3505012Sgblack@eecs.umich.edu 3514999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3524999Sgblack@eecs.umich.edu 3536102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3544999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3554999Sgblack@eecs.umich.edu } 3564968Sacolyte@umich.edu } 3574986Ssaidi@eecs.umich.edu 3584999Sgblack@eecs.umich.edu //If there's a fault, return it 3596739Sgblack@eecs.umich.edu if (fault != NoFault) { 3606739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3616739Sgblack@eecs.umich.edu return NoFault; 3626739Sgblack@eecs.umich.edu } else { 3636739Sgblack@eecs.umich.edu return fault; 3646739Sgblack@eecs.umich.edu } 3656739Sgblack@eecs.umich.edu } 3666739Sgblack@eecs.umich.edu 3674999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3684999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3694999Sgblack@eecs.umich.edu { 3706078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3716078Sgblack@eecs.umich.edu assert(!locked); 3726078Sgblack@eecs.umich.edu locked = true; 3736078Sgblack@eecs.umich.edu } 3744999Sgblack@eecs.umich.edu return fault; 3754968Sacolyte@umich.edu } 3763170Sstever@eecs.umich.edu 3774999Sgblack@eecs.umich.edu /* 3784999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3794999Sgblack@eecs.umich.edu */ 3804999Sgblack@eecs.umich.edu 3814999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3827520Sgblack@eecs.umich.edu data += size; 3834999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3847520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3854999Sgblack@eecs.umich.edu //And access the right address. 3864999Sgblack@eecs.umich.edu addr = secondAddr; 3872623SN/A } 3882623SN/A} 3892623SN/A 3907520Sgblack@eecs.umich.edu 3912623SN/AFault 3928444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3938444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3942623SN/A{ 3953169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3964870Sstever@eecs.umich.edu Request *req = &data_write_req; 3972623SN/A 3982623SN/A if (traceData) { 3992623SN/A traceData->setAddr(addr); 4002623SN/A } 4012623SN/A 4024999Sgblack@eecs.umich.edu //The block size of our peer. 4036227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 4044999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4057520Sgblack@eecs.umich.edu int fullSize = size; 4062623SN/A 4074999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4084999Sgblack@eecs.umich.edu //across a cache line boundary. 4097520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 4104999Sgblack@eecs.umich.edu 4114999Sgblack@eecs.umich.edu if(secondAddr > addr) 4127520Sgblack@eecs.umich.edu size = secondAddr - addr; 4134999Sgblack@eecs.umich.edu 4144999Sgblack@eecs.umich.edu dcache_latency = 0; 4154999Sgblack@eecs.umich.edu 4164999Sgblack@eecs.umich.edu while(1) { 4177720Sgblack@eecs.umich.edu req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); 4184999Sgblack@eecs.umich.edu 4194999Sgblack@eecs.umich.edu // translate to physical address 4206023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4214999Sgblack@eecs.umich.edu 4224999Sgblack@eecs.umich.edu // Now do the access. 4234999Sgblack@eecs.umich.edu if (fault == NoFault) { 4244999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4254999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4264999Sgblack@eecs.umich.edu 4276102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4284999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 4294999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 4304999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4314999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4324999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4334999Sgblack@eecs.umich.edu assert(res); 4344999Sgblack@eecs.umich.edu req->setExtraData(*res); 4354999Sgblack@eecs.umich.edu } 4364999Sgblack@eecs.umich.edu } 4374999Sgblack@eecs.umich.edu 4386623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4394999Sgblack@eecs.umich.edu Packet pkt = Packet(req, cmd, Packet::Broadcast); 4407520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4414999Sgblack@eecs.umich.edu 4428105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4434999Sgblack@eecs.umich.edu dcache_latency += 4444999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4454999Sgblack@eecs.umich.edu } else { 4464999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 4474999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 4484999Sgblack@eecs.umich.edu else 4494999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4504999Sgblack@eecs.umich.edu } 4514999Sgblack@eecs.umich.edu dcache_access = true; 4524999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4534999Sgblack@eecs.umich.edu 4544999Sgblack@eecs.umich.edu if (req->isSwap()) { 4554999Sgblack@eecs.umich.edu assert(res); 4567520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 4574999Sgblack@eecs.umich.edu } 4584999Sgblack@eecs.umich.edu } 4594999Sgblack@eecs.umich.edu 4604999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4614999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4624878Sstever@eecs.umich.edu } 4634040Ssaidi@eecs.umich.edu } 4644040Ssaidi@eecs.umich.edu 4654999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4664999Sgblack@eecs.umich.edu //stop now. 4674999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4684999Sgblack@eecs.umich.edu { 4696078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4706078Sgblack@eecs.umich.edu assert(locked); 4716078Sgblack@eecs.umich.edu locked = false; 4726078Sgblack@eecs.umich.edu } 4736739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4746739Sgblack@eecs.umich.edu return NoFault; 4756739Sgblack@eecs.umich.edu } else { 4766739Sgblack@eecs.umich.edu return fault; 4776739Sgblack@eecs.umich.edu } 4783170Sstever@eecs.umich.edu } 4793170Sstever@eecs.umich.edu 4804999Sgblack@eecs.umich.edu /* 4814999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4824999Sgblack@eecs.umich.edu */ 4834999Sgblack@eecs.umich.edu 4844999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4857520Sgblack@eecs.umich.edu data += size; 4864999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4877520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4884999Sgblack@eecs.umich.edu //And access the right address. 4894999Sgblack@eecs.umich.edu addr = secondAddr; 4902623SN/A } 4912623SN/A} 4922623SN/A 4932623SN/A 4942623SN/Avoid 4952623SN/AAtomicSimpleCPU::tick() 4962623SN/A{ 4974940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4984940Snate@binkert.org 4995487Snate@binkert.org Tick latency = 0; 5002623SN/A 5016078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5022623SN/A numCycles++; 5032623SN/A 5043387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5053387Sgblack@eecs.umich.edu checkForInterrupts(); 5062626SN/A 5075348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5088143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5098143SAli.Saidi@ARM.com if (_status == Idle) 5108143SAli.Saidi@ARM.com return; 5115348Ssaidi@eecs.umich.edu 5125669Sgblack@eecs.umich.edu Fault fault = NoFault; 5135669Sgblack@eecs.umich.edu 5147720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5157720Sgblack@eecs.umich.edu 5167720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5177720Sgblack@eecs.umich.edu !curMacroStaticInst; 5187720Sgblack@eecs.umich.edu if (needToFetch) { 5195894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 5206023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 5216023Snate@binkert.org BaseTLB::Execute); 5225894Sgblack@eecs.umich.edu } 5232623SN/A 5242623SN/A if (fault == NoFault) { 5254182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5264182Sgblack@eecs.umich.edu bool icache_access = false; 5274182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5282662Sstever@eecs.umich.edu 5297720Sgblack@eecs.umich.edu if (needToFetch) { 5305694Sgblack@eecs.umich.edu // This is commented out because the predecoder would act like 5315694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5325694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5335694Sgblack@eecs.umich.edu // this code should be uncommented. 5345669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5355669Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 5365669Sgblack@eecs.umich.edu //{ 5375669Sgblack@eecs.umich.edu icache_access = true; 5385669Sgblack@eecs.umich.edu Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 5395669Sgblack@eecs.umich.edu Packet::Broadcast); 5405669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5412623SN/A 5425669Sgblack@eecs.umich.edu if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 5435669Sgblack@eecs.umich.edu icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 5445669Sgblack@eecs.umich.edu else 5455669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5464968Sacolyte@umich.edu 5475669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5484968Sacolyte@umich.edu 5495669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5505669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5515669Sgblack@eecs.umich.edu //} 5525669Sgblack@eecs.umich.edu } 5534182Sgblack@eecs.umich.edu 5542623SN/A preExecute(); 5553814Ssaidi@eecs.umich.edu 5565001Sgblack@eecs.umich.edu if (curStaticInst) { 5574182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5584998Sgblack@eecs.umich.edu 5594998Sgblack@eecs.umich.edu // keep an instruction count 5604998Sgblack@eecs.umich.edu if (fault == NoFault) 5614998Sgblack@eecs.umich.edu countInst(); 5627655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5635001Sgblack@eecs.umich.edu delete traceData; 5645001Sgblack@eecs.umich.edu traceData = NULL; 5655001Sgblack@eecs.umich.edu } 5664998Sgblack@eecs.umich.edu 5674182Sgblack@eecs.umich.edu postExecute(); 5684182Sgblack@eecs.umich.edu } 5692623SN/A 5703814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5714539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5724539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5733814Ssaidi@eecs.umich.edu instCnt++; 5743814Ssaidi@eecs.umich.edu 5755487Snate@binkert.org Tick stall_ticks = 0; 5765487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5775487Snate@binkert.org stall_ticks += icache_latency; 5785487Snate@binkert.org 5795487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5805487Snate@binkert.org stall_ticks += dcache_latency; 5815487Snate@binkert.org 5825487Snate@binkert.org if (stall_ticks) { 5835487Snate@binkert.org Tick stall_cycles = stall_ticks / ticks(1); 5845487Snate@binkert.org Tick aligned_stall_ticks = ticks(stall_cycles); 5855487Snate@binkert.org 5865487Snate@binkert.org if (aligned_stall_ticks < stall_ticks) 5875487Snate@binkert.org aligned_stall_ticks += 1; 5885487Snate@binkert.org 5895487Snate@binkert.org latency += aligned_stall_ticks; 5902623SN/A } 5912623SN/A 5922623SN/A } 5934377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5944182Sgblack@eecs.umich.edu advancePC(fault); 5952623SN/A } 5962623SN/A 5975487Snate@binkert.org // instruction takes at least one cycle 5985487Snate@binkert.org if (latency < ticks(1)) 5995487Snate@binkert.org latency = ticks(1); 6005487Snate@binkert.org 6012626SN/A if (_status != Idle) 6027823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 6032623SN/A} 6042623SN/A 6052623SN/A 6065315Sstever@gmail.comvoid 6075315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6085315Sstever@gmail.com{ 6095315Sstever@gmail.com dcachePort.printAddr(a); 6105315Sstever@gmail.com} 6115315Sstever@gmail.com 6125315Sstever@gmail.com 6132623SN/A//////////////////////////////////////////////////////////////////////// 6142623SN/A// 6152623SN/A// AtomicSimpleCPU Simulation Object 6162623SN/A// 6174762Snate@binkert.orgAtomicSimpleCPU * 6184762Snate@binkert.orgAtomicSimpleCPUParams::create() 6192623SN/A{ 6205529Snate@binkert.org numThreads = 1; 6215529Snate@binkert.org#if !FULL_SYSTEM 6228779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 6234762Snate@binkert.org panic("only one workload allowed"); 6242623SN/A#endif 6255529Snate@binkert.org return new AtomicSimpleCPU(this); 6262623SN/A} 627