atomic.cc revision 8232 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmapped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/simple/atomic.hh"
37#include "cpu/exetrace.hh"
38#include "debug/ExecFaulting.hh"
39#include "debug/SimpleCPU.hh"
40#include "mem/packet.hh"
41#include "mem/packet_access.hh"
42#include "params/AtomicSimpleCPU.hh"
43#include "sim/faults.hh"
44#include "sim/system.hh"
45
46using namespace std;
47using namespace TheISA;
48
49AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
50    : Event(CPU_Tick_Pri), cpu(c)
51{
52}
53
54
55void
56AtomicSimpleCPU::TickEvent::process()
57{
58    cpu->tick();
59}
60
61const char *
62AtomicSimpleCPU::TickEvent::description() const
63{
64    return "AtomicSimpleCPU tick";
65}
66
67Port *
68AtomicSimpleCPU::getPort(const string &if_name, int idx)
69{
70    if (if_name == "dcache_port")
71        return &dcachePort;
72    else if (if_name == "icache_port")
73        return &icachePort;
74    else if (if_name == "physmem_port") {
75        hasPhysMemPort = true;
76        return &physmemPort;
77    }
78    else
79        panic("No Such Port\n");
80}
81
82void
83AtomicSimpleCPU::init()
84{
85    BaseCPU::init();
86#if FULL_SYSTEM
87    ThreadID size = threadContexts.size();
88    for (ThreadID i = 0; i < size; ++i) {
89        ThreadContext *tc = threadContexts[i];
90
91        // initialize CPU, including PC
92        TheISA::initCPU(tc, tc->contextId());
93    }
94#endif
95    if (hasPhysMemPort) {
96        bool snoop = false;
97        AddrRangeList pmAddrList;
98        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
99        physMemAddr = *pmAddrList.begin();
100    }
101    // Atomic doesn't do MT right now, so contextId == threadId
102    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
103    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
104    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
105}
106
107bool
108AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
109{
110    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
111    return true;
112}
113
114Tick
115AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
116{
117    //Snooping a coherence request, just return
118    return 0;
119}
120
121void
122AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
123{
124    //No internal storage to update, just return
125    return;
126}
127
128void
129AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
130{
131    if (status == RangeChange) {
132        if (!snoopRangeSent) {
133            snoopRangeSent = true;
134            sendStatusChange(Port::RangeChange);
135        }
136        return;
137    }
138
139    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
140}
141
142void
143AtomicSimpleCPU::CpuPort::recvRetry()
144{
145    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
146}
147
148void
149AtomicSimpleCPU::DcachePort::setPeer(Port *port)
150{
151    Port::setPeer(port);
152
153#if FULL_SYSTEM
154    // Update the ThreadContext's memory ports (Functional/Virtual
155    // Ports)
156    cpu->tcBase()->connectMemPorts(cpu->tcBase());
157#endif
158}
159
160AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
161    : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
162      simulate_data_stalls(p->simulate_data_stalls),
163      simulate_inst_stalls(p->simulate_inst_stalls),
164      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
165      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
166{
167    _status = Idle;
168
169    icachePort.snoopRangeSent = false;
170    dcachePort.snoopRangeSent = false;
171
172}
173
174
175AtomicSimpleCPU::~AtomicSimpleCPU()
176{
177    if (tickEvent.scheduled()) {
178        deschedule(tickEvent);
179    }
180}
181
182void
183AtomicSimpleCPU::serialize(ostream &os)
184{
185    SimObject::State so_state = SimObject::getState();
186    SERIALIZE_ENUM(so_state);
187    SERIALIZE_SCALAR(locked);
188    BaseSimpleCPU::serialize(os);
189    nameOut(os, csprintf("%s.tickEvent", name()));
190    tickEvent.serialize(os);
191}
192
193void
194AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
195{
196    SimObject::State so_state;
197    UNSERIALIZE_ENUM(so_state);
198    UNSERIALIZE_SCALAR(locked);
199    BaseSimpleCPU::unserialize(cp, section);
200    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
201}
202
203void
204AtomicSimpleCPU::resume()
205{
206    if (_status == Idle || _status == SwitchedOut)
207        return;
208
209    DPRINTF(SimpleCPU, "Resume\n");
210    assert(system->getMemoryMode() == Enums::atomic);
211
212    changeState(SimObject::Running);
213    if (thread->status() == ThreadContext::Active) {
214        if (!tickEvent.scheduled())
215            schedule(tickEvent, nextCycle());
216    }
217    system->totalNumInsts = 0;
218}
219
220void
221AtomicSimpleCPU::switchOut()
222{
223    assert(_status == Running || _status == Idle);
224    _status = SwitchedOut;
225
226    tickEvent.squash();
227}
228
229
230void
231AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
232{
233    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
234
235    assert(!tickEvent.scheduled());
236
237    // if any of this CPU's ThreadContexts are active, mark the CPU as
238    // running and schedule its tick event.
239    ThreadID size = threadContexts.size();
240    for (ThreadID i = 0; i < size; ++i) {
241        ThreadContext *tc = threadContexts[i];
242        if (tc->status() == ThreadContext::Active && _status != Running) {
243            _status = Running;
244            schedule(tickEvent, nextCycle());
245            break;
246        }
247    }
248    if (_status != Running) {
249        _status = Idle;
250    }
251    assert(threadContexts.size() == 1);
252    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
253    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
254    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
255}
256
257
258void
259AtomicSimpleCPU::activateContext(int thread_num, int delay)
260{
261    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
262
263    assert(thread_num == 0);
264    assert(thread);
265
266    assert(_status == Idle);
267    assert(!tickEvent.scheduled());
268
269    notIdleFraction++;
270    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
271
272    //Make sure ticks are still on multiples of cycles
273    schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
274    _status = Running;
275}
276
277
278void
279AtomicSimpleCPU::suspendContext(int thread_num)
280{
281    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
282
283    assert(thread_num == 0);
284    assert(thread);
285
286    if (_status == Idle)
287        return;
288
289    assert(_status == Running);
290
291    // tick event may not be scheduled if this gets called from inside
292    // an instruction's execution, e.g. "quiesce"
293    if (tickEvent.scheduled())
294        deschedule(tickEvent);
295
296    notIdleFraction--;
297    _status = Idle;
298}
299
300
301Fault
302AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
303                           unsigned size, unsigned flags)
304{
305    // use the CPU's statically allocated read request and packet objects
306    Request *req = &data_read_req;
307
308    if (traceData) {
309        traceData->setAddr(addr);
310    }
311
312    //The block size of our peer.
313    unsigned blockSize = dcachePort.peerBlockSize();
314    //The size of the data we're trying to read.
315    int fullSize = size;
316
317    //The address of the second part of this access if it needs to be split
318    //across a cache line boundary.
319    Addr secondAddr = roundDown(addr + size - 1, blockSize);
320
321    if (secondAddr > addr)
322        size = secondAddr - addr;
323
324    dcache_latency = 0;
325
326    while (1) {
327        req->setVirt(0, addr, size, flags, thread->pcState().instAddr());
328
329        // translate to physical address
330        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
331
332        // Now do the access.
333        if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
334            Packet pkt = Packet(req,
335                    req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
336                    Packet::Broadcast);
337            pkt.dataStatic(data);
338
339            if (req->isMmappedIpr())
340                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
341            else {
342                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
343                    dcache_latency += physmemPort.sendAtomic(&pkt);
344                else
345                    dcache_latency += dcachePort.sendAtomic(&pkt);
346            }
347            dcache_access = true;
348
349            assert(!pkt.isError());
350
351            if (req->isLLSC()) {
352                TheISA::handleLockedRead(thread, req);
353            }
354        }
355
356        //If there's a fault, return it
357        if (fault != NoFault) {
358            if (req->isPrefetch()) {
359                return NoFault;
360            } else {
361                return fault;
362            }
363        }
364
365        //If we don't need to access a second cache line, stop now.
366        if (secondAddr <= addr)
367        {
368            if (req->isLocked() && fault == NoFault) {
369                assert(!locked);
370                locked = true;
371            }
372            return fault;
373        }
374
375        /*
376         * Set up for accessing the second cache line.
377         */
378
379        //Move the pointer we're reading into to the correct location.
380        data += size;
381        //Adjust the size to get the remaining bytes.
382        size = addr + fullSize - secondAddr;
383        //And access the right address.
384        addr = secondAddr;
385    }
386}
387
388
389template <class T>
390Fault
391AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
392{
393    uint8_t *dataPtr = (uint8_t *)&data;
394    memset(dataPtr, 0, sizeof(data));
395    Fault fault = readBytes(addr, dataPtr, sizeof(data), flags);
396    if (fault == NoFault) {
397        data = gtoh(data);
398        if (traceData)
399            traceData->setData(data);
400    }
401    return fault;
402}
403
404#ifndef DOXYGEN_SHOULD_SKIP_THIS
405
406template
407Fault
408AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
409
410template
411Fault
412AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
413
414template
415Fault
416AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
417
418template
419Fault
420AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
421
422template
423Fault
424AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
425
426template
427Fault
428AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
429
430#endif //DOXYGEN_SHOULD_SKIP_THIS
431
432template<>
433Fault
434AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
435{
436    return read(addr, *(uint64_t*)&data, flags);
437}
438
439template<>
440Fault
441AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
442{
443    return read(addr, *(uint32_t*)&data, flags);
444}
445
446
447template<>
448Fault
449AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
450{
451    return read(addr, (uint32_t&)data, flags);
452}
453
454
455Fault
456AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
457                            Addr addr, unsigned flags, uint64_t *res)
458{
459    // use the CPU's statically allocated write request and packet objects
460    Request *req = &data_write_req;
461
462    if (traceData) {
463        traceData->setAddr(addr);
464    }
465
466    //The block size of our peer.
467    unsigned blockSize = dcachePort.peerBlockSize();
468    //The size of the data we're trying to read.
469    int fullSize = size;
470
471    //The address of the second part of this access if it needs to be split
472    //across a cache line boundary.
473    Addr secondAddr = roundDown(addr + size - 1, blockSize);
474
475    if(secondAddr > addr)
476        size = secondAddr - addr;
477
478    dcache_latency = 0;
479
480    while(1) {
481        req->setVirt(0, addr, size, flags, thread->pcState().instAddr());
482
483        // translate to physical address
484        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
485
486        // Now do the access.
487        if (fault == NoFault) {
488            MemCmd cmd = MemCmd::WriteReq; // default
489            bool do_access = true;  // flag to suppress cache access
490
491            if (req->isLLSC()) {
492                cmd = MemCmd::StoreCondReq;
493                do_access = TheISA::handleLockedWrite(thread, req);
494            } else if (req->isSwap()) {
495                cmd = MemCmd::SwapReq;
496                if (req->isCondSwap()) {
497                    assert(res);
498                    req->setExtraData(*res);
499                }
500            }
501
502            if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
503                Packet pkt = Packet(req, cmd, Packet::Broadcast);
504                pkt.dataStatic(data);
505
506                if (req->isMmappedIpr()) {
507                    dcache_latency +=
508                        TheISA::handleIprWrite(thread->getTC(), &pkt);
509                } else {
510                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
511                        dcache_latency += physmemPort.sendAtomic(&pkt);
512                    else
513                        dcache_latency += dcachePort.sendAtomic(&pkt);
514                }
515                dcache_access = true;
516                assert(!pkt.isError());
517
518                if (req->isSwap()) {
519                    assert(res);
520                    memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
521                }
522            }
523
524            if (res && !req->isSwap()) {
525                *res = req->getExtraData();
526            }
527        }
528
529        //If there's a fault or we don't need to access a second cache line,
530        //stop now.
531        if (fault != NoFault || secondAddr <= addr)
532        {
533            if (req->isLocked() && fault == NoFault) {
534                assert(locked);
535                locked = false;
536            }
537            if (fault != NoFault && req->isPrefetch()) {
538                return NoFault;
539            } else {
540                return fault;
541            }
542        }
543
544        /*
545         * Set up for accessing the second cache line.
546         */
547
548        //Move the pointer we're reading into to the correct location.
549        data += size;
550        //Adjust the size to get the remaining bytes.
551        size = addr + fullSize - secondAddr;
552        //And access the right address.
553        addr = secondAddr;
554    }
555}
556
557
558template <class T>
559Fault
560AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
561{
562    uint8_t *dataPtr = (uint8_t *)&data;
563    if (traceData)
564        traceData->setData(data);
565    data = htog(data);
566
567    Fault fault = writeBytes(dataPtr, sizeof(data), addr, flags, res);
568    if (fault == NoFault && data_write_req.isSwap()) {
569        *res = gtoh((T)*res);
570    }
571    return fault;
572}
573
574
575#ifndef DOXYGEN_SHOULD_SKIP_THIS
576
577template
578Fault
579AtomicSimpleCPU::write(Twin32_t data, Addr addr,
580                       unsigned flags, uint64_t *res);
581
582template
583Fault
584AtomicSimpleCPU::write(Twin64_t data, Addr addr,
585                       unsigned flags, uint64_t *res);
586
587template
588Fault
589AtomicSimpleCPU::write(uint64_t data, Addr addr,
590                       unsigned flags, uint64_t *res);
591
592template
593Fault
594AtomicSimpleCPU::write(uint32_t data, Addr addr,
595                       unsigned flags, uint64_t *res);
596
597template
598Fault
599AtomicSimpleCPU::write(uint16_t data, Addr addr,
600                       unsigned flags, uint64_t *res);
601
602template
603Fault
604AtomicSimpleCPU::write(uint8_t data, Addr addr,
605                       unsigned flags, uint64_t *res);
606
607#endif //DOXYGEN_SHOULD_SKIP_THIS
608
609template<>
610Fault
611AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
612{
613    return write(*(uint64_t*)&data, addr, flags, res);
614}
615
616template<>
617Fault
618AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
619{
620    return write(*(uint32_t*)&data, addr, flags, res);
621}
622
623
624template<>
625Fault
626AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
627{
628    return write((uint32_t)data, addr, flags, res);
629}
630
631
632void
633AtomicSimpleCPU::tick()
634{
635    DPRINTF(SimpleCPU, "Tick\n");
636
637    Tick latency = 0;
638
639    for (int i = 0; i < width || locked; ++i) {
640        numCycles++;
641
642        if (!curStaticInst || !curStaticInst->isDelayedCommit())
643            checkForInterrupts();
644
645        checkPcEventQueue();
646        // We must have just got suspended by a PC event
647        if (_status == Idle)
648            return;
649
650        Fault fault = NoFault;
651
652        TheISA::PCState pcState = thread->pcState();
653
654        bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
655                           !curMacroStaticInst;
656        if (needToFetch) {
657            setupFetchRequest(&ifetch_req);
658            fault = thread->itb->translateAtomic(&ifetch_req, tc,
659                                                 BaseTLB::Execute);
660        }
661
662        if (fault == NoFault) {
663            Tick icache_latency = 0;
664            bool icache_access = false;
665            dcache_access = false; // assume no dcache access
666
667            if (needToFetch) {
668                // This is commented out because the predecoder would act like
669                // a tiny cache otherwise. It wouldn't be flushed when needed
670                // like the I cache. It should be flushed, and when that works
671                // this code should be uncommented.
672                //Fetch more instruction memory if necessary
673                //if(predecoder.needMoreBytes())
674                //{
675                    icache_access = true;
676                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
677                                               Packet::Broadcast);
678                    ifetch_pkt.dataStatic(&inst);
679
680                    if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
681                        icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
682                    else
683                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
684
685                    assert(!ifetch_pkt.isError());
686
687                    // ifetch_req is initialized to read the instruction directly
688                    // into the CPU object's inst field.
689                //}
690            }
691
692            preExecute();
693
694            if (curStaticInst) {
695                fault = curStaticInst->execute(this, traceData);
696
697                // keep an instruction count
698                if (fault == NoFault)
699                    countInst();
700                else if (traceData && !DTRACE(ExecFaulting)) {
701                    delete traceData;
702                    traceData = NULL;
703                }
704
705                postExecute();
706            }
707
708            // @todo remove me after debugging with legion done
709            if (curStaticInst && (!curStaticInst->isMicroop() ||
710                        curStaticInst->isFirstMicroop()))
711                instCnt++;
712
713            Tick stall_ticks = 0;
714            if (simulate_inst_stalls && icache_access)
715                stall_ticks += icache_latency;
716
717            if (simulate_data_stalls && dcache_access)
718                stall_ticks += dcache_latency;
719
720            if (stall_ticks) {
721                Tick stall_cycles = stall_ticks / ticks(1);
722                Tick aligned_stall_ticks = ticks(stall_cycles);
723
724                if (aligned_stall_ticks < stall_ticks)
725                    aligned_stall_ticks += 1;
726
727                latency += aligned_stall_ticks;
728            }
729
730        }
731        if(fault != NoFault || !stayAtPC)
732            advancePC(fault);
733    }
734
735    // instruction takes at least one cycle
736    if (latency < ticks(1))
737        latency = ticks(1);
738
739    if (_status != Idle)
740        schedule(tickEvent, curTick() + latency);
741}
742
743
744void
745AtomicSimpleCPU::printAddr(Addr a)
746{
747    dcachePort.printAddr(a);
748}
749
750
751////////////////////////////////////////////////////////////////////////
752//
753//  AtomicSimpleCPU Simulation Object
754//
755AtomicSimpleCPU *
756AtomicSimpleCPUParams::create()
757{
758    numThreads = 1;
759#if !FULL_SYSTEM
760    if (workload.size() != 1)
761        panic("only one workload allowed");
762#endif
763    return new AtomicSimpleCPU(this);
764}
765