atomic.cc revision 6739
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
344040Ssaidi@eecs.umich.edu#include "base/bigint.hh"
356658Snate@binkert.org#include "config/the_isa.hh"
362623SN/A#include "cpu/exetrace.hh"
372623SN/A#include "cpu/simple/atomic.hh"
383348Sbinkertn@umich.edu#include "mem/packet.hh"
393348Sbinkertn@umich.edu#include "mem/packet_access.hh"
404762Snate@binkert.org#include "params/AtomicSimpleCPU.hh"
412901Ssaidi@eecs.umich.edu#include "sim/system.hh"
422623SN/A
432623SN/Ausing namespace std;
442623SN/Ausing namespace TheISA;
452623SN/A
462623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
475606Snate@binkert.org    : Event(CPU_Tick_Pri), cpu(c)
482623SN/A{
492623SN/A}
502623SN/A
512623SN/A
522623SN/Avoid
532623SN/AAtomicSimpleCPU::TickEvent::process()
542623SN/A{
552623SN/A    cpu->tick();
562623SN/A}
572623SN/A
582623SN/Aconst char *
595336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const
602623SN/A{
614873Sstever@eecs.umich.edu    return "AtomicSimpleCPU tick";
622623SN/A}
632623SN/A
642856Srdreslin@umich.eduPort *
656227Snate@binkert.orgAtomicSimpleCPU::getPort(const string &if_name, int idx)
662856Srdreslin@umich.edu{
672856Srdreslin@umich.edu    if (if_name == "dcache_port")
682856Srdreslin@umich.edu        return &dcachePort;
692856Srdreslin@umich.edu    else if (if_name == "icache_port")
702856Srdreslin@umich.edu        return &icachePort;
714968Sacolyte@umich.edu    else if (if_name == "physmem_port") {
724968Sacolyte@umich.edu        hasPhysMemPort = true;
734968Sacolyte@umich.edu        return &physmemPort;
744968Sacolyte@umich.edu    }
752856Srdreslin@umich.edu    else
762856Srdreslin@umich.edu        panic("No Such Port\n");
772856Srdreslin@umich.edu}
782623SN/A
792623SN/Avoid
802623SN/AAtomicSimpleCPU::init()
812623SN/A{
822623SN/A    BaseCPU::init();
832623SN/A#if FULL_SYSTEM
846221Snate@binkert.org    ThreadID size = threadContexts.size();
856221Snate@binkert.org    for (ThreadID i = 0; i < size; ++i) {
862680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
872623SN/A
882623SN/A        // initialize CPU, including PC
895714Shsul@eecs.umich.edu        TheISA::initCPU(tc, tc->contextId());
902623SN/A    }
912623SN/A#endif
924968Sacolyte@umich.edu    if (hasPhysMemPort) {
934968Sacolyte@umich.edu        bool snoop = false;
944968Sacolyte@umich.edu        AddrRangeList pmAddrList;
954968Sacolyte@umich.edu        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
964968Sacolyte@umich.edu        physMemAddr = *pmAddrList.begin();
974968Sacolyte@umich.edu    }
985714Shsul@eecs.umich.edu    // Atomic doesn't do MT right now, so contextId == threadId
995712Shsul@eecs.umich.edu    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
1005712Shsul@eecs.umich.edu    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
1015712Shsul@eecs.umich.edu    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
1022623SN/A}
1032623SN/A
1042623SN/Abool
1053349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
1062623SN/A{
1073184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
1082623SN/A    return true;
1092623SN/A}
1102623SN/A
1112623SN/ATick
1123349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
1132623SN/A{
1143310Srdreslin@umich.edu    //Snooping a coherence request, just return
1153649Srdreslin@umich.edu    return 0;
1162623SN/A}
1172623SN/A
1182623SN/Avoid
1193349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1202623SN/A{
1213184Srdreslin@umich.edu    //No internal storage to update, just return
1223184Srdreslin@umich.edu    return;
1232623SN/A}
1242623SN/A
1252623SN/Avoid
1262623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1272623SN/A{
1283647Srdreslin@umich.edu    if (status == RangeChange) {
1293647Srdreslin@umich.edu        if (!snoopRangeSent) {
1303647Srdreslin@umich.edu            snoopRangeSent = true;
1313647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1323647Srdreslin@umich.edu        }
1332626SN/A        return;
1343647Srdreslin@umich.edu    }
1352626SN/A
1362623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1372623SN/A}
1382623SN/A
1392657Ssaidi@eecs.umich.eduvoid
1402623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1412623SN/A{
1422623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1432623SN/A}
1442623SN/A
1454192Sktlim@umich.eduvoid
1464192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port)
1474192Sktlim@umich.edu{
1484192Sktlim@umich.edu    Port::setPeer(port);
1494192Sktlim@umich.edu
1504192Sktlim@umich.edu#if FULL_SYSTEM
1514192Sktlim@umich.edu    // Update the ThreadContext's memory ports (Functional/Virtual
1524192Sktlim@umich.edu    // Ports)
1535497Ssaidi@eecs.umich.edu    cpu->tcBase()->connectMemPorts(cpu->tcBase());
1544192Sktlim@umich.edu#endif
1554192Sktlim@umich.edu}
1562623SN/A
1575529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
1586078Sgblack@eecs.umich.edu    : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
1595487Snate@binkert.org      simulate_data_stalls(p->simulate_data_stalls),
1605487Snate@binkert.org      simulate_inst_stalls(p->simulate_inst_stalls),
1614968Sacolyte@umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
1624968Sacolyte@umich.edu      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
1632623SN/A{
1642623SN/A    _status = Idle;
1652623SN/A
1663647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1673647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1683647Srdreslin@umich.edu
1692623SN/A}
1702623SN/A
1712623SN/A
1722623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1732623SN/A{
1742623SN/A}
1752623SN/A
1762623SN/Avoid
1772623SN/AAtomicSimpleCPU::serialize(ostream &os)
1782623SN/A{
1792915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1802915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1816078Sgblack@eecs.umich.edu    SERIALIZE_SCALAR(locked);
1823145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1832623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1842623SN/A    tickEvent.serialize(os);
1852623SN/A}
1862623SN/A
1872623SN/Avoid
1882623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1892623SN/A{
1902915Sktlim@umich.edu    SimObject::State so_state;
1912915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1926078Sgblack@eecs.umich.edu    UNSERIALIZE_SCALAR(locked);
1933145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1942915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1952915Sktlim@umich.edu}
1962915Sktlim@umich.edu
1972915Sktlim@umich.eduvoid
1982915Sktlim@umich.eduAtomicSimpleCPU::resume()
1992915Sktlim@umich.edu{
2005220Ssaidi@eecs.umich.edu    if (_status == Idle || _status == SwitchedOut)
2015220Ssaidi@eecs.umich.edu        return;
2025220Ssaidi@eecs.umich.edu
2034940Snate@binkert.org    DPRINTF(SimpleCPU, "Resume\n");
2045220Ssaidi@eecs.umich.edu    assert(system->getMemoryMode() == Enums::atomic);
2053324Shsul@eecs.umich.edu
2065220Ssaidi@eecs.umich.edu    changeState(SimObject::Running);
2075220Ssaidi@eecs.umich.edu    if (thread->status() == ThreadContext::Active) {
2085606Snate@binkert.org        if (!tickEvent.scheduled())
2095606Snate@binkert.org            schedule(tickEvent, nextCycle());
2102915Sktlim@umich.edu    }
2112623SN/A}
2122623SN/A
2132623SN/Avoid
2142798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2152623SN/A{
2165496Ssaidi@eecs.umich.edu    assert(_status == Running || _status == Idle);
2172798Sktlim@umich.edu    _status = SwitchedOut;
2182623SN/A
2192798Sktlim@umich.edu    tickEvent.squash();
2202623SN/A}
2212623SN/A
2222623SN/A
2232623SN/Avoid
2242623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2252623SN/A{
2264192Sktlim@umich.edu    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
2272623SN/A
2282623SN/A    assert(!tickEvent.scheduled());
2292623SN/A
2302680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2312623SN/A    // running and schedule its tick event.
2326221Snate@binkert.org    ThreadID size = threadContexts.size();
2336221Snate@binkert.org    for (ThreadID i = 0; i < size; ++i) {
2342680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2352680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2362623SN/A            _status = Running;
2375606Snate@binkert.org            schedule(tickEvent, nextCycle());
2382623SN/A            break;
2392623SN/A        }
2402623SN/A    }
2413512Sktlim@umich.edu    if (_status != Running) {
2423512Sktlim@umich.edu        _status = Idle;
2433512Sktlim@umich.edu    }
2445169Ssaidi@eecs.umich.edu    assert(threadContexts.size() == 1);
2455712Shsul@eecs.umich.edu    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
2465712Shsul@eecs.umich.edu    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
2475712Shsul@eecs.umich.edu    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
2482623SN/A}
2492623SN/A
2502623SN/A
2512623SN/Avoid
2522623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2532623SN/A{
2544940Snate@binkert.org    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
2554940Snate@binkert.org
2562623SN/A    assert(thread_num == 0);
2572683Sktlim@umich.edu    assert(thread);
2582623SN/A
2592623SN/A    assert(_status == Idle);
2602623SN/A    assert(!tickEvent.scheduled());
2612623SN/A
2622623SN/A    notIdleFraction++;
2635101Ssaidi@eecs.umich.edu    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
2643686Sktlim@umich.edu
2653430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2665606Snate@binkert.org    schedule(tickEvent, nextCycle(curTick + ticks(delay)));
2672623SN/A    _status = Running;
2682623SN/A}
2692623SN/A
2702623SN/A
2712623SN/Avoid
2722623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2732623SN/A{
2744940Snate@binkert.org    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
2754940Snate@binkert.org
2762623SN/A    assert(thread_num == 0);
2772683Sktlim@umich.edu    assert(thread);
2782623SN/A
2796043Sgblack@eecs.umich.edu    if (_status == Idle)
2806043Sgblack@eecs.umich.edu        return;
2816043Sgblack@eecs.umich.edu
2822623SN/A    assert(_status == Running);
2832626SN/A
2842626SN/A    // tick event may not be scheduled if this gets called from inside
2852626SN/A    // an instruction's execution, e.g. "quiesce"
2862626SN/A    if (tickEvent.scheduled())
2875606Snate@binkert.org        deschedule(tickEvent);
2882623SN/A
2892623SN/A    notIdleFraction--;
2902623SN/A    _status = Idle;
2912623SN/A}
2922623SN/A
2932623SN/A
2942623SN/Atemplate <class T>
2952623SN/AFault
2962623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2972623SN/A{
2983169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2994870Sstever@eecs.umich.edu    Request *req = &data_read_req;
3002623SN/A
3012623SN/A    if (traceData) {
3022623SN/A        traceData->setAddr(addr);
3032623SN/A    }
3042623SN/A
3054999Sgblack@eecs.umich.edu    //The block size of our peer.
3066227Snate@binkert.org    unsigned blockSize = dcachePort.peerBlockSize();
3074999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
3084999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
3092623SN/A
3104999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
3112623SN/A
3124999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3134999Sgblack@eecs.umich.edu    //across a cache line boundary.
3144999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
3154999Sgblack@eecs.umich.edu
3164999Sgblack@eecs.umich.edu    if(secondAddr > addr)
3174999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
3184999Sgblack@eecs.umich.edu
3194999Sgblack@eecs.umich.edu    dcache_latency = 0;
3204999Sgblack@eecs.umich.edu
3214999Sgblack@eecs.umich.edu    while(1) {
3224999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
3234999Sgblack@eecs.umich.edu
3244999Sgblack@eecs.umich.edu        // translate to physical address
3256023Snate@binkert.org        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
3264999Sgblack@eecs.umich.edu
3274999Sgblack@eecs.umich.edu        // Now do the access.
3286623Sgblack@eecs.umich.edu        if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
3294999Sgblack@eecs.umich.edu            Packet pkt = Packet(req,
3306102Sgblack@eecs.umich.edu                    req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
3314999Sgblack@eecs.umich.edu                    Packet::Broadcast);
3324999Sgblack@eecs.umich.edu            pkt.dataStatic(dataPtr);
3334999Sgblack@eecs.umich.edu
3344999Sgblack@eecs.umich.edu            if (req->isMmapedIpr())
3354999Sgblack@eecs.umich.edu                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
3364999Sgblack@eecs.umich.edu            else {
3374999Sgblack@eecs.umich.edu                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
3384999Sgblack@eecs.umich.edu                    dcache_latency += physmemPort.sendAtomic(&pkt);
3394999Sgblack@eecs.umich.edu                else
3404999Sgblack@eecs.umich.edu                    dcache_latency += dcachePort.sendAtomic(&pkt);
3414999Sgblack@eecs.umich.edu            }
3424999Sgblack@eecs.umich.edu            dcache_access = true;
3435012Sgblack@eecs.umich.edu
3444999Sgblack@eecs.umich.edu            assert(!pkt.isError());
3454999Sgblack@eecs.umich.edu
3466102Sgblack@eecs.umich.edu            if (req->isLLSC()) {
3474999Sgblack@eecs.umich.edu                TheISA::handleLockedRead(thread, req);
3484999Sgblack@eecs.umich.edu            }
3494968Sacolyte@umich.edu        }
3504986Ssaidi@eecs.umich.edu
3514999Sgblack@eecs.umich.edu        // This will need a new way to tell if it has a dcache attached.
3524999Sgblack@eecs.umich.edu        if (req->isUncacheable())
3534999Sgblack@eecs.umich.edu            recordEvent("Uncached Read");
3544762Snate@binkert.org
3554999Sgblack@eecs.umich.edu        //If there's a fault, return it
3566739Sgblack@eecs.umich.edu        if (fault != NoFault) {
3576739Sgblack@eecs.umich.edu            if (req->isPrefetch()) {
3586739Sgblack@eecs.umich.edu                return NoFault;
3596739Sgblack@eecs.umich.edu            } else {
3606739Sgblack@eecs.umich.edu                return fault;
3616739Sgblack@eecs.umich.edu            }
3626739Sgblack@eecs.umich.edu        }
3636739Sgblack@eecs.umich.edu
3644999Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
3654999Sgblack@eecs.umich.edu        if (secondAddr <= addr)
3664999Sgblack@eecs.umich.edu        {
3674999Sgblack@eecs.umich.edu            data = gtoh(data);
3685408Sgblack@eecs.umich.edu            if (traceData) {
3695408Sgblack@eecs.umich.edu                traceData->setData(data);
3705408Sgblack@eecs.umich.edu            }
3716078Sgblack@eecs.umich.edu            if (req->isLocked() && fault == NoFault) {
3726078Sgblack@eecs.umich.edu                assert(!locked);
3736078Sgblack@eecs.umich.edu                locked = true;
3746078Sgblack@eecs.umich.edu            }
3754999Sgblack@eecs.umich.edu            return fault;
3764968Sacolyte@umich.edu        }
3773170Sstever@eecs.umich.edu
3784999Sgblack@eecs.umich.edu        /*
3794999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
3804999Sgblack@eecs.umich.edu         */
3814999Sgblack@eecs.umich.edu
3824999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
3834999Sgblack@eecs.umich.edu        dataPtr += dataSize;
3844999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
3854999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
3864999Sgblack@eecs.umich.edu        //And access the right address.
3874999Sgblack@eecs.umich.edu        addr = secondAddr;
3882623SN/A    }
3892623SN/A}
3902623SN/A
3912623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3922623SN/A
3932623SN/Atemplate
3942623SN/AFault
3954115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
3964115Ssaidi@eecs.umich.edu
3974115Ssaidi@eecs.umich.edutemplate
3984115Ssaidi@eecs.umich.eduFault
3994040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
4004040Ssaidi@eecs.umich.edu
4014040Ssaidi@eecs.umich.edutemplate
4024040Ssaidi@eecs.umich.eduFault
4032623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
4042623SN/A
4052623SN/Atemplate
4062623SN/AFault
4072623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
4082623SN/A
4092623SN/Atemplate
4102623SN/AFault
4112623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
4122623SN/A
4132623SN/Atemplate
4142623SN/AFault
4152623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
4162623SN/A
4172623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4182623SN/A
4192623SN/Atemplate<>
4202623SN/AFault
4212623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
4222623SN/A{
4232623SN/A    return read(addr, *(uint64_t*)&data, flags);
4242623SN/A}
4252623SN/A
4262623SN/Atemplate<>
4272623SN/AFault
4282623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
4292623SN/A{
4302623SN/A    return read(addr, *(uint32_t*)&data, flags);
4312623SN/A}
4322623SN/A
4332623SN/A
4342623SN/Atemplate<>
4352623SN/AFault
4362623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
4372623SN/A{
4382623SN/A    return read(addr, (uint32_t&)data, flags);
4392623SN/A}
4402623SN/A
4412623SN/A
4422623SN/Atemplate <class T>
4432623SN/AFault
4442623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
4452623SN/A{
4463169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
4474870Sstever@eecs.umich.edu    Request *req = &data_write_req;
4482623SN/A
4492623SN/A    if (traceData) {
4502623SN/A        traceData->setAddr(addr);
4512623SN/A    }
4522623SN/A
4534999Sgblack@eecs.umich.edu    //The block size of our peer.
4546227Snate@binkert.org    unsigned blockSize = dcachePort.peerBlockSize();
4554999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
4564999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
4572623SN/A
4584999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
4592623SN/A
4604999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
4614999Sgblack@eecs.umich.edu    //across a cache line boundary.
4624999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
4634999Sgblack@eecs.umich.edu
4644999Sgblack@eecs.umich.edu    if(secondAddr > addr)
4654999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
4664999Sgblack@eecs.umich.edu
4674999Sgblack@eecs.umich.edu    dcache_latency = 0;
4684999Sgblack@eecs.umich.edu
4694999Sgblack@eecs.umich.edu    while(1) {
4704999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
4714999Sgblack@eecs.umich.edu
4724999Sgblack@eecs.umich.edu        // translate to physical address
4736023Snate@binkert.org        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
4744999Sgblack@eecs.umich.edu
4754999Sgblack@eecs.umich.edu        // Now do the access.
4764999Sgblack@eecs.umich.edu        if (fault == NoFault) {
4774999Sgblack@eecs.umich.edu            MemCmd cmd = MemCmd::WriteReq; // default
4784999Sgblack@eecs.umich.edu            bool do_access = true;  // flag to suppress cache access
4794999Sgblack@eecs.umich.edu
4806102Sgblack@eecs.umich.edu            if (req->isLLSC()) {
4814999Sgblack@eecs.umich.edu                cmd = MemCmd::StoreCondReq;
4824999Sgblack@eecs.umich.edu                do_access = TheISA::handleLockedWrite(thread, req);
4834999Sgblack@eecs.umich.edu            } else if (req->isSwap()) {
4844999Sgblack@eecs.umich.edu                cmd = MemCmd::SwapReq;
4854999Sgblack@eecs.umich.edu                if (req->isCondSwap()) {
4864999Sgblack@eecs.umich.edu                    assert(res);
4874999Sgblack@eecs.umich.edu                    req->setExtraData(*res);
4884999Sgblack@eecs.umich.edu                }
4894999Sgblack@eecs.umich.edu            }
4904999Sgblack@eecs.umich.edu
4916623Sgblack@eecs.umich.edu            if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
4924999Sgblack@eecs.umich.edu                Packet pkt = Packet(req, cmd, Packet::Broadcast);
4934999Sgblack@eecs.umich.edu                pkt.dataStatic(dataPtr);
4944999Sgblack@eecs.umich.edu
4954999Sgblack@eecs.umich.edu                if (req->isMmapedIpr()) {
4964999Sgblack@eecs.umich.edu                    dcache_latency +=
4974999Sgblack@eecs.umich.edu                        TheISA::handleIprWrite(thread->getTC(), &pkt);
4984999Sgblack@eecs.umich.edu                } else {
4994999Sgblack@eecs.umich.edu                    //XXX This needs to be outside of the loop in order to
5004999Sgblack@eecs.umich.edu                    //work properly for cache line boundary crossing
5014999Sgblack@eecs.umich.edu                    //accesses in transendian simulations.
5024999Sgblack@eecs.umich.edu                    data = htog(data);
5034999Sgblack@eecs.umich.edu                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
5044999Sgblack@eecs.umich.edu                        dcache_latency += physmemPort.sendAtomic(&pkt);
5054999Sgblack@eecs.umich.edu                    else
5064999Sgblack@eecs.umich.edu                        dcache_latency += dcachePort.sendAtomic(&pkt);
5074999Sgblack@eecs.umich.edu                }
5084999Sgblack@eecs.umich.edu                dcache_access = true;
5094999Sgblack@eecs.umich.edu                assert(!pkt.isError());
5104999Sgblack@eecs.umich.edu
5114999Sgblack@eecs.umich.edu                if (req->isSwap()) {
5124999Sgblack@eecs.umich.edu                    assert(res);
5134999Sgblack@eecs.umich.edu                    *res = pkt.get<T>();
5144999Sgblack@eecs.umich.edu                }
5154999Sgblack@eecs.umich.edu            }
5164999Sgblack@eecs.umich.edu
5174999Sgblack@eecs.umich.edu            if (res && !req->isSwap()) {
5184999Sgblack@eecs.umich.edu                *res = req->getExtraData();
5194878Sstever@eecs.umich.edu            }
5204040Ssaidi@eecs.umich.edu        }
5214040Ssaidi@eecs.umich.edu
5224999Sgblack@eecs.umich.edu        // This will need a new way to tell if it's hooked up to a cache or not.
5234999Sgblack@eecs.umich.edu        if (req->isUncacheable())
5244999Sgblack@eecs.umich.edu            recordEvent("Uncached Write");
5252631SN/A
5264999Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
5274999Sgblack@eecs.umich.edu        //stop now.
5284999Sgblack@eecs.umich.edu        if (fault != NoFault || secondAddr <= addr)
5294999Sgblack@eecs.umich.edu        {
5304999Sgblack@eecs.umich.edu            // If the write needs to have a fault on the access, consider
5314999Sgblack@eecs.umich.edu            // calling changeStatus() and changing it to "bad addr write"
5324999Sgblack@eecs.umich.edu            // or something.
5335408Sgblack@eecs.umich.edu            if (traceData) {
5346012Ssteve.reinhardt@amd.com                traceData->setData(gtoh(data));
5355408Sgblack@eecs.umich.edu            }
5366078Sgblack@eecs.umich.edu            if (req->isLocked() && fault == NoFault) {
5376078Sgblack@eecs.umich.edu                assert(locked);
5386078Sgblack@eecs.umich.edu                locked = false;
5396078Sgblack@eecs.umich.edu            }
5406739Sgblack@eecs.umich.edu            if (fault != NoFault && req->isPrefetch()) {
5416739Sgblack@eecs.umich.edu                return NoFault;
5426739Sgblack@eecs.umich.edu            } else {
5436739Sgblack@eecs.umich.edu                return fault;
5446739Sgblack@eecs.umich.edu            }
5453170Sstever@eecs.umich.edu        }
5463170Sstever@eecs.umich.edu
5474999Sgblack@eecs.umich.edu        /*
5484999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
5494999Sgblack@eecs.umich.edu         */
5504999Sgblack@eecs.umich.edu
5514999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
5524999Sgblack@eecs.umich.edu        dataPtr += dataSize;
5534999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
5544999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
5554999Sgblack@eecs.umich.edu        //And access the right address.
5564999Sgblack@eecs.umich.edu        addr = secondAddr;
5572623SN/A    }
5582623SN/A}
5592623SN/A
5602623SN/A
5612623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
5624224Sgblack@eecs.umich.edu
5634224Sgblack@eecs.umich.edutemplate
5644224Sgblack@eecs.umich.eduFault
5654224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr,
5664224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
5674224Sgblack@eecs.umich.edu
5684224Sgblack@eecs.umich.edutemplate
5694224Sgblack@eecs.umich.eduFault
5704224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr,
5714224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
5724224Sgblack@eecs.umich.edu
5732623SN/Atemplate
5742623SN/AFault
5752623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
5762623SN/A                       unsigned flags, uint64_t *res);
5772623SN/A
5782623SN/Atemplate
5792623SN/AFault
5802623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
5812623SN/A                       unsigned flags, uint64_t *res);
5822623SN/A
5832623SN/Atemplate
5842623SN/AFault
5852623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
5862623SN/A                       unsigned flags, uint64_t *res);
5872623SN/A
5882623SN/Atemplate
5892623SN/AFault
5902623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
5912623SN/A                       unsigned flags, uint64_t *res);
5922623SN/A
5932623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
5942623SN/A
5952623SN/Atemplate<>
5962623SN/AFault
5972623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
5982623SN/A{
5992623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
6002623SN/A}
6012623SN/A
6022623SN/Atemplate<>
6032623SN/AFault
6042623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
6052623SN/A{
6062623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
6072623SN/A}
6082623SN/A
6092623SN/A
6102623SN/Atemplate<>
6112623SN/AFault
6122623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
6132623SN/A{
6142623SN/A    return write((uint32_t)data, addr, flags, res);
6152623SN/A}
6162623SN/A
6172623SN/A
6182623SN/Avoid
6192623SN/AAtomicSimpleCPU::tick()
6202623SN/A{
6214940Snate@binkert.org    DPRINTF(SimpleCPU, "Tick\n");
6224940Snate@binkert.org
6235487Snate@binkert.org    Tick latency = 0;
6242623SN/A
6256078Sgblack@eecs.umich.edu    for (int i = 0; i < width || locked; ++i) {
6262623SN/A        numCycles++;
6272623SN/A
6283387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
6293387Sgblack@eecs.umich.edu            checkForInterrupts();
6302626SN/A
6315348Ssaidi@eecs.umich.edu        checkPcEventQueue();
6325348Ssaidi@eecs.umich.edu
6335669Sgblack@eecs.umich.edu        Fault fault = NoFault;
6345669Sgblack@eecs.umich.edu
6355669Sgblack@eecs.umich.edu        bool fromRom = isRomMicroPC(thread->readMicroPC());
6365914Sgblack@eecs.umich.edu        if (!fromRom && !curMacroStaticInst) {
6375894Sgblack@eecs.umich.edu            setupFetchRequest(&ifetch_req);
6386023Snate@binkert.org            fault = thread->itb->translateAtomic(&ifetch_req, tc,
6396023Snate@binkert.org                                                 BaseTLB::Execute);
6405894Sgblack@eecs.umich.edu        }
6412623SN/A
6422623SN/A        if (fault == NoFault) {
6434182Sgblack@eecs.umich.edu            Tick icache_latency = 0;
6444182Sgblack@eecs.umich.edu            bool icache_access = false;
6454182Sgblack@eecs.umich.edu            dcache_access = false; // assume no dcache access
6462662Sstever@eecs.umich.edu
6475914Sgblack@eecs.umich.edu            if (!fromRom && !curMacroStaticInst) {
6485694Sgblack@eecs.umich.edu                // This is commented out because the predecoder would act like
6495694Sgblack@eecs.umich.edu                // a tiny cache otherwise. It wouldn't be flushed when needed
6505694Sgblack@eecs.umich.edu                // like the I cache. It should be flushed, and when that works
6515694Sgblack@eecs.umich.edu                // this code should be uncommented.
6525669Sgblack@eecs.umich.edu                //Fetch more instruction memory if necessary
6535669Sgblack@eecs.umich.edu                //if(predecoder.needMoreBytes())
6545669Sgblack@eecs.umich.edu                //{
6555669Sgblack@eecs.umich.edu                    icache_access = true;
6565669Sgblack@eecs.umich.edu                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
6575669Sgblack@eecs.umich.edu                                               Packet::Broadcast);
6585669Sgblack@eecs.umich.edu                    ifetch_pkt.dataStatic(&inst);
6592623SN/A
6605669Sgblack@eecs.umich.edu                    if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
6615669Sgblack@eecs.umich.edu                        icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
6625669Sgblack@eecs.umich.edu                    else
6635669Sgblack@eecs.umich.edu                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
6644968Sacolyte@umich.edu
6655669Sgblack@eecs.umich.edu                    assert(!ifetch_pkt.isError());
6664968Sacolyte@umich.edu
6675669Sgblack@eecs.umich.edu                    // ifetch_req is initialized to read the instruction directly
6685669Sgblack@eecs.umich.edu                    // into the CPU object's inst field.
6695669Sgblack@eecs.umich.edu                //}
6705669Sgblack@eecs.umich.edu            }
6714182Sgblack@eecs.umich.edu
6722623SN/A            preExecute();
6733814Ssaidi@eecs.umich.edu
6745001Sgblack@eecs.umich.edu            if (curStaticInst) {
6754182Sgblack@eecs.umich.edu                fault = curStaticInst->execute(this, traceData);
6764998Sgblack@eecs.umich.edu
6774998Sgblack@eecs.umich.edu                // keep an instruction count
6784998Sgblack@eecs.umich.edu                if (fault == NoFault)
6794998Sgblack@eecs.umich.edu                    countInst();
6805001Sgblack@eecs.umich.edu                else if (traceData) {
6815001Sgblack@eecs.umich.edu                    // If there was a fault, we should trace this instruction.
6825001Sgblack@eecs.umich.edu                    delete traceData;
6835001Sgblack@eecs.umich.edu                    traceData = NULL;
6845001Sgblack@eecs.umich.edu                }
6854998Sgblack@eecs.umich.edu
6864182Sgblack@eecs.umich.edu                postExecute();
6874182Sgblack@eecs.umich.edu            }
6882623SN/A
6893814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
6904539Sgblack@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroop() ||
6914539Sgblack@eecs.umich.edu                        curStaticInst->isFirstMicroop()))
6923814Ssaidi@eecs.umich.edu                instCnt++;
6933814Ssaidi@eecs.umich.edu
6945487Snate@binkert.org            Tick stall_ticks = 0;
6955487Snate@binkert.org            if (simulate_inst_stalls && icache_access)
6965487Snate@binkert.org                stall_ticks += icache_latency;
6975487Snate@binkert.org
6985487Snate@binkert.org            if (simulate_data_stalls && dcache_access)
6995487Snate@binkert.org                stall_ticks += dcache_latency;
7005487Snate@binkert.org
7015487Snate@binkert.org            if (stall_ticks) {
7025487Snate@binkert.org                Tick stall_cycles = stall_ticks / ticks(1);
7035487Snate@binkert.org                Tick aligned_stall_ticks = ticks(stall_cycles);
7045487Snate@binkert.org
7055487Snate@binkert.org                if (aligned_stall_ticks < stall_ticks)
7065487Snate@binkert.org                    aligned_stall_ticks += 1;
7075487Snate@binkert.org
7085487Snate@binkert.org                latency += aligned_stall_ticks;
7092623SN/A            }
7102623SN/A
7112623SN/A        }
7124377Sgblack@eecs.umich.edu        if(fault != NoFault || !stayAtPC)
7134182Sgblack@eecs.umich.edu            advancePC(fault);
7142623SN/A    }
7152623SN/A
7165487Snate@binkert.org    // instruction takes at least one cycle
7175487Snate@binkert.org    if (latency < ticks(1))
7185487Snate@binkert.org        latency = ticks(1);
7195487Snate@binkert.org
7202626SN/A    if (_status != Idle)
7215606Snate@binkert.org        schedule(tickEvent, curTick + latency);
7222623SN/A}
7232623SN/A
7242623SN/A
7255315Sstever@gmail.comvoid
7265315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a)
7275315Sstever@gmail.com{
7285315Sstever@gmail.com    dcachePort.printAddr(a);
7295315Sstever@gmail.com}
7305315Sstever@gmail.com
7315315Sstever@gmail.com
7322623SN/A////////////////////////////////////////////////////////////////////////
7332623SN/A//
7342623SN/A//  AtomicSimpleCPU Simulation Object
7352623SN/A//
7364762Snate@binkert.orgAtomicSimpleCPU *
7374762Snate@binkert.orgAtomicSimpleCPUParams::create()
7382623SN/A{
7395529Snate@binkert.org    numThreads = 1;
7405529Snate@binkert.org#if !FULL_SYSTEM
7414762Snate@binkert.org    if (workload.size() != 1)
7424762Snate@binkert.org        panic("only one workload allowed");
7432623SN/A#endif
7445529Snate@binkert.org    return new AtomicSimpleCPU(this);
7452623SN/A}
746