atomic.cc revision 5408
12207SN/A/* 22207SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu */ 302207SN/A 312207SN/A#include "arch/locked_mem.hh" 322972Sgblack@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332207SN/A#include "arch/utility.hh" 342454SN/A#include "base/bigint.hh" 355759Shsul@eecs.umich.edu#include "cpu/exetrace.hh" 362454SN/A#include "cpu/simple/atomic.hh" 372680Sktlim@umich.edu#include "mem/packet.hh" 385759Shsul@eecs.umich.edu#include "mem/packet_access.hh" 395759Shsul@eecs.umich.edu#include "params/AtomicSimpleCPU.hh" 402474SN/A#include "sim/system.hh" 412207SN/A 422474SN/Ausing namespace std; 432474SN/Ausing namespace TheISA; 442474SN/A 455569Snate@binkert.orgAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 465569Snate@binkert.org : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 475154Sgblack@eecs.umich.edu{ 482474SN/A} 492474SN/A 502474SN/A 512474SN/Avoid 522474SN/AAtomicSimpleCPU::TickEvent::process() 532474SN/A{ 542474SN/A cpu->tick(); 552474SN/A} 562474SN/A 572474SN/Aconst char * 582474SN/AAtomicSimpleCPU::TickEvent::description() const 592474SN/A{ 602474SN/A return "AtomicSimpleCPU tick"; 612474SN/A} 622474SN/A 632474SN/APort * 642474SN/AAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 652474SN/A{ 665759Shsul@eecs.umich.edu if (if_name == "dcache_port") 675759Shsul@eecs.umich.edu return &dcachePort; 685759Shsul@eecs.umich.edu else if (if_name == "icache_port") 695759Shsul@eecs.umich.edu return &icachePort; 705771Shsul@eecs.umich.edu else if (if_name == "physmem_port") { 715759Shsul@eecs.umich.edu hasPhysMemPort = true; 725759Shsul@eecs.umich.edu return &physmemPort; 735759Shsul@eecs.umich.edu } 745759Shsul@eecs.umich.edu else 755759Shsul@eecs.umich.edu panic("No Such Port\n"); 765759Shsul@eecs.umich.edu} 775759Shsul@eecs.umich.edu 785759Shsul@eecs.umich.eduvoid 795759Shsul@eecs.umich.eduAtomicSimpleCPU::init() 805759Shsul@eecs.umich.edu{ 815759Shsul@eecs.umich.edu BaseCPU::init(); 825759Shsul@eecs.umich.edu cpuId = tc->readCpuId(); 835759Shsul@eecs.umich.edu#if FULL_SYSTEM 845759Shsul@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 855759Shsul@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 865759Shsul@eecs.umich.edu 875759Shsul@eecs.umich.edu // initialize CPU, including PC 885759Shsul@eecs.umich.edu TheISA::initCPU(tc, cpuId); 895759Shsul@eecs.umich.edu } 905759Shsul@eecs.umich.edu#endif 915759Shsul@eecs.umich.edu if (hasPhysMemPort) { 925759Shsul@eecs.umich.edu bool snoop = false; 935759Shsul@eecs.umich.edu AddrRangeList pmAddrList; 945759Shsul@eecs.umich.edu physmemPort.getPeerAddressRanges(pmAddrList, snoop); 955759Shsul@eecs.umich.edu physMemAddr = *pmAddrList.begin(); 965759Shsul@eecs.umich.edu } 975759Shsul@eecs.umich.edu ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT 985759Shsul@eecs.umich.edu data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too 995759Shsul@eecs.umich.edu data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too 1005759Shsul@eecs.umich.edu} 1015759Shsul@eecs.umich.edu 1025759Shsul@eecs.umich.edubool 1035759Shsul@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 1045759Shsul@eecs.umich.edu{ 1055759Shsul@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 1065759Shsul@eecs.umich.edu return true; 1075759Shsul@eecs.umich.edu} 1085759Shsul@eecs.umich.edu 1095759Shsul@eecs.umich.eduTick 1105759Shsul@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 1115759Shsul@eecs.umich.edu{ 1125759Shsul@eecs.umich.edu //Snooping a coherence request, just return 1135759Shsul@eecs.umich.edu return 0; 1145759Shsul@eecs.umich.edu} 1155759Shsul@eecs.umich.edu 1165759Shsul@eecs.umich.eduvoid 1175759Shsul@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1185759Shsul@eecs.umich.edu{ 1195759Shsul@eecs.umich.edu //No internal storage to update, just return 1205759Shsul@eecs.umich.edu return; 1215759Shsul@eecs.umich.edu} 1225759Shsul@eecs.umich.edu 1235759Shsul@eecs.umich.eduvoid 1245759Shsul@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1255759Shsul@eecs.umich.edu{ 1265759Shsul@eecs.umich.edu if (status == RangeChange) { 1275759Shsul@eecs.umich.edu if (!snoopRangeSent) { 1285759Shsul@eecs.umich.edu snoopRangeSent = true; 1295759Shsul@eecs.umich.edu sendStatusChange(Port::RangeChange); 1305759Shsul@eecs.umich.edu } 1315759Shsul@eecs.umich.edu return; 1325759Shsul@eecs.umich.edu } 1335759Shsul@eecs.umich.edu 1345759Shsul@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1355759Shsul@eecs.umich.edu} 1365759Shsul@eecs.umich.edu 1375759Shsul@eecs.umich.eduvoid 1385759Shsul@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvRetry() 1395759Shsul@eecs.umich.edu{ 1405759Shsul@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1415759Shsul@eecs.umich.edu} 1425759Shsul@eecs.umich.edu 1435759Shsul@eecs.umich.eduvoid 1445759Shsul@eecs.umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port) 1455759Shsul@eecs.umich.edu{ 1465759Shsul@eecs.umich.edu Port::setPeer(port); 1475759Shsul@eecs.umich.edu 1485759Shsul@eecs.umich.edu#if FULL_SYSTEM 1495759Shsul@eecs.umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 1505759Shsul@eecs.umich.edu // Ports) 1515759Shsul@eecs.umich.edu cpu->tcBase()->connectMemPorts(); 1525759Shsul@eecs.umich.edu#endif 1535759Shsul@eecs.umich.edu} 1545759Shsul@eecs.umich.edu 1555759Shsul@eecs.umich.eduAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1565759Shsul@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), 1575759Shsul@eecs.umich.edu width(p->width), simulate_stalls(p->simulate_stalls), 1585759Shsul@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1595759Shsul@eecs.umich.edu physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1605759Shsul@eecs.umich.edu{ 1615958Sgblack@eecs.umich.edu _status = Idle; 1625958Sgblack@eecs.umich.edu 1635759Shsul@eecs.umich.edu icachePort.snoopRangeSent = false; 1645759Shsul@eecs.umich.edu dcachePort.snoopRangeSent = false; 1655759Shsul@eecs.umich.edu 1665759Shsul@eecs.umich.edu} 1675759Shsul@eecs.umich.edu 1685759Shsul@eecs.umich.edu 1696180Sksewell@umich.eduAtomicSimpleCPU::~AtomicSimpleCPU() 1706180Sksewell@umich.edu{ 1716180Sksewell@umich.edu} 1726180Sksewell@umich.edu 1735759Shsul@eecs.umich.eduvoid 1745759Shsul@eecs.umich.eduAtomicSimpleCPU::serialize(ostream &os) 1755759Shsul@eecs.umich.edu{ 1765759Shsul@eecs.umich.edu SimObject::State so_state = SimObject::getState(); 1772474SN/A SERIALIZE_ENUM(so_state); 1782474SN/A Status _status = status(); 1795183Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 1805183Ssaidi@eecs.umich.edu BaseSimpleCPU::serialize(os); 1815183Ssaidi@eecs.umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 1825759Shsul@eecs.umich.edu tickEvent.serialize(os); 1835759Shsul@eecs.umich.edu} 1842474SN/A 1852474SN/Avoid 1865713Shsul@eecs.umich.eduAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1875713Shsul@eecs.umich.edu{ 1885713Shsul@eecs.umich.edu SimObject::State so_state; 1895713Shsul@eecs.umich.edu UNSERIALIZE_ENUM(so_state); 1904997Sgblack@eecs.umich.edu UNSERIALIZE_ENUM(_status); 1915713Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1924997Sgblack@eecs.umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1935713Shsul@eecs.umich.edu} 1942474SN/A 1952474SN/Avoid 1965958Sgblack@eecs.umich.eduAtomicSimpleCPU::resume() 1975958Sgblack@eecs.umich.edu{ 1985958Sgblack@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1995958Sgblack@eecs.umich.edu return; 2005958Sgblack@eecs.umich.edu 2015958Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 2025958Sgblack@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 2035958Sgblack@eecs.umich.edu 2045958Sgblack@eecs.umich.edu changeState(SimObject::Running); 2055958Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 2065958Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 2075958Sgblack@eecs.umich.edu tickEvent.schedule(nextCycle()); 2085958Sgblack@eecs.umich.edu } 2095958Sgblack@eecs.umich.edu } 2105958Sgblack@eecs.umich.edu} 2115958Sgblack@eecs.umich.edu 2125958Sgblack@eecs.umich.eduvoid 2135958Sgblack@eecs.umich.eduAtomicSimpleCPU::switchOut() 2145958Sgblack@eecs.umich.edu{ 2155958Sgblack@eecs.umich.edu assert(status() == Running || status() == Idle); 2165958Sgblack@eecs.umich.edu _status = SwitchedOut; 2175958Sgblack@eecs.umich.edu 2185958Sgblack@eecs.umich.edu tickEvent.squash(); 2195958Sgblack@eecs.umich.edu} 2205958Sgblack@eecs.umich.edu 2215958Sgblack@eecs.umich.edu 2225958Sgblack@eecs.umich.eduvoid 2235958Sgblack@eecs.umich.eduAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2245958Sgblack@eecs.umich.edu{ 2255958Sgblack@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2265958Sgblack@eecs.umich.edu 2275958Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 228 229 // if any of this CPU's ThreadContexts are active, mark the CPU as 230 // running and schedule its tick event. 231 for (int i = 0; i < threadContexts.size(); ++i) { 232 ThreadContext *tc = threadContexts[i]; 233 if (tc->status() == ThreadContext::Active && _status != Running) { 234 _status = Running; 235 tickEvent.schedule(nextCycle()); 236 break; 237 } 238 } 239 if (_status != Running) { 240 _status = Idle; 241 } 242 assert(threadContexts.size() == 1); 243 cpuId = tc->readCpuId(); 244 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT 245 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too 246 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too 247} 248 249 250void 251AtomicSimpleCPU::activateContext(int thread_num, int delay) 252{ 253 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 254 255 assert(thread_num == 0); 256 assert(thread); 257 258 assert(_status == Idle); 259 assert(!tickEvent.scheduled()); 260 261 notIdleFraction++; 262 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 263 264 //Make sure ticks are still on multiples of cycles 265 tickEvent.schedule(nextCycle(curTick + ticks(delay))); 266 _status = Running; 267} 268 269 270void 271AtomicSimpleCPU::suspendContext(int thread_num) 272{ 273 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 274 275 assert(thread_num == 0); 276 assert(thread); 277 278 assert(_status == Running); 279 280 // tick event may not be scheduled if this gets called from inside 281 // an instruction's execution, e.g. "quiesce" 282 if (tickEvent.scheduled()) 283 tickEvent.deschedule(); 284 285 notIdleFraction--; 286 _status = Idle; 287} 288 289 290template <class T> 291Fault 292AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 293{ 294 // use the CPU's statically allocated read request and packet objects 295 Request *req = &data_read_req; 296 297 if (traceData) { 298 traceData->setAddr(addr); 299 } 300 301 //The block size of our peer. 302 int blockSize = dcachePort.peerBlockSize(); 303 //The size of the data we're trying to read. 304 int dataSize = sizeof(T); 305 306 uint8_t * dataPtr = (uint8_t *)&data; 307 308 //The address of the second part of this access if it needs to be split 309 //across a cache line boundary. 310 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 311 312 if(secondAddr > addr) 313 dataSize = secondAddr - addr; 314 315 dcache_latency = 0; 316 317 while(1) { 318 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 319 320 // translate to physical address 321 Fault fault = thread->translateDataReadReq(req); 322 323 // Now do the access. 324 if (fault == NoFault) { 325 Packet pkt = Packet(req, 326 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 327 Packet::Broadcast); 328 pkt.dataStatic(dataPtr); 329 330 if (req->isMmapedIpr()) 331 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 332 else { 333 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 334 dcache_latency += physmemPort.sendAtomic(&pkt); 335 else 336 dcache_latency += dcachePort.sendAtomic(&pkt); 337 } 338 dcache_access = true; 339 340 assert(!pkt.isError()); 341 342 if (req->isLocked()) { 343 TheISA::handleLockedRead(thread, req); 344 } 345 } 346 347 // This will need a new way to tell if it has a dcache attached. 348 if (req->isUncacheable()) 349 recordEvent("Uncached Read"); 350 351 //If there's a fault, return it 352 if (fault != NoFault) 353 return fault; 354 //If we don't need to access a second cache line, stop now. 355 if (secondAddr <= addr) 356 { 357 data = gtoh(data); 358 if (traceData) { 359 traceData->setData(data); 360 } 361 return fault; 362 } 363 364 /* 365 * Set up for accessing the second cache line. 366 */ 367 368 //Move the pointer we're reading into to the correct location. 369 dataPtr += dataSize; 370 //Adjust the size to get the remaining bytes. 371 dataSize = addr + sizeof(T) - secondAddr; 372 //And access the right address. 373 addr = secondAddr; 374 } 375} 376 377Fault 378AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr, 379 int size, unsigned flags) 380{ 381 // use the CPU's statically allocated read request and packet objects 382 Request *req = &data_read_req; 383 384 if (traceData) { 385 traceData->setAddr(vaddr); 386 } 387 388 //The block size of our peer. 389 int blockSize = dcachePort.peerBlockSize(); 390 //The size of the data we're trying to read. 391 int dataSize = size; 392 393 bool firstTimeThrough = true; 394 395 //The address of the second part of this access if it needs to be split 396 //across a cache line boundary. 397 Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize); 398 399 if(secondAddr > vaddr) 400 dataSize = secondAddr - vaddr; 401 402 while(1) { 403 req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); 404 405 // translate to physical address 406 Fault fault = thread->translateDataReadReq(req); 407 408 //If there's a fault, return it 409 if (fault != NoFault) 410 return fault; 411 412 if (firstTimeThrough) { 413 paddr = req->getPaddr(); 414 firstTimeThrough = false; 415 } 416 417 //If we don't need to access a second cache line, stop now. 418 if (secondAddr <= vaddr) 419 return fault; 420 421 /* 422 * Set up for accessing the second cache line. 423 */ 424 425 //Adjust the size to get the remaining bytes. 426 dataSize = vaddr + size - secondAddr; 427 //And access the right address. 428 vaddr = secondAddr; 429 } 430} 431 432#ifndef DOXYGEN_SHOULD_SKIP_THIS 433 434template 435Fault 436AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 437 438template 439Fault 440AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 441 442template 443Fault 444AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 445 446template 447Fault 448AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 449 450template 451Fault 452AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 453 454template 455Fault 456AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 457 458#endif //DOXYGEN_SHOULD_SKIP_THIS 459 460template<> 461Fault 462AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 463{ 464 return read(addr, *(uint64_t*)&data, flags); 465} 466 467template<> 468Fault 469AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 470{ 471 return read(addr, *(uint32_t*)&data, flags); 472} 473 474 475template<> 476Fault 477AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 478{ 479 return read(addr, (uint32_t&)data, flags); 480} 481 482 483template <class T> 484Fault 485AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 486{ 487 // use the CPU's statically allocated write request and packet objects 488 Request *req = &data_write_req; 489 490 if (traceData) { 491 traceData->setAddr(addr); 492 } 493 494 //The block size of our peer. 495 int blockSize = dcachePort.peerBlockSize(); 496 //The size of the data we're trying to read. 497 int dataSize = sizeof(T); 498 499 uint8_t * dataPtr = (uint8_t *)&data; 500 501 //The address of the second part of this access if it needs to be split 502 //across a cache line boundary. 503 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 504 505 if(secondAddr > addr) 506 dataSize = secondAddr - addr; 507 508 dcache_latency = 0; 509 510 while(1) { 511 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 512 513 // translate to physical address 514 Fault fault = thread->translateDataWriteReq(req); 515 516 // Now do the access. 517 if (fault == NoFault) { 518 MemCmd cmd = MemCmd::WriteReq; // default 519 bool do_access = true; // flag to suppress cache access 520 521 if (req->isLocked()) { 522 cmd = MemCmd::StoreCondReq; 523 do_access = TheISA::handleLockedWrite(thread, req); 524 } else if (req->isSwap()) { 525 cmd = MemCmd::SwapReq; 526 if (req->isCondSwap()) { 527 assert(res); 528 req->setExtraData(*res); 529 } 530 } 531 532 if (do_access) { 533 Packet pkt = Packet(req, cmd, Packet::Broadcast); 534 pkt.dataStatic(dataPtr); 535 536 if (req->isMmapedIpr()) { 537 dcache_latency += 538 TheISA::handleIprWrite(thread->getTC(), &pkt); 539 } else { 540 //XXX This needs to be outside of the loop in order to 541 //work properly for cache line boundary crossing 542 //accesses in transendian simulations. 543 data = htog(data); 544 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 545 dcache_latency += physmemPort.sendAtomic(&pkt); 546 else 547 dcache_latency += dcachePort.sendAtomic(&pkt); 548 } 549 dcache_access = true; 550 assert(!pkt.isError()); 551 552 if (req->isSwap()) { 553 assert(res); 554 *res = pkt.get<T>(); 555 } 556 } 557 558 if (res && !req->isSwap()) { 559 *res = req->getExtraData(); 560 } 561 } 562 563 // This will need a new way to tell if it's hooked up to a cache or not. 564 if (req->isUncacheable()) 565 recordEvent("Uncached Write"); 566 567 //If there's a fault or we don't need to access a second cache line, 568 //stop now. 569 if (fault != NoFault || secondAddr <= addr) 570 { 571 // If the write needs to have a fault on the access, consider 572 // calling changeStatus() and changing it to "bad addr write" 573 // or something. 574 if (traceData) { 575 traceData->setData(data); 576 } 577 return fault; 578 } 579 580 /* 581 * Set up for accessing the second cache line. 582 */ 583 584 //Move the pointer we're reading into to the correct location. 585 dataPtr += dataSize; 586 //Adjust the size to get the remaining bytes. 587 dataSize = addr + sizeof(T) - secondAddr; 588 //And access the right address. 589 addr = secondAddr; 590 } 591} 592 593Fault 594AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 595 int size, unsigned flags) 596{ 597 // use the CPU's statically allocated write request and packet objects 598 Request *req = &data_write_req; 599 600 if (traceData) { 601 traceData->setAddr(vaddr); 602 } 603 604 //The block size of our peer. 605 int blockSize = dcachePort.peerBlockSize(); 606 607 //The address of the second part of this access if it needs to be split 608 //across a cache line boundary. 609 Addr secondAddr = roundDown(vaddr + size - 1, blockSize); 610 611 //The size of the data we're trying to read. 612 int dataSize = size; 613 614 bool firstTimeThrough = true; 615 616 if(secondAddr > vaddr) 617 dataSize = secondAddr - vaddr; 618 619 dcache_latency = 0; 620 621 while(1) { 622 req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); 623 624 // translate to physical address 625 Fault fault = thread->translateDataWriteReq(req); 626 627 //If there's a fault or we don't need to access a second cache line, 628 //stop now. 629 if (fault != NoFault) 630 return fault; 631 632 if (firstTimeThrough) { 633 paddr = req->getPaddr(); 634 firstTimeThrough = false; 635 } 636 637 if (secondAddr <= vaddr) 638 return fault; 639 640 /* 641 * Set up for accessing the second cache line. 642 */ 643 644 //Adjust the size to get the remaining bytes. 645 dataSize = vaddr + size - secondAddr; 646 //And access the right address. 647 vaddr = secondAddr; 648 } 649} 650 651 652#ifndef DOXYGEN_SHOULD_SKIP_THIS 653 654template 655Fault 656AtomicSimpleCPU::write(Twin32_t data, Addr addr, 657 unsigned flags, uint64_t *res); 658 659template 660Fault 661AtomicSimpleCPU::write(Twin64_t data, Addr addr, 662 unsigned flags, uint64_t *res); 663 664template 665Fault 666AtomicSimpleCPU::write(uint64_t data, Addr addr, 667 unsigned flags, uint64_t *res); 668 669template 670Fault 671AtomicSimpleCPU::write(uint32_t data, Addr addr, 672 unsigned flags, uint64_t *res); 673 674template 675Fault 676AtomicSimpleCPU::write(uint16_t data, Addr addr, 677 unsigned flags, uint64_t *res); 678 679template 680Fault 681AtomicSimpleCPU::write(uint8_t data, Addr addr, 682 unsigned flags, uint64_t *res); 683 684#endif //DOXYGEN_SHOULD_SKIP_THIS 685 686template<> 687Fault 688AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 689{ 690 return write(*(uint64_t*)&data, addr, flags, res); 691} 692 693template<> 694Fault 695AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 696{ 697 return write(*(uint32_t*)&data, addr, flags, res); 698} 699 700 701template<> 702Fault 703AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 704{ 705 return write((uint32_t)data, addr, flags, res); 706} 707 708 709void 710AtomicSimpleCPU::tick() 711{ 712 DPRINTF(SimpleCPU, "Tick\n"); 713 714 Tick latency = ticks(1); // instruction takes one cycle by default 715 716 for (int i = 0; i < width; ++i) { 717 numCycles++; 718 719 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 720 checkForInterrupts(); 721 722 checkPcEventQueue(); 723 724 Fault fault = setupFetchRequest(&ifetch_req); 725 726 if (fault == NoFault) { 727 Tick icache_latency = 0; 728 bool icache_access = false; 729 dcache_access = false; // assume no dcache access 730 731 //Fetch more instruction memory if necessary 732 //if(predecoder.needMoreBytes()) 733 //{ 734 icache_access = true; 735 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 736 Packet::Broadcast); 737 ifetch_pkt.dataStatic(&inst); 738 739 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 740 icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 741 else 742 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 743 744 assert(!ifetch_pkt.isError()); 745 746 // ifetch_req is initialized to read the instruction directly 747 // into the CPU object's inst field. 748 //} 749 750 preExecute(); 751 752 if (curStaticInst) { 753 fault = curStaticInst->execute(this, traceData); 754 755 // keep an instruction count 756 if (fault == NoFault) 757 countInst(); 758 else if (traceData) { 759 // If there was a fault, we should trace this instruction. 760 delete traceData; 761 traceData = NULL; 762 } 763 764 postExecute(); 765 } 766 767 // @todo remove me after debugging with legion done 768 if (curStaticInst && (!curStaticInst->isMicroop() || 769 curStaticInst->isFirstMicroop())) 770 instCnt++; 771 772 if (simulate_stalls) { 773 Tick icache_stall = 774 icache_access ? icache_latency - ticks(1) : 0; 775 Tick dcache_stall = 776 dcache_access ? dcache_latency - ticks(1) : 0; 777 Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1); 778 if (ticks(stall_cycles) < (icache_stall + dcache_stall)) 779 latency += ticks(stall_cycles+1); 780 else 781 latency += ticks(stall_cycles); 782 } 783 784 } 785 if(fault != NoFault || !stayAtPC) 786 advancePC(fault); 787 } 788 789 if (_status != Idle) 790 tickEvent.schedule(curTick + latency); 791} 792 793 794void 795AtomicSimpleCPU::printAddr(Addr a) 796{ 797 dcachePort.printAddr(a); 798} 799 800 801//////////////////////////////////////////////////////////////////////// 802// 803// AtomicSimpleCPU Simulation Object 804// 805AtomicSimpleCPU * 806AtomicSimpleCPUParams::create() 807{ 808 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 809 params->name = name; 810 params->numberOfThreads = 1; 811 params->max_insts_any_thread = max_insts_any_thread; 812 params->max_insts_all_threads = max_insts_all_threads; 813 params->max_loads_any_thread = max_loads_any_thread; 814 params->max_loads_all_threads = max_loads_all_threads; 815 params->progress_interval = progress_interval; 816 params->deferRegistration = defer_registration; 817 params->phase = phase; 818 params->clock = clock; 819 params->functionTrace = function_trace; 820 params->functionTraceStart = function_trace_start; 821 params->width = width; 822 params->simulate_stalls = simulate_stalls; 823 params->system = system; 824 params->cpu_id = cpu_id; 825 params->tracer = tracer; 826 827 params->itb = itb; 828 params->dtb = dtb; 829#if FULL_SYSTEM 830 params->profile = profile; 831 params->do_quiesce = do_quiesce; 832 params->do_checkpoint_insts = do_checkpoint_insts; 833 params->do_statistics_insts = do_statistics_insts; 834#else 835 if (workload.size() != 1) 836 panic("only one workload allowed"); 837 params->process = workload[0]; 838#endif 839 840 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 841 return cpu; 842} 843