atomic.cc revision 4115
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
344040Ssaidi@eecs.umich.edu#include "base/bigint.hh"
352623SN/A#include "cpu/exetrace.hh"
362623SN/A#include "cpu/simple/atomic.hh"
373348Sbinkertn@umich.edu#include "mem/packet.hh"
383348Sbinkertn@umich.edu#include "mem/packet_access.hh"
392623SN/A#include "sim/builder.hh"
402901Ssaidi@eecs.umich.edu#include "sim/system.hh"
412623SN/A
422623SN/Ausing namespace std;
432623SN/Ausing namespace TheISA;
442623SN/A
452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
462623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
472623SN/A{
482623SN/A}
492623SN/A
502623SN/A
512623SN/Avoid
522623SN/AAtomicSimpleCPU::TickEvent::process()
532623SN/A{
542623SN/A    cpu->tick();
552623SN/A}
562623SN/A
572623SN/Aconst char *
582623SN/AAtomicSimpleCPU::TickEvent::description()
592623SN/A{
602623SN/A    return "AtomicSimpleCPU tick event";
612623SN/A}
622623SN/A
632856Srdreslin@umich.eduPort *
642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
652856Srdreslin@umich.edu{
662856Srdreslin@umich.edu    if (if_name == "dcache_port")
672856Srdreslin@umich.edu        return &dcachePort;
682856Srdreslin@umich.edu    else if (if_name == "icache_port")
692856Srdreslin@umich.edu        return &icachePort;
702856Srdreslin@umich.edu    else
712856Srdreslin@umich.edu        panic("No Such Port\n");
722856Srdreslin@umich.edu}
732623SN/A
742623SN/Avoid
752623SN/AAtomicSimpleCPU::init()
762623SN/A{
772623SN/A    BaseCPU::init();
782623SN/A#if FULL_SYSTEM
792680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
802680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
812623SN/A
822623SN/A        // initialize CPU, including PC
832680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
842623SN/A    }
852623SN/A#endif
862623SN/A}
872623SN/A
882623SN/Abool
893349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
902623SN/A{
913184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
922623SN/A    return true;
932623SN/A}
942623SN/A
952623SN/ATick
963349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
972623SN/A{
983310Srdreslin@umich.edu    //Snooping a coherence request, just return
993649Srdreslin@umich.edu    return 0;
1002623SN/A}
1012623SN/A
1022623SN/Avoid
1033349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1042623SN/A{
1053184Srdreslin@umich.edu    //No internal storage to update, just return
1063184Srdreslin@umich.edu    return;
1072623SN/A}
1082623SN/A
1092623SN/Avoid
1102623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1112623SN/A{
1123647Srdreslin@umich.edu    if (status == RangeChange) {
1133647Srdreslin@umich.edu        if (!snoopRangeSent) {
1143647Srdreslin@umich.edu            snoopRangeSent = true;
1153647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1163647Srdreslin@umich.edu        }
1172626SN/A        return;
1183647Srdreslin@umich.edu    }
1192626SN/A
1202623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1212623SN/A}
1222623SN/A
1232657Ssaidi@eecs.umich.eduvoid
1242623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1252623SN/A{
1262623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1272623SN/A}
1282623SN/A
1292623SN/A
1302623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1312623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1322623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1332640Sstever@eecs.umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
1342623SN/A{
1352623SN/A    _status = Idle;
1362623SN/A
1373647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1383647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1393647Srdreslin@umich.edu
1402663Sstever@eecs.umich.edu    ifetch_req = new Request();
1413170Sstever@eecs.umich.edu    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
1424022Sstever@eecs.umich.edu    ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
1432623SN/A    ifetch_pkt->dataStatic(&inst);
1442623SN/A
1452663Sstever@eecs.umich.edu    data_read_req = new Request();
1463170Sstever@eecs.umich.edu    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1474022Sstever@eecs.umich.edu    data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
1482641Sstever@eecs.umich.edu                               Packet::Broadcast);
1492623SN/A    data_read_pkt->dataStatic(&dataReg);
1502623SN/A
1512663Sstever@eecs.umich.edu    data_write_req = new Request();
1523170Sstever@eecs.umich.edu    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1534022Sstever@eecs.umich.edu    data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
1542641Sstever@eecs.umich.edu                                Packet::Broadcast);
1554040Ssaidi@eecs.umich.edu    data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
1564040Ssaidi@eecs.umich.edu                                Packet::Broadcast);
1572623SN/A}
1582623SN/A
1592623SN/A
1602623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1612623SN/A{
1622623SN/A}
1632623SN/A
1642623SN/Avoid
1652623SN/AAtomicSimpleCPU::serialize(ostream &os)
1662623SN/A{
1672915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1682915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1693177Shsul@eecs.umich.edu    Status _status = status();
1703177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1713145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1722623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1732623SN/A    tickEvent.serialize(os);
1742623SN/A}
1752623SN/A
1762623SN/Avoid
1772623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1782623SN/A{
1792915Sktlim@umich.edu    SimObject::State so_state;
1802915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1813177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1823145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1832915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1842915Sktlim@umich.edu}
1852915Sktlim@umich.edu
1862915Sktlim@umich.eduvoid
1872915Sktlim@umich.eduAtomicSimpleCPU::resume()
1882915Sktlim@umich.edu{
1893324Shsul@eecs.umich.edu    if (_status != SwitchedOut && _status != Idle) {
1903201Shsul@eecs.umich.edu        assert(system->getMemoryMode() == System::Atomic);
1913324Shsul@eecs.umich.edu
1923324Shsul@eecs.umich.edu        changeState(SimObject::Running);
1933324Shsul@eecs.umich.edu        if (thread->status() == ThreadContext::Active) {
1943431Sgblack@eecs.umich.edu            if (!tickEvent.scheduled()) {
1953495Sktlim@umich.edu                tickEvent.schedule(nextCycle());
1963431Sgblack@eecs.umich.edu            }
1973324Shsul@eecs.umich.edu        }
1982915Sktlim@umich.edu    }
1992623SN/A}
2002623SN/A
2012623SN/Avoid
2022798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2032623SN/A{
2042798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2052798Sktlim@umich.edu    _status = SwitchedOut;
2062623SN/A
2072798Sktlim@umich.edu    tickEvent.squash();
2082623SN/A}
2092623SN/A
2102623SN/A
2112623SN/Avoid
2122623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2132623SN/A{
2142623SN/A    BaseCPU::takeOverFrom(oldCPU);
2152623SN/A
2162623SN/A    assert(!tickEvent.scheduled());
2172623SN/A
2182680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2192623SN/A    // running and schedule its tick event.
2202680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2212680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2222680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2232623SN/A            _status = Running;
2243495Sktlim@umich.edu            tickEvent.schedule(nextCycle());
2252623SN/A            break;
2262623SN/A        }
2272623SN/A    }
2283512Sktlim@umich.edu    if (_status != Running) {
2293512Sktlim@umich.edu        _status = Idle;
2303512Sktlim@umich.edu    }
2312623SN/A}
2322623SN/A
2332623SN/A
2342623SN/Avoid
2352623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2362623SN/A{
2372623SN/A    assert(thread_num == 0);
2382683Sktlim@umich.edu    assert(thread);
2392623SN/A
2402623SN/A    assert(_status == Idle);
2412623SN/A    assert(!tickEvent.scheduled());
2422623SN/A
2432623SN/A    notIdleFraction++;
2443686Sktlim@umich.edu
2453686Sktlim@umich.edu#if FULL_SYSTEM
2463686Sktlim@umich.edu    // Connect the ThreadContext's memory ports (Functional/Virtual
2473686Sktlim@umich.edu    // Ports)
2483686Sktlim@umich.edu    tc->connectMemPorts();
2493686Sktlim@umich.edu#endif
2503686Sktlim@umich.edu
2513430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2523495Sktlim@umich.edu    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
2532623SN/A    _status = Running;
2542623SN/A}
2552623SN/A
2562623SN/A
2572623SN/Avoid
2582623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2592623SN/A{
2602623SN/A    assert(thread_num == 0);
2612683Sktlim@umich.edu    assert(thread);
2622623SN/A
2632623SN/A    assert(_status == Running);
2642626SN/A
2652626SN/A    // tick event may not be scheduled if this gets called from inside
2662626SN/A    // an instruction's execution, e.g. "quiesce"
2672626SN/A    if (tickEvent.scheduled())
2682626SN/A        tickEvent.deschedule();
2692623SN/A
2702623SN/A    notIdleFraction--;
2712623SN/A    _status = Idle;
2722623SN/A}
2732623SN/A
2742623SN/A
2752623SN/Atemplate <class T>
2762623SN/AFault
2772623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2782623SN/A{
2793169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2803169Sstever@eecs.umich.edu    Request *req = data_read_req;
2813349Sbinkertn@umich.edu    PacketPtr pkt = data_read_pkt;
2823169Sstever@eecs.umich.edu
2833169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
2842623SN/A
2852623SN/A    if (traceData) {
2862623SN/A        traceData->setAddr(addr);
2872623SN/A    }
2882623SN/A
2892623SN/A    // translate to physical address
2903169Sstever@eecs.umich.edu    Fault fault = thread->translateDataReadReq(req);
2912623SN/A
2922623SN/A    // Now do the access.
2932623SN/A    if (fault == NoFault) {
2943169Sstever@eecs.umich.edu        pkt->reinitFromRequest();
2952623SN/A
2963806Ssaidi@eecs.umich.edu        if (req->isMmapedIpr())
2973806Ssaidi@eecs.umich.edu            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
2983806Ssaidi@eecs.umich.edu        else
2993806Ssaidi@eecs.umich.edu            dcache_latency = dcachePort.sendAtomic(pkt);
3002623SN/A        dcache_access = true;
3013814Ssaidi@eecs.umich.edu#if !defined(NDEBUG)
3023814Ssaidi@eecs.umich.edu        if (pkt->result != Packet::Success)
3033814Ssaidi@eecs.umich.edu            panic("Unable to find responder for address pa = %#X va = %#X\n",
3043814Ssaidi@eecs.umich.edu                    pkt->req->getPaddr(), pkt->req->getVaddr());
3053814Ssaidi@eecs.umich.edu#endif
3063169Sstever@eecs.umich.edu        data = pkt->get<T>();
3073170Sstever@eecs.umich.edu
3083170Sstever@eecs.umich.edu        if (req->isLocked()) {
3093170Sstever@eecs.umich.edu            TheISA::handleLockedRead(thread, req);
3103170Sstever@eecs.umich.edu        }
3112623SN/A    }
3122623SN/A
3132623SN/A    // This will need a new way to tell if it has a dcache attached.
3143172Sstever@eecs.umich.edu    if (req->isUncacheable())
3152623SN/A        recordEvent("Uncached Read");
3162623SN/A
3172623SN/A    return fault;
3182623SN/A}
3192623SN/A
3202623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3212623SN/A
3222623SN/Atemplate
3232623SN/AFault
3244115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
3254115Ssaidi@eecs.umich.edu
3264115Ssaidi@eecs.umich.edutemplate
3274115Ssaidi@eecs.umich.eduFault
3284040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
3294040Ssaidi@eecs.umich.edu
3304040Ssaidi@eecs.umich.edutemplate
3314040Ssaidi@eecs.umich.eduFault
3322623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
3332623SN/A
3342623SN/Atemplate
3352623SN/AFault
3362623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
3372623SN/A
3382623SN/Atemplate
3392623SN/AFault
3402623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
3412623SN/A
3422623SN/Atemplate
3432623SN/AFault
3442623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
3452623SN/A
3462623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
3472623SN/A
3482623SN/Atemplate<>
3492623SN/AFault
3502623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
3512623SN/A{
3522623SN/A    return read(addr, *(uint64_t*)&data, flags);
3532623SN/A}
3542623SN/A
3552623SN/Atemplate<>
3562623SN/AFault
3572623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
3582623SN/A{
3592623SN/A    return read(addr, *(uint32_t*)&data, flags);
3602623SN/A}
3612623SN/A
3622623SN/A
3632623SN/Atemplate<>
3642623SN/AFault
3652623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
3662623SN/A{
3672623SN/A    return read(addr, (uint32_t&)data, flags);
3682623SN/A}
3692623SN/A
3702623SN/A
3712623SN/Atemplate <class T>
3722623SN/AFault
3732623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
3742623SN/A{
3753169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
3763169Sstever@eecs.umich.edu    Request *req = data_write_req;
3774040Ssaidi@eecs.umich.edu    PacketPtr pkt;
3783169Sstever@eecs.umich.edu
3793169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
3802623SN/A
3814040Ssaidi@eecs.umich.edu    if (req->isSwap())
3824040Ssaidi@eecs.umich.edu        pkt = data_swap_pkt;
3834040Ssaidi@eecs.umich.edu    else
3844040Ssaidi@eecs.umich.edu        pkt = data_write_pkt;
3854040Ssaidi@eecs.umich.edu
3862623SN/A    if (traceData) {
3872623SN/A        traceData->setAddr(addr);
3882623SN/A    }
3892623SN/A
3902623SN/A    // translate to physical address
3913169Sstever@eecs.umich.edu    Fault fault = thread->translateDataWriteReq(req);
3922623SN/A
3932623SN/A    // Now do the access.
3942623SN/A    if (fault == NoFault) {
3953170Sstever@eecs.umich.edu        bool do_access = true;  // flag to suppress cache access
3962623SN/A
3973170Sstever@eecs.umich.edu        if (req->isLocked()) {
3983170Sstever@eecs.umich.edu            do_access = TheISA::handleLockedWrite(thread, req);
3993170Sstever@eecs.umich.edu        }
4004040Ssaidi@eecs.umich.edu        if (req->isCondSwap()) {
4014040Ssaidi@eecs.umich.edu             assert(res);
4024040Ssaidi@eecs.umich.edu             req->setExtraData(*res);
4034040Ssaidi@eecs.umich.edu        }
4044040Ssaidi@eecs.umich.edu
4052623SN/A
4063170Sstever@eecs.umich.edu        if (do_access) {
4073170Sstever@eecs.umich.edu            pkt->reinitFromRequest();
4083170Sstever@eecs.umich.edu            pkt->dataStatic(&data);
4092631SN/A
4103806Ssaidi@eecs.umich.edu            if (req->isMmapedIpr()) {
4113806Ssaidi@eecs.umich.edu                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
4123806Ssaidi@eecs.umich.edu            } else {
4133806Ssaidi@eecs.umich.edu                data = htog(data);
4143806Ssaidi@eecs.umich.edu                dcache_latency = dcachePort.sendAtomic(pkt);
4153806Ssaidi@eecs.umich.edu            }
4163170Sstever@eecs.umich.edu            dcache_access = true;
4173170Sstever@eecs.umich.edu
4183814Ssaidi@eecs.umich.edu#if !defined(NDEBUG)
4193814Ssaidi@eecs.umich.edu            if (pkt->result != Packet::Success)
4203814Ssaidi@eecs.umich.edu                panic("Unable to find responder for address pa = %#X va = %#X\n",
4213814Ssaidi@eecs.umich.edu                        pkt->req->getPaddr(), pkt->req->getVaddr());
4223814Ssaidi@eecs.umich.edu#endif
4233170Sstever@eecs.umich.edu        }
4243170Sstever@eecs.umich.edu
4254040Ssaidi@eecs.umich.edu        if (req->isSwap()) {
4264040Ssaidi@eecs.umich.edu            assert(res);
4274040Ssaidi@eecs.umich.edu            *res = pkt->get<T>();
4284050Ssaidi@eecs.umich.edu        } else if (res) {
4294052Ssaidi@eecs.umich.edu            *res = req->getExtraData();
4302631SN/A        }
4312623SN/A    }
4322623SN/A
4332623SN/A    // This will need a new way to tell if it's hooked up to a cache or not.
4343172Sstever@eecs.umich.edu    if (req->isUncacheable())
4352623SN/A        recordEvent("Uncached Write");
4362623SN/A
4372623SN/A    // If the write needs to have a fault on the access, consider calling
4382623SN/A    // changeStatus() and changing it to "bad addr write" or something.
4392623SN/A    return fault;
4402623SN/A}
4412623SN/A
4422623SN/A
4432623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
4442623SN/Atemplate
4452623SN/AFault
4462623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
4472623SN/A                       unsigned flags, uint64_t *res);
4482623SN/A
4492623SN/Atemplate
4502623SN/AFault
4512623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
4522623SN/A                       unsigned flags, uint64_t *res);
4532623SN/A
4542623SN/Atemplate
4552623SN/AFault
4562623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
4572623SN/A                       unsigned flags, uint64_t *res);
4582623SN/A
4592623SN/Atemplate
4602623SN/AFault
4612623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
4622623SN/A                       unsigned flags, uint64_t *res);
4632623SN/A
4642623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4652623SN/A
4662623SN/Atemplate<>
4672623SN/AFault
4682623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
4692623SN/A{
4702623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
4712623SN/A}
4722623SN/A
4732623SN/Atemplate<>
4742623SN/AFault
4752623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
4762623SN/A{
4772623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
4782623SN/A}
4792623SN/A
4802623SN/A
4812623SN/Atemplate<>
4822623SN/AFault
4832623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
4842623SN/A{
4852623SN/A    return write((uint32_t)data, addr, flags, res);
4862623SN/A}
4872623SN/A
4882623SN/A
4892623SN/Avoid
4902623SN/AAtomicSimpleCPU::tick()
4912623SN/A{
4922623SN/A    Tick latency = cycles(1); // instruction takes one cycle by default
4932623SN/A
4942623SN/A    for (int i = 0; i < width; ++i) {
4952623SN/A        numCycles++;
4962623SN/A
4973387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
4983387Sgblack@eecs.umich.edu            checkForInterrupts();
4992626SN/A
5002662Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(ifetch_req);
5012623SN/A
5022623SN/A        if (fault == NoFault) {
5032662Sstever@eecs.umich.edu            ifetch_pkt->reinitFromRequest();
5042662Sstever@eecs.umich.edu
5052662Sstever@eecs.umich.edu            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
5062623SN/A            // ifetch_req is initialized to read the instruction directly
5072623SN/A            // into the CPU object's inst field.
5082623SN/A
5092623SN/A            dcache_access = false; // assume no dcache access
5102623SN/A            preExecute();
5113814Ssaidi@eecs.umich.edu
5122623SN/A            fault = curStaticInst->execute(this, traceData);
5132623SN/A            postExecute();
5142623SN/A
5153814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
5163814Ssaidi@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroOp() ||
5173901Ssaidi@eecs.umich.edu                        curStaticInst->isFirstMicroOp()))
5183814Ssaidi@eecs.umich.edu                instCnt++;
5193814Ssaidi@eecs.umich.edu
5202623SN/A            if (simulate_stalls) {
5212662Sstever@eecs.umich.edu                Tick icache_stall = icache_latency - cycles(1);
5222623SN/A                Tick dcache_stall =
5232662Sstever@eecs.umich.edu                    dcache_access ? dcache_latency - cycles(1) : 0;
5242803Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
5252803Ssaidi@eecs.umich.edu                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
5262803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles+1);
5272803Ssaidi@eecs.umich.edu                else
5282803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles);
5292623SN/A            }
5302623SN/A
5312623SN/A        }
5322623SN/A
5332623SN/A        advancePC(fault);
5342623SN/A    }
5352623SN/A
5362626SN/A    if (_status != Idle)
5372626SN/A        tickEvent.schedule(curTick + latency);
5382623SN/A}
5392623SN/A
5402623SN/A
5412623SN/A////////////////////////////////////////////////////////////////////////
5422623SN/A//
5432623SN/A//  AtomicSimpleCPU Simulation Object
5442623SN/A//
5452623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5462623SN/A
5472623SN/A    Param<Counter> max_insts_any_thread;
5482623SN/A    Param<Counter> max_insts_all_threads;
5492623SN/A    Param<Counter> max_loads_any_thread;
5502623SN/A    Param<Counter> max_loads_all_threads;
5513119Sktlim@umich.edu    Param<Tick> progress_interval;
5522901Ssaidi@eecs.umich.edu    SimObjectParam<System *> system;
5533170Sstever@eecs.umich.edu    Param<int> cpu_id;
5542623SN/A
5552623SN/A#if FULL_SYSTEM
5563453Sgblack@eecs.umich.edu    SimObjectParam<TheISA::ITB *> itb;
5573453Sgblack@eecs.umich.edu    SimObjectParam<TheISA::DTB *> dtb;
5582623SN/A    Param<Tick> profile;
5593617Sbinkertn@umich.edu
5603617Sbinkertn@umich.edu    Param<bool> do_quiesce;
5613617Sbinkertn@umich.edu    Param<bool> do_checkpoint_insts;
5623617Sbinkertn@umich.edu    Param<bool> do_statistics_insts;
5632623SN/A#else
5642623SN/A    SimObjectParam<Process *> workload;
5652623SN/A#endif // FULL_SYSTEM
5662623SN/A
5672623SN/A    Param<int> clock;
5683661Srdreslin@umich.edu    Param<int> phase;
5692623SN/A
5702623SN/A    Param<bool> defer_registration;
5712623SN/A    Param<int> width;
5722623SN/A    Param<bool> function_trace;
5732623SN/A    Param<Tick> function_trace_start;
5742623SN/A    Param<bool> simulate_stalls;
5752623SN/A
5762623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5772623SN/A
5782623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5792623SN/A
5802623SN/A    INIT_PARAM(max_insts_any_thread,
5812623SN/A               "terminate when any thread reaches this inst count"),
5822623SN/A    INIT_PARAM(max_insts_all_threads,
5832623SN/A               "terminate when all threads have reached this inst count"),
5842623SN/A    INIT_PARAM(max_loads_any_thread,
5852623SN/A               "terminate when any thread reaches this load count"),
5862623SN/A    INIT_PARAM(max_loads_all_threads,
5872623SN/A               "terminate when all threads have reached this load count"),
5883119Sktlim@umich.edu    INIT_PARAM(progress_interval, "Progress interval"),
5892901Ssaidi@eecs.umich.edu    INIT_PARAM(system, "system object"),
5903170Sstever@eecs.umich.edu    INIT_PARAM(cpu_id, "processor ID"),
5912623SN/A
5922623SN/A#if FULL_SYSTEM
5932623SN/A    INIT_PARAM(itb, "Instruction TLB"),
5942623SN/A    INIT_PARAM(dtb, "Data TLB"),
5952623SN/A    INIT_PARAM(profile, ""),
5963617Sbinkertn@umich.edu    INIT_PARAM(do_quiesce, ""),
5973617Sbinkertn@umich.edu    INIT_PARAM(do_checkpoint_insts, ""),
5983617Sbinkertn@umich.edu    INIT_PARAM(do_statistics_insts, ""),
5992623SN/A#else
6002623SN/A    INIT_PARAM(workload, "processes to run"),
6012623SN/A#endif // FULL_SYSTEM
6022623SN/A
6032623SN/A    INIT_PARAM(clock, "clock speed"),
6043661Srdreslin@umich.edu    INIT_PARAM_DFLT(phase, "clock phase", 0),
6052623SN/A    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
6062623SN/A    INIT_PARAM(width, "cpu width"),
6072623SN/A    INIT_PARAM(function_trace, "Enable function trace"),
6082623SN/A    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
6092623SN/A    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
6102623SN/A
6112623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
6122623SN/A
6132623SN/A
6142623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU)
6152623SN/A{
6162623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
6172623SN/A    params->name = getInstanceName();
6182623SN/A    params->numberOfThreads = 1;
6192623SN/A    params->max_insts_any_thread = max_insts_any_thread;
6202623SN/A    params->max_insts_all_threads = max_insts_all_threads;
6212623SN/A    params->max_loads_any_thread = max_loads_any_thread;
6222623SN/A    params->max_loads_all_threads = max_loads_all_threads;
6233119Sktlim@umich.edu    params->progress_interval = progress_interval;
6242623SN/A    params->deferRegistration = defer_registration;
6253661Srdreslin@umich.edu    params->phase = phase;
6262623SN/A    params->clock = clock;
6272623SN/A    params->functionTrace = function_trace;
6282623SN/A    params->functionTraceStart = function_trace_start;
6292623SN/A    params->width = width;
6302623SN/A    params->simulate_stalls = simulate_stalls;
6312901Ssaidi@eecs.umich.edu    params->system = system;
6323170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
6332623SN/A
6342623SN/A#if FULL_SYSTEM
6352623SN/A    params->itb = itb;
6362623SN/A    params->dtb = dtb;
6372623SN/A    params->profile = profile;
6383617Sbinkertn@umich.edu    params->do_quiesce = do_quiesce;
6393617Sbinkertn@umich.edu    params->do_checkpoint_insts = do_checkpoint_insts;
6403617Sbinkertn@umich.edu    params->do_statistics_insts = do_statistics_insts;
6412623SN/A#else
6422623SN/A    params->process = workload;
6432623SN/A#endif
6442623SN/A
6452623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
6462623SN/A    return cpu;
6472623SN/A}
6482623SN/A
6492623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
6502623SN/A
651