atomic.cc revision 3901
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
342623SN/A#include "cpu/exetrace.hh"
352623SN/A#include "cpu/simple/atomic.hh"
363348Sbinkertn@umich.edu#include "mem/packet.hh"
373348Sbinkertn@umich.edu#include "mem/packet_access.hh"
382623SN/A#include "sim/builder.hh"
392901Ssaidi@eecs.umich.edu#include "sim/system.hh"
402623SN/A
412623SN/Ausing namespace std;
422623SN/Ausing namespace TheISA;
432623SN/A
442623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
452623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
462623SN/A{
472623SN/A}
482623SN/A
492623SN/A
502623SN/Avoid
512623SN/AAtomicSimpleCPU::TickEvent::process()
522623SN/A{
532623SN/A    cpu->tick();
542623SN/A}
552623SN/A
562623SN/Aconst char *
572623SN/AAtomicSimpleCPU::TickEvent::description()
582623SN/A{
592623SN/A    return "AtomicSimpleCPU tick event";
602623SN/A}
612623SN/A
622856Srdreslin@umich.eduPort *
632856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
642856Srdreslin@umich.edu{
652856Srdreslin@umich.edu    if (if_name == "dcache_port")
662856Srdreslin@umich.edu        return &dcachePort;
672856Srdreslin@umich.edu    else if (if_name == "icache_port")
682856Srdreslin@umich.edu        return &icachePort;
692856Srdreslin@umich.edu    else
702856Srdreslin@umich.edu        panic("No Such Port\n");
712856Srdreslin@umich.edu}
722623SN/A
732623SN/Avoid
742623SN/AAtomicSimpleCPU::init()
752623SN/A{
762623SN/A    BaseCPU::init();
772623SN/A#if FULL_SYSTEM
782680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
792680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
802623SN/A
812623SN/A        // initialize CPU, including PC
822680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
832623SN/A    }
842623SN/A#endif
852623SN/A}
862623SN/A
872623SN/Abool
883349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
892623SN/A{
903184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
912623SN/A    return true;
922623SN/A}
932623SN/A
942623SN/ATick
953349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
962623SN/A{
973310Srdreslin@umich.edu    //Snooping a coherence request, just return
983649Srdreslin@umich.edu    return 0;
992623SN/A}
1002623SN/A
1012623SN/Avoid
1023349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1032623SN/A{
1043184Srdreslin@umich.edu    //No internal storage to update, just return
1053184Srdreslin@umich.edu    return;
1062623SN/A}
1072623SN/A
1082623SN/Avoid
1092623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1102623SN/A{
1113647Srdreslin@umich.edu    if (status == RangeChange) {
1123647Srdreslin@umich.edu        if (!snoopRangeSent) {
1133647Srdreslin@umich.edu            snoopRangeSent = true;
1143647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1153647Srdreslin@umich.edu        }
1162626SN/A        return;
1173647Srdreslin@umich.edu    }
1182626SN/A
1192623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1202623SN/A}
1212623SN/A
1222657Ssaidi@eecs.umich.eduvoid
1232623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1242623SN/A{
1252623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1262623SN/A}
1272623SN/A
1282623SN/A
1292623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1302623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1312623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1322640Sstever@eecs.umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
1332623SN/A{
1342623SN/A    _status = Idle;
1352623SN/A
1363647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1373647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1383647Srdreslin@umich.edu
1392663Sstever@eecs.umich.edu    ifetch_req = new Request();
1403170Sstever@eecs.umich.edu    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
1412641Sstever@eecs.umich.edu    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
1422623SN/A    ifetch_pkt->dataStatic(&inst);
1432623SN/A
1442663Sstever@eecs.umich.edu    data_read_req = new Request();
1453170Sstever@eecs.umich.edu    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1462641Sstever@eecs.umich.edu    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
1472641Sstever@eecs.umich.edu                               Packet::Broadcast);
1482623SN/A    data_read_pkt->dataStatic(&dataReg);
1492623SN/A
1502663Sstever@eecs.umich.edu    data_write_req = new Request();
1513170Sstever@eecs.umich.edu    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1522641Sstever@eecs.umich.edu    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
1532641Sstever@eecs.umich.edu                                Packet::Broadcast);
1542623SN/A}
1552623SN/A
1562623SN/A
1572623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1582623SN/A{
1592623SN/A}
1602623SN/A
1612623SN/Avoid
1622623SN/AAtomicSimpleCPU::serialize(ostream &os)
1632623SN/A{
1642915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1652915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1663177Shsul@eecs.umich.edu    Status _status = status();
1673177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1683145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1692623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1702623SN/A    tickEvent.serialize(os);
1712623SN/A}
1722623SN/A
1732623SN/Avoid
1742623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1752623SN/A{
1762915Sktlim@umich.edu    SimObject::State so_state;
1772915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1783177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1793145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1802915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1812915Sktlim@umich.edu}
1822915Sktlim@umich.edu
1832915Sktlim@umich.eduvoid
1842915Sktlim@umich.eduAtomicSimpleCPU::resume()
1852915Sktlim@umich.edu{
1863324Shsul@eecs.umich.edu    if (_status != SwitchedOut && _status != Idle) {
1873201Shsul@eecs.umich.edu        assert(system->getMemoryMode() == System::Atomic);
1883324Shsul@eecs.umich.edu
1893324Shsul@eecs.umich.edu        changeState(SimObject::Running);
1903324Shsul@eecs.umich.edu        if (thread->status() == ThreadContext::Active) {
1913431Sgblack@eecs.umich.edu            if (!tickEvent.scheduled()) {
1923495Sktlim@umich.edu                tickEvent.schedule(nextCycle());
1933431Sgblack@eecs.umich.edu            }
1943324Shsul@eecs.umich.edu        }
1952915Sktlim@umich.edu    }
1962623SN/A}
1972623SN/A
1982623SN/Avoid
1992798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2002623SN/A{
2012798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2022798Sktlim@umich.edu    _status = SwitchedOut;
2032623SN/A
2042798Sktlim@umich.edu    tickEvent.squash();
2052623SN/A}
2062623SN/A
2072623SN/A
2082623SN/Avoid
2092623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2102623SN/A{
2112623SN/A    BaseCPU::takeOverFrom(oldCPU);
2122623SN/A
2132623SN/A    assert(!tickEvent.scheduled());
2142623SN/A
2152680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2162623SN/A    // running and schedule its tick event.
2172680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2182680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2192680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2202623SN/A            _status = Running;
2213495Sktlim@umich.edu            tickEvent.schedule(nextCycle());
2222623SN/A            break;
2232623SN/A        }
2242623SN/A    }
2253512Sktlim@umich.edu    if (_status != Running) {
2263512Sktlim@umich.edu        _status = Idle;
2273512Sktlim@umich.edu    }
2282623SN/A}
2292623SN/A
2302623SN/A
2312623SN/Avoid
2322623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2332623SN/A{
2342623SN/A    assert(thread_num == 0);
2352683Sktlim@umich.edu    assert(thread);
2362623SN/A
2372623SN/A    assert(_status == Idle);
2382623SN/A    assert(!tickEvent.scheduled());
2392623SN/A
2402623SN/A    notIdleFraction++;
2413686Sktlim@umich.edu
2423686Sktlim@umich.edu#if FULL_SYSTEM
2433686Sktlim@umich.edu    // Connect the ThreadContext's memory ports (Functional/Virtual
2443686Sktlim@umich.edu    // Ports)
2453686Sktlim@umich.edu    tc->connectMemPorts();
2463686Sktlim@umich.edu#endif
2473686Sktlim@umich.edu
2483430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2493495Sktlim@umich.edu    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
2502623SN/A    _status = Running;
2512623SN/A}
2522623SN/A
2532623SN/A
2542623SN/Avoid
2552623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2562623SN/A{
2572623SN/A    assert(thread_num == 0);
2582683Sktlim@umich.edu    assert(thread);
2592623SN/A
2602623SN/A    assert(_status == Running);
2612626SN/A
2622626SN/A    // tick event may not be scheduled if this gets called from inside
2632626SN/A    // an instruction's execution, e.g. "quiesce"
2642626SN/A    if (tickEvent.scheduled())
2652626SN/A        tickEvent.deschedule();
2662623SN/A
2672623SN/A    notIdleFraction--;
2682623SN/A    _status = Idle;
2692623SN/A}
2702623SN/A
2712623SN/A
2722623SN/Atemplate <class T>
2732623SN/AFault
2742623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2752623SN/A{
2763169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2773169Sstever@eecs.umich.edu    Request *req = data_read_req;
2783349Sbinkertn@umich.edu    PacketPtr pkt = data_read_pkt;
2793169Sstever@eecs.umich.edu
2803169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
2812623SN/A
2822623SN/A    if (traceData) {
2832623SN/A        traceData->setAddr(addr);
2842623SN/A    }
2852623SN/A
2862623SN/A    // translate to physical address
2873169Sstever@eecs.umich.edu    Fault fault = thread->translateDataReadReq(req);
2882623SN/A
2892623SN/A    // Now do the access.
2902623SN/A    if (fault == NoFault) {
2913169Sstever@eecs.umich.edu        pkt->reinitFromRequest();
2922623SN/A
2933806Ssaidi@eecs.umich.edu        if (req->isMmapedIpr())
2943806Ssaidi@eecs.umich.edu            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
2953806Ssaidi@eecs.umich.edu        else
2963806Ssaidi@eecs.umich.edu            dcache_latency = dcachePort.sendAtomic(pkt);
2972623SN/A        dcache_access = true;
2983814Ssaidi@eecs.umich.edu#if !defined(NDEBUG)
2993814Ssaidi@eecs.umich.edu        if (pkt->result != Packet::Success)
3003814Ssaidi@eecs.umich.edu            panic("Unable to find responder for address pa = %#X va = %#X\n",
3013814Ssaidi@eecs.umich.edu                    pkt->req->getPaddr(), pkt->req->getVaddr());
3023814Ssaidi@eecs.umich.edu#endif
3033169Sstever@eecs.umich.edu        data = pkt->get<T>();
3043170Sstever@eecs.umich.edu
3053170Sstever@eecs.umich.edu        if (req->isLocked()) {
3063170Sstever@eecs.umich.edu            TheISA::handleLockedRead(thread, req);
3073170Sstever@eecs.umich.edu        }
3082623SN/A    }
3092623SN/A
3102623SN/A    // This will need a new way to tell if it has a dcache attached.
3113172Sstever@eecs.umich.edu    if (req->isUncacheable())
3122623SN/A        recordEvent("Uncached Read");
3132623SN/A
3142623SN/A    return fault;
3152623SN/A}
3162623SN/A
3172623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3182623SN/A
3192623SN/Atemplate
3202623SN/AFault
3212623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
3222623SN/A
3232623SN/Atemplate
3242623SN/AFault
3252623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
3262623SN/A
3272623SN/Atemplate
3282623SN/AFault
3292623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
3302623SN/A
3312623SN/Atemplate
3322623SN/AFault
3332623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
3342623SN/A
3352623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
3362623SN/A
3372623SN/Atemplate<>
3382623SN/AFault
3392623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
3402623SN/A{
3412623SN/A    return read(addr, *(uint64_t*)&data, flags);
3422623SN/A}
3432623SN/A
3442623SN/Atemplate<>
3452623SN/AFault
3462623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
3472623SN/A{
3482623SN/A    return read(addr, *(uint32_t*)&data, flags);
3492623SN/A}
3502623SN/A
3512623SN/A
3522623SN/Atemplate<>
3532623SN/AFault
3542623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
3552623SN/A{
3562623SN/A    return read(addr, (uint32_t&)data, flags);
3572623SN/A}
3582623SN/A
3592623SN/A
3602623SN/Atemplate <class T>
3612623SN/AFault
3622623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
3632623SN/A{
3643169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
3653169Sstever@eecs.umich.edu    Request *req = data_write_req;
3663349Sbinkertn@umich.edu    PacketPtr pkt = data_write_pkt;
3673169Sstever@eecs.umich.edu
3683169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
3692623SN/A
3702623SN/A    if (traceData) {
3712623SN/A        traceData->setAddr(addr);
3722623SN/A    }
3732623SN/A
3742623SN/A    // translate to physical address
3753169Sstever@eecs.umich.edu    Fault fault = thread->translateDataWriteReq(req);
3762623SN/A
3772623SN/A    // Now do the access.
3782623SN/A    if (fault == NoFault) {
3793170Sstever@eecs.umich.edu        bool do_access = true;  // flag to suppress cache access
3802623SN/A
3813170Sstever@eecs.umich.edu        if (req->isLocked()) {
3823170Sstever@eecs.umich.edu            do_access = TheISA::handleLockedWrite(thread, req);
3833170Sstever@eecs.umich.edu        }
3842623SN/A
3853170Sstever@eecs.umich.edu        if (do_access) {
3863170Sstever@eecs.umich.edu            pkt->reinitFromRequest();
3873170Sstever@eecs.umich.edu            pkt->dataStatic(&data);
3882631SN/A
3893806Ssaidi@eecs.umich.edu            if (req->isMmapedIpr()) {
3903806Ssaidi@eecs.umich.edu                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
3913806Ssaidi@eecs.umich.edu            } else {
3923806Ssaidi@eecs.umich.edu                data = htog(data);
3933806Ssaidi@eecs.umich.edu                dcache_latency = dcachePort.sendAtomic(pkt);
3943806Ssaidi@eecs.umich.edu            }
3953170Sstever@eecs.umich.edu            dcache_access = true;
3963170Sstever@eecs.umich.edu
3973814Ssaidi@eecs.umich.edu#if !defined(NDEBUG)
3983814Ssaidi@eecs.umich.edu            if (pkt->result != Packet::Success)
3993814Ssaidi@eecs.umich.edu                panic("Unable to find responder for address pa = %#X va = %#X\n",
4003814Ssaidi@eecs.umich.edu                        pkt->req->getPaddr(), pkt->req->getVaddr());
4013814Ssaidi@eecs.umich.edu#endif
4023170Sstever@eecs.umich.edu        }
4033170Sstever@eecs.umich.edu
4043170Sstever@eecs.umich.edu        if (req->isLocked()) {
4053170Sstever@eecs.umich.edu            uint64_t scResult = req->getScResult();
4063170Sstever@eecs.umich.edu            if (scResult != 0) {
4073170Sstever@eecs.umich.edu                // clear failure counter
4083170Sstever@eecs.umich.edu                thread->setStCondFailures(0);
4093170Sstever@eecs.umich.edu            }
4103170Sstever@eecs.umich.edu            if (res) {
4113170Sstever@eecs.umich.edu                *res = req->getScResult();
4123170Sstever@eecs.umich.edu            }
4132631SN/A        }
4142623SN/A    }
4152623SN/A
4162623SN/A    // This will need a new way to tell if it's hooked up to a cache or not.
4173172Sstever@eecs.umich.edu    if (req->isUncacheable())
4182623SN/A        recordEvent("Uncached Write");
4192623SN/A
4202623SN/A    // If the write needs to have a fault on the access, consider calling
4212623SN/A    // changeStatus() and changing it to "bad addr write" or something.
4222623SN/A    return fault;
4232623SN/A}
4242623SN/A
4252623SN/A
4262623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
4272623SN/Atemplate
4282623SN/AFault
4292623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
4302623SN/A                       unsigned flags, uint64_t *res);
4312623SN/A
4322623SN/Atemplate
4332623SN/AFault
4342623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
4352623SN/A                       unsigned flags, uint64_t *res);
4362623SN/A
4372623SN/Atemplate
4382623SN/AFault
4392623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
4402623SN/A                       unsigned flags, uint64_t *res);
4412623SN/A
4422623SN/Atemplate
4432623SN/AFault
4442623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
4452623SN/A                       unsigned flags, uint64_t *res);
4462623SN/A
4472623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4482623SN/A
4492623SN/Atemplate<>
4502623SN/AFault
4512623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
4522623SN/A{
4532623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
4542623SN/A}
4552623SN/A
4562623SN/Atemplate<>
4572623SN/AFault
4582623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
4592623SN/A{
4602623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
4612623SN/A}
4622623SN/A
4632623SN/A
4642623SN/Atemplate<>
4652623SN/AFault
4662623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
4672623SN/A{
4682623SN/A    return write((uint32_t)data, addr, flags, res);
4692623SN/A}
4702623SN/A
4712623SN/A
4722623SN/Avoid
4732623SN/AAtomicSimpleCPU::tick()
4742623SN/A{
4752623SN/A    Tick latency = cycles(1); // instruction takes one cycle by default
4762623SN/A
4772623SN/A    for (int i = 0; i < width; ++i) {
4782623SN/A        numCycles++;
4792623SN/A
4803387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
4813387Sgblack@eecs.umich.edu            checkForInterrupts();
4822626SN/A
4832662Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(ifetch_req);
4842623SN/A
4852623SN/A        if (fault == NoFault) {
4862662Sstever@eecs.umich.edu            ifetch_pkt->reinitFromRequest();
4872662Sstever@eecs.umich.edu
4882662Sstever@eecs.umich.edu            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
4892623SN/A            // ifetch_req is initialized to read the instruction directly
4902623SN/A            // into the CPU object's inst field.
4912623SN/A
4922623SN/A            dcache_access = false; // assume no dcache access
4932623SN/A            preExecute();
4943814Ssaidi@eecs.umich.edu
4952623SN/A            fault = curStaticInst->execute(this, traceData);
4962623SN/A            postExecute();
4972623SN/A
4983814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
4993814Ssaidi@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroOp() ||
5003901Ssaidi@eecs.umich.edu                        curStaticInst->isFirstMicroOp()))
5013814Ssaidi@eecs.umich.edu                instCnt++;
5023814Ssaidi@eecs.umich.edu
5032623SN/A            if (simulate_stalls) {
5042662Sstever@eecs.umich.edu                Tick icache_stall = icache_latency - cycles(1);
5052623SN/A                Tick dcache_stall =
5062662Sstever@eecs.umich.edu                    dcache_access ? dcache_latency - cycles(1) : 0;
5072803Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
5082803Ssaidi@eecs.umich.edu                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
5092803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles+1);
5102803Ssaidi@eecs.umich.edu                else
5112803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles);
5122623SN/A            }
5132623SN/A
5142623SN/A        }
5152623SN/A
5162623SN/A        advancePC(fault);
5172623SN/A    }
5182623SN/A
5192626SN/A    if (_status != Idle)
5202626SN/A        tickEvent.schedule(curTick + latency);
5212623SN/A}
5222623SN/A
5232623SN/A
5242623SN/A////////////////////////////////////////////////////////////////////////
5252623SN/A//
5262623SN/A//  AtomicSimpleCPU Simulation Object
5272623SN/A//
5282623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5292623SN/A
5302623SN/A    Param<Counter> max_insts_any_thread;
5312623SN/A    Param<Counter> max_insts_all_threads;
5322623SN/A    Param<Counter> max_loads_any_thread;
5332623SN/A    Param<Counter> max_loads_all_threads;
5343119Sktlim@umich.edu    Param<Tick> progress_interval;
5352901Ssaidi@eecs.umich.edu    SimObjectParam<System *> system;
5363170Sstever@eecs.umich.edu    Param<int> cpu_id;
5372623SN/A
5382623SN/A#if FULL_SYSTEM
5393453Sgblack@eecs.umich.edu    SimObjectParam<TheISA::ITB *> itb;
5403453Sgblack@eecs.umich.edu    SimObjectParam<TheISA::DTB *> dtb;
5412623SN/A    Param<Tick> profile;
5423617Sbinkertn@umich.edu
5433617Sbinkertn@umich.edu    Param<bool> do_quiesce;
5443617Sbinkertn@umich.edu    Param<bool> do_checkpoint_insts;
5453617Sbinkertn@umich.edu    Param<bool> do_statistics_insts;
5462623SN/A#else
5472623SN/A    SimObjectParam<Process *> workload;
5482623SN/A#endif // FULL_SYSTEM
5492623SN/A
5502623SN/A    Param<int> clock;
5513661Srdreslin@umich.edu    Param<int> phase;
5522623SN/A
5532623SN/A    Param<bool> defer_registration;
5542623SN/A    Param<int> width;
5552623SN/A    Param<bool> function_trace;
5562623SN/A    Param<Tick> function_trace_start;
5572623SN/A    Param<bool> simulate_stalls;
5582623SN/A
5592623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5602623SN/A
5612623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5622623SN/A
5632623SN/A    INIT_PARAM(max_insts_any_thread,
5642623SN/A               "terminate when any thread reaches this inst count"),
5652623SN/A    INIT_PARAM(max_insts_all_threads,
5662623SN/A               "terminate when all threads have reached this inst count"),
5672623SN/A    INIT_PARAM(max_loads_any_thread,
5682623SN/A               "terminate when any thread reaches this load count"),
5692623SN/A    INIT_PARAM(max_loads_all_threads,
5702623SN/A               "terminate when all threads have reached this load count"),
5713119Sktlim@umich.edu    INIT_PARAM(progress_interval, "Progress interval"),
5722901Ssaidi@eecs.umich.edu    INIT_PARAM(system, "system object"),
5733170Sstever@eecs.umich.edu    INIT_PARAM(cpu_id, "processor ID"),
5742623SN/A
5752623SN/A#if FULL_SYSTEM
5762623SN/A    INIT_PARAM(itb, "Instruction TLB"),
5772623SN/A    INIT_PARAM(dtb, "Data TLB"),
5782623SN/A    INIT_PARAM(profile, ""),
5793617Sbinkertn@umich.edu    INIT_PARAM(do_quiesce, ""),
5803617Sbinkertn@umich.edu    INIT_PARAM(do_checkpoint_insts, ""),
5813617Sbinkertn@umich.edu    INIT_PARAM(do_statistics_insts, ""),
5822623SN/A#else
5832623SN/A    INIT_PARAM(workload, "processes to run"),
5842623SN/A#endif // FULL_SYSTEM
5852623SN/A
5862623SN/A    INIT_PARAM(clock, "clock speed"),
5873661Srdreslin@umich.edu    INIT_PARAM_DFLT(phase, "clock phase", 0),
5882623SN/A    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
5892623SN/A    INIT_PARAM(width, "cpu width"),
5902623SN/A    INIT_PARAM(function_trace, "Enable function trace"),
5912623SN/A    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
5922623SN/A    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
5932623SN/A
5942623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5952623SN/A
5962623SN/A
5972623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU)
5982623SN/A{
5992623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
6002623SN/A    params->name = getInstanceName();
6012623SN/A    params->numberOfThreads = 1;
6022623SN/A    params->max_insts_any_thread = max_insts_any_thread;
6032623SN/A    params->max_insts_all_threads = max_insts_all_threads;
6042623SN/A    params->max_loads_any_thread = max_loads_any_thread;
6052623SN/A    params->max_loads_all_threads = max_loads_all_threads;
6063119Sktlim@umich.edu    params->progress_interval = progress_interval;
6072623SN/A    params->deferRegistration = defer_registration;
6083661Srdreslin@umich.edu    params->phase = phase;
6092623SN/A    params->clock = clock;
6102623SN/A    params->functionTrace = function_trace;
6112623SN/A    params->functionTraceStart = function_trace_start;
6122623SN/A    params->width = width;
6132623SN/A    params->simulate_stalls = simulate_stalls;
6142901Ssaidi@eecs.umich.edu    params->system = system;
6153170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
6162623SN/A
6172623SN/A#if FULL_SYSTEM
6182623SN/A    params->itb = itb;
6192623SN/A    params->dtb = dtb;
6202623SN/A    params->profile = profile;
6213617Sbinkertn@umich.edu    params->do_quiesce = do_quiesce;
6223617Sbinkertn@umich.edu    params->do_checkpoint_insts = do_checkpoint_insts;
6233617Sbinkertn@umich.edu    params->do_statistics_insts = do_statistics_insts;
6242623SN/A#else
6252623SN/A    params->process = workload;
6262623SN/A#endif
6272623SN/A
6282623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
6292623SN/A    return cpu;
6302623SN/A}
6312623SN/A
6322623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
6332623SN/A
634