atomic.cc revision 3431
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
322623SN/A#include "arch/utility.hh"
332623SN/A#include "cpu/exetrace.hh"
342623SN/A#include "cpu/simple/atomic.hh"
353348Sbinkertn@umich.edu#include "mem/packet.hh"
363348Sbinkertn@umich.edu#include "mem/packet_access.hh"
372623SN/A#include "sim/builder.hh"
382901Ssaidi@eecs.umich.edu#include "sim/system.hh"
392623SN/A
402623SN/Ausing namespace std;
412623SN/Ausing namespace TheISA;
422623SN/A
432623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
442623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
452623SN/A{
462623SN/A}
472623SN/A
482623SN/A
492623SN/Avoid
502623SN/AAtomicSimpleCPU::TickEvent::process()
512623SN/A{
522623SN/A    cpu->tick();
532623SN/A}
542623SN/A
552623SN/Aconst char *
562623SN/AAtomicSimpleCPU::TickEvent::description()
572623SN/A{
582623SN/A    return "AtomicSimpleCPU tick event";
592623SN/A}
602623SN/A
612856Srdreslin@umich.eduPort *
622856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
632856Srdreslin@umich.edu{
642856Srdreslin@umich.edu    if (if_name == "dcache_port")
652856Srdreslin@umich.edu        return &dcachePort;
662856Srdreslin@umich.edu    else if (if_name == "icache_port")
672856Srdreslin@umich.edu        return &icachePort;
682856Srdreslin@umich.edu    else
692856Srdreslin@umich.edu        panic("No Such Port\n");
702856Srdreslin@umich.edu}
712623SN/A
722623SN/Avoid
732623SN/AAtomicSimpleCPU::init()
742623SN/A{
752623SN/A    //Create Memory Ports (conect them up)
762856Srdreslin@umich.edu//    Port *mem_dport = mem->getPort("");
772856Srdreslin@umich.edu//    dcachePort.setPeer(mem_dport);
782856Srdreslin@umich.edu//    mem_dport->setPeer(&dcachePort);
792623SN/A
802856Srdreslin@umich.edu//    Port *mem_iport = mem->getPort("");
812856Srdreslin@umich.edu//    icachePort.setPeer(mem_iport);
822856Srdreslin@umich.edu//    mem_iport->setPeer(&icachePort);
832623SN/A
842623SN/A    BaseCPU::init();
852623SN/A#if FULL_SYSTEM
862680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
872680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
882623SN/A
892623SN/A        // initialize CPU, including PC
902680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
912623SN/A    }
922623SN/A#endif
932623SN/A}
942623SN/A
952623SN/Abool
963349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
972623SN/A{
983184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
992623SN/A    return true;
1002623SN/A}
1012623SN/A
1022623SN/ATick
1033349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
1042623SN/A{
1053310Srdreslin@umich.edu    //Snooping a coherence request, just return
1062623SN/A    return curTick;
1072623SN/A}
1082623SN/A
1092623SN/Avoid
1103349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1112623SN/A{
1123184Srdreslin@umich.edu    //No internal storage to update, just return
1133184Srdreslin@umich.edu    return;
1142623SN/A}
1152623SN/A
1162623SN/Avoid
1172623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1182623SN/A{
1192626SN/A    if (status == RangeChange)
1202626SN/A        return;
1212626SN/A
1222623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1232623SN/A}
1242623SN/A
1252657Ssaidi@eecs.umich.eduvoid
1262623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1272623SN/A{
1282623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1292623SN/A}
1302623SN/A
1312623SN/A
1322623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1332623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1342623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1352640Sstever@eecs.umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
1362623SN/A{
1372623SN/A    _status = Idle;
1382623SN/A
1392663Sstever@eecs.umich.edu    ifetch_req = new Request();
1403170Sstever@eecs.umich.edu    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
1412641Sstever@eecs.umich.edu    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
1422623SN/A    ifetch_pkt->dataStatic(&inst);
1432623SN/A
1442663Sstever@eecs.umich.edu    data_read_req = new Request();
1453170Sstever@eecs.umich.edu    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1462641Sstever@eecs.umich.edu    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
1472641Sstever@eecs.umich.edu                               Packet::Broadcast);
1482623SN/A    data_read_pkt->dataStatic(&dataReg);
1492623SN/A
1502663Sstever@eecs.umich.edu    data_write_req = new Request();
1513170Sstever@eecs.umich.edu    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
1522641Sstever@eecs.umich.edu    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
1532641Sstever@eecs.umich.edu                                Packet::Broadcast);
1542623SN/A}
1552623SN/A
1562623SN/A
1572623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1582623SN/A{
1592623SN/A}
1602623SN/A
1612623SN/Avoid
1622623SN/AAtomicSimpleCPU::serialize(ostream &os)
1632623SN/A{
1642915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1652915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1663177Shsul@eecs.umich.edu    Status _status = status();
1673177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1683145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1692623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1702623SN/A    tickEvent.serialize(os);
1712623SN/A}
1722623SN/A
1732623SN/Avoid
1742623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1752623SN/A{
1762915Sktlim@umich.edu    SimObject::State so_state;
1772915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1783177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1793145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1802915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1812915Sktlim@umich.edu}
1822915Sktlim@umich.edu
1832915Sktlim@umich.eduvoid
1842915Sktlim@umich.eduAtomicSimpleCPU::resume()
1852915Sktlim@umich.edu{
1863324Shsul@eecs.umich.edu    if (_status != SwitchedOut && _status != Idle) {
1873201Shsul@eecs.umich.edu        assert(system->getMemoryMode() == System::Atomic);
1883324Shsul@eecs.umich.edu
1893324Shsul@eecs.umich.edu        changeState(SimObject::Running);
1903324Shsul@eecs.umich.edu        if (thread->status() == ThreadContext::Active) {
1913431Sgblack@eecs.umich.edu            if (!tickEvent.scheduled()) {
1923431Sgblack@eecs.umich.edu                Tick nextTick = curTick + cycles(1) - 1;
1933431Sgblack@eecs.umich.edu                nextTick -= (nextTick % (cycles(1)));
1943431Sgblack@eecs.umich.edu                tickEvent.schedule(nextTick);
1953431Sgblack@eecs.umich.edu            }
1963324Shsul@eecs.umich.edu        }
1972915Sktlim@umich.edu    }
1982623SN/A}
1992623SN/A
2002623SN/Avoid
2012798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2022623SN/A{
2032798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2042798Sktlim@umich.edu    _status = SwitchedOut;
2052623SN/A
2062798Sktlim@umich.edu    tickEvent.squash();
2072623SN/A}
2082623SN/A
2092623SN/A
2102623SN/Avoid
2112623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2122623SN/A{
2132623SN/A    BaseCPU::takeOverFrom(oldCPU);
2142623SN/A
2152623SN/A    assert(!tickEvent.scheduled());
2162623SN/A
2172680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2182623SN/A    // running and schedule its tick event.
2192680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2202680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2212680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2222623SN/A            _status = Running;
2233431Sgblack@eecs.umich.edu            Tick nextTick = curTick + cycles(1) - 1;
2243431Sgblack@eecs.umich.edu            nextTick -= (nextTick % (cycles(1)));
2253431Sgblack@eecs.umich.edu            tickEvent.schedule(nextTick);
2262623SN/A            break;
2272623SN/A        }
2282623SN/A    }
2292623SN/A}
2302623SN/A
2312623SN/A
2322623SN/Avoid
2332623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2342623SN/A{
2352623SN/A    assert(thread_num == 0);
2362683Sktlim@umich.edu    assert(thread);
2372623SN/A
2382623SN/A    assert(_status == Idle);
2392623SN/A    assert(!tickEvent.scheduled());
2402623SN/A
2412623SN/A    notIdleFraction++;
2423430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2433430Sgblack@eecs.umich.edu    Tick nextTick = curTick + cycles(1) - 1;
2443430Sgblack@eecs.umich.edu    nextTick -= (nextTick % (cycles(1)));
2453431Sgblack@eecs.umich.edu    tickEvent.schedule(nextTick);
2462623SN/A    _status = Running;
2472623SN/A}
2482623SN/A
2492623SN/A
2502623SN/Avoid
2512623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2522623SN/A{
2532623SN/A    assert(thread_num == 0);
2542683Sktlim@umich.edu    assert(thread);
2552623SN/A
2562623SN/A    assert(_status == Running);
2572626SN/A
2582626SN/A    // tick event may not be scheduled if this gets called from inside
2592626SN/A    // an instruction's execution, e.g. "quiesce"
2602626SN/A    if (tickEvent.scheduled())
2612626SN/A        tickEvent.deschedule();
2622623SN/A
2632623SN/A    notIdleFraction--;
2642623SN/A    _status = Idle;
2652623SN/A}
2662623SN/A
2672623SN/A
2682623SN/Atemplate <class T>
2692623SN/AFault
2702623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2712623SN/A{
2723169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2733169Sstever@eecs.umich.edu    Request *req = data_read_req;
2743349Sbinkertn@umich.edu    PacketPtr pkt = data_read_pkt;
2753169Sstever@eecs.umich.edu
2763169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
2772623SN/A
2782623SN/A    if (traceData) {
2792623SN/A        traceData->setAddr(addr);
2802623SN/A    }
2812623SN/A
2822623SN/A    // translate to physical address
2833169Sstever@eecs.umich.edu    Fault fault = thread->translateDataReadReq(req);
2842623SN/A
2852623SN/A    // Now do the access.
2862623SN/A    if (fault == NoFault) {
2873169Sstever@eecs.umich.edu        pkt->reinitFromRequest();
2882623SN/A
2893169Sstever@eecs.umich.edu        dcache_latency = dcachePort.sendAtomic(pkt);
2902623SN/A        dcache_access = true;
2912623SN/A
2923169Sstever@eecs.umich.edu        assert(pkt->result == Packet::Success);
2933169Sstever@eecs.umich.edu        data = pkt->get<T>();
2943170Sstever@eecs.umich.edu
2953170Sstever@eecs.umich.edu        if (req->isLocked()) {
2963170Sstever@eecs.umich.edu            TheISA::handleLockedRead(thread, req);
2973170Sstever@eecs.umich.edu        }
2982623SN/A    }
2992623SN/A
3002623SN/A    // This will need a new way to tell if it has a dcache attached.
3013172Sstever@eecs.umich.edu    if (req->isUncacheable())
3022623SN/A        recordEvent("Uncached Read");
3032623SN/A
3042623SN/A    return fault;
3052623SN/A}
3062623SN/A
3072623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3082623SN/A
3092623SN/Atemplate
3102623SN/AFault
3112623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
3122623SN/A
3132623SN/Atemplate
3142623SN/AFault
3152623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
3162623SN/A
3172623SN/Atemplate
3182623SN/AFault
3192623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
3202623SN/A
3212623SN/Atemplate
3222623SN/AFault
3232623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
3242623SN/A
3252623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
3262623SN/A
3272623SN/Atemplate<>
3282623SN/AFault
3292623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
3302623SN/A{
3312623SN/A    return read(addr, *(uint64_t*)&data, flags);
3322623SN/A}
3332623SN/A
3342623SN/Atemplate<>
3352623SN/AFault
3362623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
3372623SN/A{
3382623SN/A    return read(addr, *(uint32_t*)&data, flags);
3392623SN/A}
3402623SN/A
3412623SN/A
3422623SN/Atemplate<>
3432623SN/AFault
3442623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
3452623SN/A{
3462623SN/A    return read(addr, (uint32_t&)data, flags);
3472623SN/A}
3482623SN/A
3492623SN/A
3502623SN/Atemplate <class T>
3512623SN/AFault
3522623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
3532623SN/A{
3543169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
3553169Sstever@eecs.umich.edu    Request *req = data_write_req;
3563349Sbinkertn@umich.edu    PacketPtr pkt = data_write_pkt;
3573169Sstever@eecs.umich.edu
3583169Sstever@eecs.umich.edu    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
3592623SN/A
3602623SN/A    if (traceData) {
3612623SN/A        traceData->setAddr(addr);
3622623SN/A    }
3632623SN/A
3642623SN/A    // translate to physical address
3653169Sstever@eecs.umich.edu    Fault fault = thread->translateDataWriteReq(req);
3662623SN/A
3672623SN/A    // Now do the access.
3682623SN/A    if (fault == NoFault) {
3693170Sstever@eecs.umich.edu        bool do_access = true;  // flag to suppress cache access
3702623SN/A
3713170Sstever@eecs.umich.edu        if (req->isLocked()) {
3723170Sstever@eecs.umich.edu            do_access = TheISA::handleLockedWrite(thread, req);
3733170Sstever@eecs.umich.edu        }
3742623SN/A
3753170Sstever@eecs.umich.edu        if (do_access) {
3763170Sstever@eecs.umich.edu            data = htog(data);
3773170Sstever@eecs.umich.edu            pkt->reinitFromRequest();
3783170Sstever@eecs.umich.edu            pkt->dataStatic(&data);
3792631SN/A
3803170Sstever@eecs.umich.edu            dcache_latency = dcachePort.sendAtomic(pkt);
3813170Sstever@eecs.umich.edu            dcache_access = true;
3823170Sstever@eecs.umich.edu
3833170Sstever@eecs.umich.edu            assert(pkt->result == Packet::Success);
3843170Sstever@eecs.umich.edu        }
3853170Sstever@eecs.umich.edu
3863170Sstever@eecs.umich.edu        if (req->isLocked()) {
3873170Sstever@eecs.umich.edu            uint64_t scResult = req->getScResult();
3883170Sstever@eecs.umich.edu            if (scResult != 0) {
3893170Sstever@eecs.umich.edu                // clear failure counter
3903170Sstever@eecs.umich.edu                thread->setStCondFailures(0);
3913170Sstever@eecs.umich.edu            }
3923170Sstever@eecs.umich.edu            if (res) {
3933170Sstever@eecs.umich.edu                *res = req->getScResult();
3943170Sstever@eecs.umich.edu            }
3952631SN/A        }
3962623SN/A    }
3972623SN/A
3982623SN/A    // This will need a new way to tell if it's hooked up to a cache or not.
3993172Sstever@eecs.umich.edu    if (req->isUncacheable())
4002623SN/A        recordEvent("Uncached Write");
4012623SN/A
4022623SN/A    // If the write needs to have a fault on the access, consider calling
4032623SN/A    // changeStatus() and changing it to "bad addr write" or something.
4042623SN/A    return fault;
4052623SN/A}
4062623SN/A
4072623SN/A
4082623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
4092623SN/Atemplate
4102623SN/AFault
4112623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
4122623SN/A                       unsigned flags, uint64_t *res);
4132623SN/A
4142623SN/Atemplate
4152623SN/AFault
4162623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
4172623SN/A                       unsigned flags, uint64_t *res);
4182623SN/A
4192623SN/Atemplate
4202623SN/AFault
4212623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
4222623SN/A                       unsigned flags, uint64_t *res);
4232623SN/A
4242623SN/Atemplate
4252623SN/AFault
4262623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
4272623SN/A                       unsigned flags, uint64_t *res);
4282623SN/A
4292623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4302623SN/A
4312623SN/Atemplate<>
4322623SN/AFault
4332623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
4342623SN/A{
4352623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
4362623SN/A}
4372623SN/A
4382623SN/Atemplate<>
4392623SN/AFault
4402623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
4412623SN/A{
4422623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
4432623SN/A}
4442623SN/A
4452623SN/A
4462623SN/Atemplate<>
4472623SN/AFault
4482623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
4492623SN/A{
4502623SN/A    return write((uint32_t)data, addr, flags, res);
4512623SN/A}
4522623SN/A
4532623SN/A
4542623SN/Avoid
4552623SN/AAtomicSimpleCPU::tick()
4562623SN/A{
4572623SN/A    Tick latency = cycles(1); // instruction takes one cycle by default
4582623SN/A
4592623SN/A    for (int i = 0; i < width; ++i) {
4602623SN/A        numCycles++;
4612623SN/A
4623387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
4633387Sgblack@eecs.umich.edu            checkForInterrupts();
4642626SN/A
4652662Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(ifetch_req);
4662623SN/A
4672623SN/A        if (fault == NoFault) {
4682662Sstever@eecs.umich.edu            ifetch_pkt->reinitFromRequest();
4692662Sstever@eecs.umich.edu
4702662Sstever@eecs.umich.edu            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
4712623SN/A            // ifetch_req is initialized to read the instruction directly
4722623SN/A            // into the CPU object's inst field.
4732623SN/A
4742623SN/A            dcache_access = false; // assume no dcache access
4752623SN/A            preExecute();
4762623SN/A            fault = curStaticInst->execute(this, traceData);
4772623SN/A            postExecute();
4782623SN/A
4792623SN/A            if (simulate_stalls) {
4802662Sstever@eecs.umich.edu                Tick icache_stall = icache_latency - cycles(1);
4812623SN/A                Tick dcache_stall =
4822662Sstever@eecs.umich.edu                    dcache_access ? dcache_latency - cycles(1) : 0;
4832803Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
4842803Ssaidi@eecs.umich.edu                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
4852803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles+1);
4862803Ssaidi@eecs.umich.edu                else
4872803Ssaidi@eecs.umich.edu                    latency += cycles(stall_cycles);
4882623SN/A            }
4892623SN/A
4902623SN/A        }
4912623SN/A
4922623SN/A        advancePC(fault);
4932623SN/A    }
4942623SN/A
4952626SN/A    if (_status != Idle)
4962626SN/A        tickEvent.schedule(curTick + latency);
4972623SN/A}
4982623SN/A
4992623SN/A
5002623SN/A////////////////////////////////////////////////////////////////////////
5012623SN/A//
5022623SN/A//  AtomicSimpleCPU Simulation Object
5032623SN/A//
5042623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5052623SN/A
5062623SN/A    Param<Counter> max_insts_any_thread;
5072623SN/A    Param<Counter> max_insts_all_threads;
5082623SN/A    Param<Counter> max_loads_any_thread;
5092623SN/A    Param<Counter> max_loads_all_threads;
5103119Sktlim@umich.edu    Param<Tick> progress_interval;
5112623SN/A    SimObjectParam<MemObject *> mem;
5122901Ssaidi@eecs.umich.edu    SimObjectParam<System *> system;
5133170Sstever@eecs.umich.edu    Param<int> cpu_id;
5142623SN/A
5152623SN/A#if FULL_SYSTEM
5162623SN/A    SimObjectParam<AlphaITB *> itb;
5172623SN/A    SimObjectParam<AlphaDTB *> dtb;
5182623SN/A    Param<Tick> profile;
5192623SN/A#else
5202623SN/A    SimObjectParam<Process *> workload;
5212623SN/A#endif // FULL_SYSTEM
5222623SN/A
5232623SN/A    Param<int> clock;
5242623SN/A
5252623SN/A    Param<bool> defer_registration;
5262623SN/A    Param<int> width;
5272623SN/A    Param<bool> function_trace;
5282623SN/A    Param<Tick> function_trace_start;
5292623SN/A    Param<bool> simulate_stalls;
5302623SN/A
5312623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5322623SN/A
5332623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5342623SN/A
5352623SN/A    INIT_PARAM(max_insts_any_thread,
5362623SN/A               "terminate when any thread reaches this inst count"),
5372623SN/A    INIT_PARAM(max_insts_all_threads,
5382623SN/A               "terminate when all threads have reached this inst count"),
5392623SN/A    INIT_PARAM(max_loads_any_thread,
5402623SN/A               "terminate when any thread reaches this load count"),
5412623SN/A    INIT_PARAM(max_loads_all_threads,
5422623SN/A               "terminate when all threads have reached this load count"),
5433119Sktlim@umich.edu    INIT_PARAM(progress_interval, "Progress interval"),
5442623SN/A    INIT_PARAM(mem, "memory"),
5452901Ssaidi@eecs.umich.edu    INIT_PARAM(system, "system object"),
5463170Sstever@eecs.umich.edu    INIT_PARAM(cpu_id, "processor ID"),
5472623SN/A
5482623SN/A#if FULL_SYSTEM
5492623SN/A    INIT_PARAM(itb, "Instruction TLB"),
5502623SN/A    INIT_PARAM(dtb, "Data TLB"),
5512623SN/A    INIT_PARAM(profile, ""),
5522623SN/A#else
5532623SN/A    INIT_PARAM(workload, "processes to run"),
5542623SN/A#endif // FULL_SYSTEM
5552623SN/A
5562623SN/A    INIT_PARAM(clock, "clock speed"),
5572623SN/A    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
5582623SN/A    INIT_PARAM(width, "cpu width"),
5592623SN/A    INIT_PARAM(function_trace, "Enable function trace"),
5602623SN/A    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
5612623SN/A    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
5622623SN/A
5632623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
5642623SN/A
5652623SN/A
5662623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU)
5672623SN/A{
5682623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
5692623SN/A    params->name = getInstanceName();
5702623SN/A    params->numberOfThreads = 1;
5712623SN/A    params->max_insts_any_thread = max_insts_any_thread;
5722623SN/A    params->max_insts_all_threads = max_insts_all_threads;
5732623SN/A    params->max_loads_any_thread = max_loads_any_thread;
5742623SN/A    params->max_loads_all_threads = max_loads_all_threads;
5753119Sktlim@umich.edu    params->progress_interval = progress_interval;
5762623SN/A    params->deferRegistration = defer_registration;
5772623SN/A    params->clock = clock;
5782623SN/A    params->functionTrace = function_trace;
5792623SN/A    params->functionTraceStart = function_trace_start;
5802623SN/A    params->width = width;
5812623SN/A    params->simulate_stalls = simulate_stalls;
5822623SN/A    params->mem = mem;
5832901Ssaidi@eecs.umich.edu    params->system = system;
5843170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
5852623SN/A
5862623SN/A#if FULL_SYSTEM
5872623SN/A    params->itb = itb;
5882623SN/A    params->dtb = dtb;
5892623SN/A    params->profile = profile;
5902623SN/A#else
5912623SN/A    params->process = workload;
5922623SN/A#endif
5932623SN/A
5942623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
5952623SN/A    return cpu;
5962623SN/A}
5972623SN/A
5982623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
5992623SN/A
600