atomic.cc revision 3349
17087Snate@binkert.org/* 27087Snate@binkert.org * Copyright (c) 2002-2005 The Regents of The University of Michigan 37087Snate@binkert.org * All rights reserved. 47087Snate@binkert.org * 57087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org * modification, are permitted provided that the following conditions are 77087Snate@binkert.org * met: redistributions of source code must retain the above copyright 87087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org * documentation and/or other materials provided with the distribution; 127087Snate@binkert.org * neither the name of the copyright holders nor the names of its 134158Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144158Sgblack@eecs.umich.edu * this software without specific prior written permission. 154158Sgblack@eecs.umich.edu * 164158Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174158Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184158Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194158Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204158Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214158Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224158Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234158Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244158Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254158Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264158Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274158Sgblack@eecs.umich.edu * 284158Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 294158Sgblack@eecs.umich.edu */ 304158Sgblack@eecs.umich.edu 314158Sgblack@eecs.umich.edu#include "arch/locked_mem.hh" 324158Sgblack@eecs.umich.edu#include "arch/utility.hh" 334158Sgblack@eecs.umich.edu#include "cpu/exetrace.hh" 344158Sgblack@eecs.umich.edu#include "cpu/simple/atomic.hh" 354158Sgblack@eecs.umich.edu#include "mem/packet.hh" 364158Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 374158Sgblack@eecs.umich.edu#include "sim/builder.hh" 384158Sgblack@eecs.umich.edu#include "sim/system.hh" 394158Sgblack@eecs.umich.edu 404158Sgblack@eecs.umich.eduusing namespace std; 414158Sgblack@eecs.umich.eduusing namespace TheISA; 424158Sgblack@eecs.umich.edu 434323Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 444323Sgblack@eecs.umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 454158Sgblack@eecs.umich.edu{ 464158Sgblack@eecs.umich.edu} 474323Sgblack@eecs.umich.edu 484323Sgblack@eecs.umich.edu 494323Sgblack@eecs.umich.eduvoid 504323Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::process() 514158Sgblack@eecs.umich.edu{ 524158Sgblack@eecs.umich.edu cpu->tick(); 538229Snate@binkert.org} 544158Sgblack@eecs.umich.edu 554158Sgblack@eecs.umich.educonst char * 567965Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::description() 575786Sgblack@eecs.umich.edu{ 585083Sgblack@eecs.umich.edu return "AtomicSimpleCPU tick event"; 594679Sgblack@eecs.umich.edu} 606516Sgblack@eecs.umich.edu 614679Sgblack@eecs.umich.eduPort * 624679Sgblack@eecs.umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 638229Snate@binkert.org{ 644158Sgblack@eecs.umich.edu if (if_name == "dcache_port") 656329Sgblack@eecs.umich.edu return &dcachePort; 664528Sgblack@eecs.umich.edu else if (if_name == "icache_port") 674158Sgblack@eecs.umich.edu return &icachePort; 684158Sgblack@eecs.umich.edu else 694158Sgblack@eecs.umich.edu panic("No Such Port\n"); 704616Sgblack@eecs.umich.edu} 716345Sgblack@eecs.umich.edu 726345Sgblack@eecs.umich.eduvoid 734158Sgblack@eecs.umich.eduAtomicSimpleCPU::init() 744158Sgblack@eecs.umich.edu{ 754158Sgblack@eecs.umich.edu //Create Memory Ports (conect them up) 767629Sgblack@eecs.umich.edu// Port *mem_dport = mem->getPort(""); 777629Sgblack@eecs.umich.edu// dcachePort.setPeer(mem_dport); 787629Sgblack@eecs.umich.edu// mem_dport->setPeer(&dcachePort); 798229Snate@binkert.org 808229Snate@binkert.org// Port *mem_iport = mem->getPort(""); 815912Sgblack@eecs.umich.edu// icachePort.setPeer(mem_iport); 828229Snate@binkert.org// mem_iport->setPeer(&icachePort); 834158Sgblack@eecs.umich.edu 845425Sgblack@eecs.umich.edu BaseCPU::init(); 854158Sgblack@eecs.umich.edu#if FULL_SYSTEM 864158Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 874158Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 884158Sgblack@eecs.umich.edu 894158Sgblack@eecs.umich.edu // initialize CPU, including PC 904158Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->readCpuId()); 914158Sgblack@eecs.umich.edu } 924158Sgblack@eecs.umich.edu#endif 934158Sgblack@eecs.umich.edu} 944158Sgblack@eecs.umich.edu 954158Sgblack@eecs.umich.edubool 964158Sgblack@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 974158Sgblack@eecs.umich.edu{ 984158Sgblack@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 994158Sgblack@eecs.umich.edu return true; 1004158Sgblack@eecs.umich.edu} 1014158Sgblack@eecs.umich.edu 1024158Sgblack@eecs.umich.eduTick 1034158Sgblack@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 1044158Sgblack@eecs.umich.edu{ 1054158Sgblack@eecs.umich.edu //Snooping a coherence request, just return 1064158Sgblack@eecs.umich.edu return curTick; 1074158Sgblack@eecs.umich.edu} 1084158Sgblack@eecs.umich.edu 1098229Snate@binkert.orgvoid 1104158Sgblack@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1114158Sgblack@eecs.umich.edu{ 1128229Snate@binkert.org //No internal storage to update, just return 1135659Sgblack@eecs.umich.edu return; 1146336Sgblack@eecs.umich.edu} 1155118Sgblack@eecs.umich.edu 1164158Sgblack@eecs.umich.eduvoid 1177969Sgblack@eecs.umich.eduAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1186570Sgblack@eecs.umich.edu{ 1194158Sgblack@eecs.umich.edu if (status == RangeChange) 1204158Sgblack@eecs.umich.edu return; 1218232Snate@binkert.org 1224158Sgblack@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1234158Sgblack@eecs.umich.edu} 1245920Sgblack@eecs.umich.edu 1255789Sgblack@eecs.umich.eduvoid 1268229Snate@binkert.orgAtomicSimpleCPU::CpuPort::recvRetry() 1274158Sgblack@eecs.umich.edu{ 1284158Sgblack@eecs.umich.edu panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1294158Sgblack@eecs.umich.edu} 1304158Sgblack@eecs.umich.edu 1314158Sgblack@eecs.umich.edu 132AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 133 : BaseSimpleCPU(p), tickEvent(this), 134 width(p->width), simulate_stalls(p->simulate_stalls), 135 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 136{ 137 _status = Idle; 138 139 ifetch_req = new Request(); 140 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 141 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 142 ifetch_pkt->dataStatic(&inst); 143 144 data_read_req = new Request(); 145 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 146 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 147 Packet::Broadcast); 148 data_read_pkt->dataStatic(&dataReg); 149 150 data_write_req = new Request(); 151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 152 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 153 Packet::Broadcast); 154} 155 156 157AtomicSimpleCPU::~AtomicSimpleCPU() 158{ 159} 160 161void 162AtomicSimpleCPU::serialize(ostream &os) 163{ 164 SimObject::State so_state = SimObject::getState(); 165 SERIALIZE_ENUM(so_state); 166 Status _status = status(); 167 SERIALIZE_ENUM(_status); 168 BaseSimpleCPU::serialize(os); 169 nameOut(os, csprintf("%s.tickEvent", name())); 170 tickEvent.serialize(os); 171} 172 173void 174AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 175{ 176 SimObject::State so_state; 177 UNSERIALIZE_ENUM(so_state); 178 UNSERIALIZE_ENUM(_status); 179 BaseSimpleCPU::unserialize(cp, section); 180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 181} 182 183void 184AtomicSimpleCPU::resume() 185{ 186 changeState(SimObject::Running); 187 if (thread->status() == ThreadContext::Active) { 188 assert(system->getMemoryMode() == System::Atomic); 189 if (!tickEvent.scheduled()) 190 tickEvent.schedule(curTick); 191 } 192} 193 194void 195AtomicSimpleCPU::switchOut() 196{ 197 assert(status() == Running || status() == Idle); 198 _status = SwitchedOut; 199 200 tickEvent.squash(); 201} 202 203 204void 205AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 206{ 207 BaseCPU::takeOverFrom(oldCPU); 208 209 assert(!tickEvent.scheduled()); 210 211 // if any of this CPU's ThreadContexts are active, mark the CPU as 212 // running and schedule its tick event. 213 for (int i = 0; i < threadContexts.size(); ++i) { 214 ThreadContext *tc = threadContexts[i]; 215 if (tc->status() == ThreadContext::Active && _status != Running) { 216 _status = Running; 217 tickEvent.schedule(curTick); 218 break; 219 } 220 } 221} 222 223 224void 225AtomicSimpleCPU::activateContext(int thread_num, int delay) 226{ 227 assert(thread_num == 0); 228 assert(thread); 229 230 assert(_status == Idle); 231 assert(!tickEvent.scheduled()); 232 233 notIdleFraction++; 234 tickEvent.schedule(curTick + cycles(delay)); 235 _status = Running; 236} 237 238 239void 240AtomicSimpleCPU::suspendContext(int thread_num) 241{ 242 assert(thread_num == 0); 243 assert(thread); 244 245 assert(_status == Running); 246 247 // tick event may not be scheduled if this gets called from inside 248 // an instruction's execution, e.g. "quiesce" 249 if (tickEvent.scheduled()) 250 tickEvent.deschedule(); 251 252 notIdleFraction--; 253 _status = Idle; 254} 255 256 257template <class T> 258Fault 259AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 260{ 261 // use the CPU's statically allocated read request and packet objects 262 Request *req = data_read_req; 263 PacketPtr pkt = data_read_pkt; 264 265 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 266 267 if (traceData) { 268 traceData->setAddr(addr); 269 } 270 271 // translate to physical address 272 Fault fault = thread->translateDataReadReq(req); 273 274 // Now do the access. 275 if (fault == NoFault) { 276 pkt->reinitFromRequest(); 277 278 dcache_latency = dcachePort.sendAtomic(pkt); 279 dcache_access = true; 280 281 assert(pkt->result == Packet::Success); 282 data = pkt->get<T>(); 283 284 if (req->isLocked()) { 285 TheISA::handleLockedRead(thread, req); 286 } 287 } 288 289 // This will need a new way to tell if it has a dcache attached. 290 if (req->isUncacheable()) 291 recordEvent("Uncached Read"); 292 293 return fault; 294} 295 296#ifndef DOXYGEN_SHOULD_SKIP_THIS 297 298template 299Fault 300AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 301 302template 303Fault 304AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 305 306template 307Fault 308AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 309 310template 311Fault 312AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 313 314#endif //DOXYGEN_SHOULD_SKIP_THIS 315 316template<> 317Fault 318AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 319{ 320 return read(addr, *(uint64_t*)&data, flags); 321} 322 323template<> 324Fault 325AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 326{ 327 return read(addr, *(uint32_t*)&data, flags); 328} 329 330 331template<> 332Fault 333AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 334{ 335 return read(addr, (uint32_t&)data, flags); 336} 337 338 339template <class T> 340Fault 341AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 342{ 343 // use the CPU's statically allocated write request and packet objects 344 Request *req = data_write_req; 345 PacketPtr pkt = data_write_pkt; 346 347 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 348 349 if (traceData) { 350 traceData->setAddr(addr); 351 } 352 353 // translate to physical address 354 Fault fault = thread->translateDataWriteReq(req); 355 356 // Now do the access. 357 if (fault == NoFault) { 358 bool do_access = true; // flag to suppress cache access 359 360 if (req->isLocked()) { 361 do_access = TheISA::handleLockedWrite(thread, req); 362 } 363 364 if (do_access) { 365 data = htog(data); 366 pkt->reinitFromRequest(); 367 pkt->dataStatic(&data); 368 369 dcache_latency = dcachePort.sendAtomic(pkt); 370 dcache_access = true; 371 372 assert(pkt->result == Packet::Success); 373 } 374 375 if (req->isLocked()) { 376 uint64_t scResult = req->getScResult(); 377 if (scResult != 0) { 378 // clear failure counter 379 thread->setStCondFailures(0); 380 } 381 if (res) { 382 *res = req->getScResult(); 383 } 384 } 385 } 386 387 // This will need a new way to tell if it's hooked up to a cache or not. 388 if (req->isUncacheable()) 389 recordEvent("Uncached Write"); 390 391 // If the write needs to have a fault on the access, consider calling 392 // changeStatus() and changing it to "bad addr write" or something. 393 return fault; 394} 395 396 397#ifndef DOXYGEN_SHOULD_SKIP_THIS 398template 399Fault 400AtomicSimpleCPU::write(uint64_t data, Addr addr, 401 unsigned flags, uint64_t *res); 402 403template 404Fault 405AtomicSimpleCPU::write(uint32_t data, Addr addr, 406 unsigned flags, uint64_t *res); 407 408template 409Fault 410AtomicSimpleCPU::write(uint16_t data, Addr addr, 411 unsigned flags, uint64_t *res); 412 413template 414Fault 415AtomicSimpleCPU::write(uint8_t data, Addr addr, 416 unsigned flags, uint64_t *res); 417 418#endif //DOXYGEN_SHOULD_SKIP_THIS 419 420template<> 421Fault 422AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 423{ 424 return write(*(uint64_t*)&data, addr, flags, res); 425} 426 427template<> 428Fault 429AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 430{ 431 return write(*(uint32_t*)&data, addr, flags, res); 432} 433 434 435template<> 436Fault 437AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 438{ 439 return write((uint32_t)data, addr, flags, res); 440} 441 442 443void 444AtomicSimpleCPU::tick() 445{ 446 Tick latency = cycles(1); // instruction takes one cycle by default 447 448 for (int i = 0; i < width; ++i) { 449 numCycles++; 450 451 checkForInterrupts(); 452 453 Fault fault = setupFetchRequest(ifetch_req); 454 455 if (fault == NoFault) { 456 ifetch_pkt->reinitFromRequest(); 457 458 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 459 // ifetch_req is initialized to read the instruction directly 460 // into the CPU object's inst field. 461 462 dcache_access = false; // assume no dcache access 463 preExecute(); 464 fault = curStaticInst->execute(this, traceData); 465 postExecute(); 466 467 if (simulate_stalls) { 468 Tick icache_stall = icache_latency - cycles(1); 469 Tick dcache_stall = 470 dcache_access ? dcache_latency - cycles(1) : 0; 471 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 472 if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 473 latency += cycles(stall_cycles+1); 474 else 475 latency += cycles(stall_cycles); 476 } 477 478 } 479 480 advancePC(fault); 481 } 482 483 if (_status != Idle) 484 tickEvent.schedule(curTick + latency); 485} 486 487 488//////////////////////////////////////////////////////////////////////// 489// 490// AtomicSimpleCPU Simulation Object 491// 492BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 493 494 Param<Counter> max_insts_any_thread; 495 Param<Counter> max_insts_all_threads; 496 Param<Counter> max_loads_any_thread; 497 Param<Counter> max_loads_all_threads; 498 Param<Tick> progress_interval; 499 SimObjectParam<MemObject *> mem; 500 SimObjectParam<System *> system; 501 Param<int> cpu_id; 502 503#if FULL_SYSTEM 504 SimObjectParam<AlphaITB *> itb; 505 SimObjectParam<AlphaDTB *> dtb; 506 Param<Tick> profile; 507#else 508 SimObjectParam<Process *> workload; 509#endif // FULL_SYSTEM 510 511 Param<int> clock; 512 513 Param<bool> defer_registration; 514 Param<int> width; 515 Param<bool> function_trace; 516 Param<Tick> function_trace_start; 517 Param<bool> simulate_stalls; 518 519END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 520 521BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 522 523 INIT_PARAM(max_insts_any_thread, 524 "terminate when any thread reaches this inst count"), 525 INIT_PARAM(max_insts_all_threads, 526 "terminate when all threads have reached this inst count"), 527 INIT_PARAM(max_loads_any_thread, 528 "terminate when any thread reaches this load count"), 529 INIT_PARAM(max_loads_all_threads, 530 "terminate when all threads have reached this load count"), 531 INIT_PARAM(progress_interval, "Progress interval"), 532 INIT_PARAM(mem, "memory"), 533 INIT_PARAM(system, "system object"), 534 INIT_PARAM(cpu_id, "processor ID"), 535 536#if FULL_SYSTEM 537 INIT_PARAM(itb, "Instruction TLB"), 538 INIT_PARAM(dtb, "Data TLB"), 539 INIT_PARAM(profile, ""), 540#else 541 INIT_PARAM(workload, "processes to run"), 542#endif // FULL_SYSTEM 543 544 INIT_PARAM(clock, "clock speed"), 545 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 546 INIT_PARAM(width, "cpu width"), 547 INIT_PARAM(function_trace, "Enable function trace"), 548 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 549 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 550 551END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 552 553 554CREATE_SIM_OBJECT(AtomicSimpleCPU) 555{ 556 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 557 params->name = getInstanceName(); 558 params->numberOfThreads = 1; 559 params->max_insts_any_thread = max_insts_any_thread; 560 params->max_insts_all_threads = max_insts_all_threads; 561 params->max_loads_any_thread = max_loads_any_thread; 562 params->max_loads_all_threads = max_loads_all_threads; 563 params->progress_interval = progress_interval; 564 params->deferRegistration = defer_registration; 565 params->clock = clock; 566 params->functionTrace = function_trace; 567 params->functionTraceStart = function_trace_start; 568 params->width = width; 569 params->simulate_stalls = simulate_stalls; 570 params->mem = mem; 571 params->system = system; 572 params->cpu_id = cpu_id; 573 574#if FULL_SYSTEM 575 params->itb = itb; 576 params->dtb = dtb; 577 params->profile = profile; 578#else 579 params->process = workload; 580#endif 581 582 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 583 return cpu; 584} 585 586REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 587 588