atomic.cc revision 2915
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/atomic.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362623SN/A 372623SN/Ausing namespace std; 382623SN/Ausing namespace TheISA; 392623SN/A 402623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 412623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 422623SN/A{ 432623SN/A} 442623SN/A 452623SN/A 462623SN/Avoid 472623SN/AAtomicSimpleCPU::TickEvent::process() 482623SN/A{ 492623SN/A cpu->tick(); 502623SN/A} 512623SN/A 522623SN/Aconst char * 532623SN/AAtomicSimpleCPU::TickEvent::description() 542623SN/A{ 552623SN/A return "AtomicSimpleCPU tick event"; 562623SN/A} 572623SN/A 582856Srdreslin@umich.eduPort * 592856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 602856Srdreslin@umich.edu{ 612856Srdreslin@umich.edu if (if_name == "dcache_port") 622856Srdreslin@umich.edu return &dcachePort; 632856Srdreslin@umich.edu else if (if_name == "icache_port") 642856Srdreslin@umich.edu return &icachePort; 652856Srdreslin@umich.edu else 662856Srdreslin@umich.edu panic("No Such Port\n"); 672856Srdreslin@umich.edu} 682623SN/A 692623SN/Avoid 702623SN/AAtomicSimpleCPU::init() 712623SN/A{ 722623SN/A //Create Memory Ports (conect them up) 732856Srdreslin@umich.edu// Port *mem_dport = mem->getPort(""); 742856Srdreslin@umich.edu// dcachePort.setPeer(mem_dport); 752856Srdreslin@umich.edu// mem_dport->setPeer(&dcachePort); 762623SN/A 772856Srdreslin@umich.edu// Port *mem_iport = mem->getPort(""); 782856Srdreslin@umich.edu// icachePort.setPeer(mem_iport); 792856Srdreslin@umich.edu// mem_iport->setPeer(&icachePort); 802623SN/A 812623SN/A BaseCPU::init(); 822623SN/A#if FULL_SYSTEM 832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 852623SN/A 862623SN/A // initialize CPU, including PC 872680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 882623SN/A } 892623SN/A#endif 902623SN/A} 912623SN/A 922623SN/Abool 932630SN/AAtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 942623SN/A{ 952623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 962623SN/A return true; 972623SN/A} 982623SN/A 992623SN/ATick 1002630SN/AAtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 1012623SN/A{ 1022623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 1032623SN/A return curTick; 1042623SN/A} 1052623SN/A 1062623SN/Avoid 1072630SN/AAtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 1082623SN/A{ 1092623SN/A panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 1102623SN/A} 1112623SN/A 1122623SN/Avoid 1132623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1142623SN/A{ 1152626SN/A if (status == RangeChange) 1162626SN/A return; 1172626SN/A 1182623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1192623SN/A} 1202623SN/A 1212657Ssaidi@eecs.umich.eduvoid 1222623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1232623SN/A{ 1242623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1252623SN/A} 1262623SN/A 1272623SN/A 1282623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1292623SN/A : BaseSimpleCPU(p), tickEvent(this), 1302623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1312640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1322623SN/A{ 1332623SN/A _status = Idle; 1342623SN/A 1352663Sstever@eecs.umich.edu // @todo fix me and get the real cpu id & thread number!!! 1362663Sstever@eecs.umich.edu ifetch_req = new Request(); 1372827Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 1382641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 1392623SN/A ifetch_pkt->dataStatic(&inst); 1402623SN/A 1412663Sstever@eecs.umich.edu data_read_req = new Request(); 1422827Srdreslin@umich.edu data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 1432641Sstever@eecs.umich.edu data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 1442641Sstever@eecs.umich.edu Packet::Broadcast); 1452623SN/A data_read_pkt->dataStatic(&dataReg); 1462623SN/A 1472663Sstever@eecs.umich.edu data_write_req = new Request(); 1482827Srdreslin@umich.edu data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 1492641Sstever@eecs.umich.edu data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 1502641Sstever@eecs.umich.edu Packet::Broadcast); 1512623SN/A} 1522623SN/A 1532623SN/A 1542623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1552623SN/A{ 1562623SN/A} 1572623SN/A 1582623SN/Avoid 1592623SN/AAtomicSimpleCPU::serialize(ostream &os) 1602623SN/A{ 1612915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1622915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1632623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1642623SN/A tickEvent.serialize(os); 1652915Sktlim@umich.edu BaseSimpleCPU::serialize(os); 1662623SN/A} 1672623SN/A 1682623SN/Avoid 1692623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1702623SN/A{ 1712915Sktlim@umich.edu SimObject::State so_state; 1722915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1732915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1742623SN/A BaseSimpleCPU::unserialize(cp, section); 1752915Sktlim@umich.edu} 1762915Sktlim@umich.edu 1772915Sktlim@umich.eduvoid 1782915Sktlim@umich.eduAtomicSimpleCPU::resume() 1792915Sktlim@umich.edu{ 1802915Sktlim@umich.edu if (thread->status() == ThreadContext::Active) { 1812915Sktlim@umich.edu if (!tickEvent.scheduled()) 1822915Sktlim@umich.edu tickEvent.schedule(curTick); 1832915Sktlim@umich.edu } 1842623SN/A} 1852623SN/A 1862623SN/Avoid 1872798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1882623SN/A{ 1892798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1902798Sktlim@umich.edu _status = SwitchedOut; 1912623SN/A 1922798Sktlim@umich.edu tickEvent.squash(); 1932623SN/A} 1942623SN/A 1952623SN/A 1962623SN/Avoid 1972623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1982623SN/A{ 1992623SN/A BaseCPU::takeOverFrom(oldCPU); 2002623SN/A 2012623SN/A assert(!tickEvent.scheduled()); 2022623SN/A 2032680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2042623SN/A // running and schedule its tick event. 2052680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2062680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2072680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2082623SN/A _status = Running; 2092623SN/A tickEvent.schedule(curTick); 2102623SN/A break; 2112623SN/A } 2122623SN/A } 2132623SN/A} 2142623SN/A 2152623SN/A 2162623SN/Avoid 2172623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2182623SN/A{ 2192623SN/A assert(thread_num == 0); 2202683Sktlim@umich.edu assert(thread); 2212623SN/A 2222623SN/A assert(_status == Idle); 2232623SN/A assert(!tickEvent.scheduled()); 2242623SN/A 2252623SN/A notIdleFraction++; 2262623SN/A tickEvent.schedule(curTick + cycles(delay)); 2272623SN/A _status = Running; 2282623SN/A} 2292623SN/A 2302623SN/A 2312623SN/Avoid 2322623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2332623SN/A{ 2342623SN/A assert(thread_num == 0); 2352683Sktlim@umich.edu assert(thread); 2362623SN/A 2372623SN/A assert(_status == Running); 2382626SN/A 2392626SN/A // tick event may not be scheduled if this gets called from inside 2402626SN/A // an instruction's execution, e.g. "quiesce" 2412626SN/A if (tickEvent.scheduled()) 2422626SN/A tickEvent.deschedule(); 2432623SN/A 2442623SN/A notIdleFraction--; 2452623SN/A _status = Idle; 2462623SN/A} 2472623SN/A 2482623SN/A 2492623SN/Atemplate <class T> 2502623SN/AFault 2512623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2522623SN/A{ 2532683Sktlim@umich.edu data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2542623SN/A 2552623SN/A if (traceData) { 2562623SN/A traceData->setAddr(addr); 2572623SN/A } 2582623SN/A 2592623SN/A // translate to physical address 2602683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(data_read_req); 2612623SN/A 2622623SN/A // Now do the access. 2632623SN/A if (fault == NoFault) { 2642641Sstever@eecs.umich.edu data_read_pkt->reinitFromRequest(); 2652623SN/A 2662662Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(data_read_pkt); 2672623SN/A dcache_access = true; 2682623SN/A 2692641Sstever@eecs.umich.edu assert(data_read_pkt->result == Packet::Success); 2702623SN/A data = data_read_pkt->get<T>(); 2712623SN/A 2722623SN/A } 2732623SN/A 2742623SN/A // This will need a new way to tell if it has a dcache attached. 2752623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2762623SN/A recordEvent("Uncached Read"); 2772623SN/A 2782623SN/A return fault; 2792623SN/A} 2802623SN/A 2812623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2822623SN/A 2832623SN/Atemplate 2842623SN/AFault 2852623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2862623SN/A 2872623SN/Atemplate 2882623SN/AFault 2892623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2902623SN/A 2912623SN/Atemplate 2922623SN/AFault 2932623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2942623SN/A 2952623SN/Atemplate 2962623SN/AFault 2972623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2982623SN/A 2992623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3002623SN/A 3012623SN/Atemplate<> 3022623SN/AFault 3032623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3042623SN/A{ 3052623SN/A return read(addr, *(uint64_t*)&data, flags); 3062623SN/A} 3072623SN/A 3082623SN/Atemplate<> 3092623SN/AFault 3102623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3112623SN/A{ 3122623SN/A return read(addr, *(uint32_t*)&data, flags); 3132623SN/A} 3142623SN/A 3152623SN/A 3162623SN/Atemplate<> 3172623SN/AFault 3182623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3192623SN/A{ 3202623SN/A return read(addr, (uint32_t&)data, flags); 3212623SN/A} 3222623SN/A 3232623SN/A 3242623SN/Atemplate <class T> 3252623SN/AFault 3262623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3272623SN/A{ 3282683Sktlim@umich.edu data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3292623SN/A 3302623SN/A if (traceData) { 3312623SN/A traceData->setAddr(addr); 3322623SN/A } 3332623SN/A 3342623SN/A // translate to physical address 3352683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(data_write_req); 3362623SN/A 3372623SN/A // Now do the access. 3382623SN/A if (fault == NoFault) { 3392623SN/A data = htog(data); 3402662Sstever@eecs.umich.edu data_write_pkt->reinitFromRequest(); 3412623SN/A data_write_pkt->dataStatic(&data); 3422623SN/A 3432662Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(data_write_pkt); 3442623SN/A dcache_access = true; 3452623SN/A 3462641Sstever@eecs.umich.edu assert(data_write_pkt->result == Packet::Success); 3472631SN/A 3482631SN/A if (res && data_write_req->getFlags() & LOCKED) { 3492631SN/A *res = data_write_req->getScResult(); 3502631SN/A } 3512623SN/A } 3522623SN/A 3532623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3542623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3552623SN/A recordEvent("Uncached Write"); 3562623SN/A 3572623SN/A // If the write needs to have a fault on the access, consider calling 3582623SN/A // changeStatus() and changing it to "bad addr write" or something. 3592623SN/A return fault; 3602623SN/A} 3612623SN/A 3622623SN/A 3632623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3642623SN/Atemplate 3652623SN/AFault 3662623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 3672623SN/A unsigned flags, uint64_t *res); 3682623SN/A 3692623SN/Atemplate 3702623SN/AFault 3712623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 3722623SN/A unsigned flags, uint64_t *res); 3732623SN/A 3742623SN/Atemplate 3752623SN/AFault 3762623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 3772623SN/A unsigned flags, uint64_t *res); 3782623SN/A 3792623SN/Atemplate 3802623SN/AFault 3812623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 3822623SN/A unsigned flags, uint64_t *res); 3832623SN/A 3842623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3852623SN/A 3862623SN/Atemplate<> 3872623SN/AFault 3882623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3892623SN/A{ 3902623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3912623SN/A} 3922623SN/A 3932623SN/Atemplate<> 3942623SN/AFault 3952623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3962623SN/A{ 3972623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3982623SN/A} 3992623SN/A 4002623SN/A 4012623SN/Atemplate<> 4022623SN/AFault 4032623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4042623SN/A{ 4052623SN/A return write((uint32_t)data, addr, flags, res); 4062623SN/A} 4072623SN/A 4082623SN/A 4092623SN/Avoid 4102623SN/AAtomicSimpleCPU::tick() 4112623SN/A{ 4122623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4132623SN/A 4142623SN/A for (int i = 0; i < width; ++i) { 4152623SN/A numCycles++; 4162623SN/A 4172626SN/A checkForInterrupts(); 4182626SN/A 4192662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4202623SN/A 4212623SN/A if (fault == NoFault) { 4222662Sstever@eecs.umich.edu ifetch_pkt->reinitFromRequest(); 4232662Sstever@eecs.umich.edu 4242662Sstever@eecs.umich.edu Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 4252623SN/A // ifetch_req is initialized to read the instruction directly 4262623SN/A // into the CPU object's inst field. 4272623SN/A 4282623SN/A dcache_access = false; // assume no dcache access 4292623SN/A preExecute(); 4302623SN/A fault = curStaticInst->execute(this, traceData); 4312623SN/A postExecute(); 4322623SN/A 4332623SN/A if (simulate_stalls) { 4342662Sstever@eecs.umich.edu Tick icache_stall = icache_latency - cycles(1); 4352623SN/A Tick dcache_stall = 4362662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 4372803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 4382803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 4392803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 4402803Ssaidi@eecs.umich.edu else 4412803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 4422623SN/A } 4432623SN/A 4442623SN/A } 4452623SN/A 4462623SN/A advancePC(fault); 4472623SN/A } 4482623SN/A 4492626SN/A if (_status != Idle) 4502626SN/A tickEvent.schedule(curTick + latency); 4512623SN/A} 4522623SN/A 4532623SN/A 4542623SN/A//////////////////////////////////////////////////////////////////////// 4552623SN/A// 4562623SN/A// AtomicSimpleCPU Simulation Object 4572623SN/A// 4582623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4592623SN/A 4602623SN/A Param<Counter> max_insts_any_thread; 4612623SN/A Param<Counter> max_insts_all_threads; 4622623SN/A Param<Counter> max_loads_any_thread; 4632623SN/A Param<Counter> max_loads_all_threads; 4642623SN/A SimObjectParam<MemObject *> mem; 4652623SN/A 4662623SN/A#if FULL_SYSTEM 4672623SN/A SimObjectParam<AlphaITB *> itb; 4682623SN/A SimObjectParam<AlphaDTB *> dtb; 4692623SN/A SimObjectParam<System *> system; 4702623SN/A Param<int> cpu_id; 4712623SN/A Param<Tick> profile; 4722623SN/A#else 4732623SN/A SimObjectParam<Process *> workload; 4742623SN/A#endif // FULL_SYSTEM 4752623SN/A 4762623SN/A Param<int> clock; 4772623SN/A 4782623SN/A Param<bool> defer_registration; 4792623SN/A Param<int> width; 4802623SN/A Param<bool> function_trace; 4812623SN/A Param<Tick> function_trace_start; 4822623SN/A Param<bool> simulate_stalls; 4832623SN/A 4842623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4852623SN/A 4862623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4872623SN/A 4882623SN/A INIT_PARAM(max_insts_any_thread, 4892623SN/A "terminate when any thread reaches this inst count"), 4902623SN/A INIT_PARAM(max_insts_all_threads, 4912623SN/A "terminate when all threads have reached this inst count"), 4922623SN/A INIT_PARAM(max_loads_any_thread, 4932623SN/A "terminate when any thread reaches this load count"), 4942623SN/A INIT_PARAM(max_loads_all_threads, 4952623SN/A "terminate when all threads have reached this load count"), 4962623SN/A INIT_PARAM(mem, "memory"), 4972623SN/A 4982623SN/A#if FULL_SYSTEM 4992623SN/A INIT_PARAM(itb, "Instruction TLB"), 5002623SN/A INIT_PARAM(dtb, "Data TLB"), 5012623SN/A INIT_PARAM(system, "system object"), 5022623SN/A INIT_PARAM(cpu_id, "processor ID"), 5032623SN/A INIT_PARAM(profile, ""), 5042623SN/A#else 5052623SN/A INIT_PARAM(workload, "processes to run"), 5062623SN/A#endif // FULL_SYSTEM 5072623SN/A 5082623SN/A INIT_PARAM(clock, "clock speed"), 5092623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5102623SN/A INIT_PARAM(width, "cpu width"), 5112623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5122623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5132623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5142623SN/A 5152623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5162623SN/A 5172623SN/A 5182623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU) 5192623SN/A{ 5202623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5212623SN/A params->name = getInstanceName(); 5222623SN/A params->numberOfThreads = 1; 5232623SN/A params->max_insts_any_thread = max_insts_any_thread; 5242623SN/A params->max_insts_all_threads = max_insts_all_threads; 5252623SN/A params->max_loads_any_thread = max_loads_any_thread; 5262623SN/A params->max_loads_all_threads = max_loads_all_threads; 5272623SN/A params->deferRegistration = defer_registration; 5282623SN/A params->clock = clock; 5292623SN/A params->functionTrace = function_trace; 5302623SN/A params->functionTraceStart = function_trace_start; 5312623SN/A params->width = width; 5322623SN/A params->simulate_stalls = simulate_stalls; 5332623SN/A params->mem = mem; 5342623SN/A 5352623SN/A#if FULL_SYSTEM 5362623SN/A params->itb = itb; 5372623SN/A params->dtb = dtb; 5382623SN/A params->system = system; 5392623SN/A params->cpu_id = cpu_id; 5402623SN/A params->profile = profile; 5412623SN/A#else 5422623SN/A params->process = workload; 5432623SN/A#endif 5442623SN/A 5452623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 5462623SN/A return cpu; 5472623SN/A} 5482623SN/A 5492623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 5502623SN/A 551