atomic.cc revision 2680
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
312623SN/A#include "arch/utility.hh"
322623SN/A#include "cpu/exetrace.hh"
332623SN/A#include "cpu/simple/atomic.hh"
342623SN/A#include "mem/packet_impl.hh"
352623SN/A#include "sim/builder.hh"
362623SN/A
372623SN/Ausing namespace std;
382623SN/Ausing namespace TheISA;
392623SN/A
402623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
412623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
422623SN/A{
432623SN/A}
442623SN/A
452623SN/A
462623SN/Avoid
472623SN/AAtomicSimpleCPU::TickEvent::process()
482623SN/A{
492623SN/A    cpu->tick();
502623SN/A}
512623SN/A
522623SN/Aconst char *
532623SN/AAtomicSimpleCPU::TickEvent::description()
542623SN/A{
552623SN/A    return "AtomicSimpleCPU tick event";
562623SN/A}
572623SN/A
582623SN/A
592623SN/Avoid
602623SN/AAtomicSimpleCPU::init()
612623SN/A{
622623SN/A    //Create Memory Ports (conect them up)
632623SN/A    Port *mem_dport = mem->getPort("");
642623SN/A    dcachePort.setPeer(mem_dport);
652623SN/A    mem_dport->setPeer(&dcachePort);
662623SN/A
672623SN/A    Port *mem_iport = mem->getPort("");
682623SN/A    icachePort.setPeer(mem_iport);
692623SN/A    mem_iport->setPeer(&icachePort);
702623SN/A
712623SN/A    BaseCPU::init();
722623SN/A#if FULL_SYSTEM
732680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
742680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
752623SN/A
762623SN/A        // initialize CPU, including PC
772680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
782623SN/A    }
792623SN/A#endif
802623SN/A}
812623SN/A
822623SN/Abool
832630SN/AAtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
842623SN/A{
852623SN/A    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
862623SN/A    return true;
872623SN/A}
882623SN/A
892623SN/ATick
902630SN/AAtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
912623SN/A{
922623SN/A    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
932623SN/A    return curTick;
942623SN/A}
952623SN/A
962623SN/Avoid
972630SN/AAtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
982623SN/A{
992623SN/A    panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
1002623SN/A}
1012623SN/A
1022623SN/Avoid
1032623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1042623SN/A{
1052626SN/A    if (status == RangeChange)
1062626SN/A        return;
1072626SN/A
1082623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1092623SN/A}
1102623SN/A
1112657Ssaidi@eecs.umich.eduvoid
1122623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1132623SN/A{
1142623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1152623SN/A}
1162623SN/A
1172623SN/A
1182623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1192623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1202623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1212640Sstever@eecs.umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
1222623SN/A{
1232623SN/A    _status = Idle;
1242623SN/A
1252663Sstever@eecs.umich.edu    // @todo fix me and get the real cpu id & thread number!!!
1262663Sstever@eecs.umich.edu    ifetch_req = new Request();
1272641Sstever@eecs.umich.edu    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
1282623SN/A    ifetch_pkt->dataStatic(&inst);
1292623SN/A
1302663Sstever@eecs.umich.edu    data_read_req = new Request();
1312641Sstever@eecs.umich.edu    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
1322641Sstever@eecs.umich.edu                               Packet::Broadcast);
1332623SN/A    data_read_pkt->dataStatic(&dataReg);
1342623SN/A
1352663Sstever@eecs.umich.edu    data_write_req = new Request();
1362641Sstever@eecs.umich.edu    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
1372641Sstever@eecs.umich.edu                                Packet::Broadcast);
1382623SN/A}
1392623SN/A
1402623SN/A
1412623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1422623SN/A{
1432623SN/A}
1442623SN/A
1452623SN/Avoid
1462623SN/AAtomicSimpleCPU::serialize(ostream &os)
1472623SN/A{
1482623SN/A    BaseSimpleCPU::serialize(os);
1492623SN/A    SERIALIZE_ENUM(_status);
1502623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1512623SN/A    tickEvent.serialize(os);
1522623SN/A}
1532623SN/A
1542623SN/Avoid
1552623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1562623SN/A{
1572623SN/A    BaseSimpleCPU::unserialize(cp, section);
1582623SN/A    UNSERIALIZE_ENUM(_status);
1592623SN/A    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1602623SN/A}
1612623SN/A
1622623SN/Avoid
1632623SN/AAtomicSimpleCPU::switchOut(Sampler *s)
1642623SN/A{
1652623SN/A    sampler = s;
1662623SN/A    if (status() == Running) {
1672623SN/A        _status = SwitchedOut;
1682623SN/A
1692623SN/A        tickEvent.squash();
1702623SN/A    }
1712623SN/A    sampler->signalSwitched();
1722623SN/A}
1732623SN/A
1742623SN/A
1752623SN/Avoid
1762623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
1772623SN/A{
1782623SN/A    BaseCPU::takeOverFrom(oldCPU);
1792623SN/A
1802623SN/A    assert(!tickEvent.scheduled());
1812623SN/A
1822680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
1832623SN/A    // running and schedule its tick event.
1842680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
1852680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
1862680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
1872623SN/A            _status = Running;
1882623SN/A            tickEvent.schedule(curTick);
1892623SN/A            break;
1902623SN/A        }
1912623SN/A    }
1922623SN/A}
1932623SN/A
1942623SN/A
1952623SN/Avoid
1962623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
1972623SN/A{
1982623SN/A    assert(thread_num == 0);
1992623SN/A    assert(cpuXC);
2002623SN/A
2012623SN/A    assert(_status == Idle);
2022623SN/A    assert(!tickEvent.scheduled());
2032623SN/A
2042623SN/A    notIdleFraction++;
2052623SN/A    tickEvent.schedule(curTick + cycles(delay));
2062623SN/A    _status = Running;
2072623SN/A}
2082623SN/A
2092623SN/A
2102623SN/Avoid
2112623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2122623SN/A{
2132623SN/A    assert(thread_num == 0);
2142623SN/A    assert(cpuXC);
2152623SN/A
2162623SN/A    assert(_status == Running);
2172626SN/A
2182626SN/A    // tick event may not be scheduled if this gets called from inside
2192626SN/A    // an instruction's execution, e.g. "quiesce"
2202626SN/A    if (tickEvent.scheduled())
2212626SN/A        tickEvent.deschedule();
2222623SN/A
2232623SN/A    notIdleFraction--;
2242623SN/A    _status = Idle;
2252623SN/A}
2262623SN/A
2272623SN/A
2282623SN/Atemplate <class T>
2292623SN/AFault
2302623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2312623SN/A{
2322663Sstever@eecs.umich.edu    data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
2332623SN/A
2342623SN/A    if (traceData) {
2352623SN/A        traceData->setAddr(addr);
2362623SN/A    }
2372623SN/A
2382623SN/A    // translate to physical address
2392623SN/A    Fault fault = cpuXC->translateDataReadReq(data_read_req);
2402623SN/A
2412623SN/A    // Now do the access.
2422623SN/A    if (fault == NoFault) {
2432641Sstever@eecs.umich.edu        data_read_pkt->reinitFromRequest();
2442623SN/A
2452662Sstever@eecs.umich.edu        dcache_latency = dcachePort.sendAtomic(data_read_pkt);
2462623SN/A        dcache_access = true;
2472623SN/A
2482641Sstever@eecs.umich.edu        assert(data_read_pkt->result == Packet::Success);
2492623SN/A        data = data_read_pkt->get<T>();
2502623SN/A
2512623SN/A    }
2522623SN/A
2532623SN/A    // This will need a new way to tell if it has a dcache attached.
2542623SN/A    if (data_read_req->getFlags() & UNCACHEABLE)
2552623SN/A        recordEvent("Uncached Read");
2562623SN/A
2572623SN/A    return fault;
2582623SN/A}
2592623SN/A
2602623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
2612623SN/A
2622623SN/Atemplate
2632623SN/AFault
2642623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
2652623SN/A
2662623SN/Atemplate
2672623SN/AFault
2682623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
2692623SN/A
2702623SN/Atemplate
2712623SN/AFault
2722623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
2732623SN/A
2742623SN/Atemplate
2752623SN/AFault
2762623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
2772623SN/A
2782623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
2792623SN/A
2802623SN/Atemplate<>
2812623SN/AFault
2822623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
2832623SN/A{
2842623SN/A    return read(addr, *(uint64_t*)&data, flags);
2852623SN/A}
2862623SN/A
2872623SN/Atemplate<>
2882623SN/AFault
2892623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
2902623SN/A{
2912623SN/A    return read(addr, *(uint32_t*)&data, flags);
2922623SN/A}
2932623SN/A
2942623SN/A
2952623SN/Atemplate<>
2962623SN/AFault
2972623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
2982623SN/A{
2992623SN/A    return read(addr, (uint32_t&)data, flags);
3002623SN/A}
3012623SN/A
3022623SN/A
3032623SN/Atemplate <class T>
3042623SN/AFault
3052623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
3062623SN/A{
3072663Sstever@eecs.umich.edu    data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
3082623SN/A
3092623SN/A    if (traceData) {
3102623SN/A        traceData->setAddr(addr);
3112623SN/A    }
3122623SN/A
3132623SN/A    // translate to physical address
3142623SN/A    Fault fault = cpuXC->translateDataWriteReq(data_write_req);
3152623SN/A
3162623SN/A    // Now do the access.
3172623SN/A    if (fault == NoFault) {
3182623SN/A        data = htog(data);
3192662Sstever@eecs.umich.edu        data_write_pkt->reinitFromRequest();
3202623SN/A        data_write_pkt->dataStatic(&data);
3212623SN/A
3222662Sstever@eecs.umich.edu        dcache_latency = dcachePort.sendAtomic(data_write_pkt);
3232623SN/A        dcache_access = true;
3242623SN/A
3252641Sstever@eecs.umich.edu        assert(data_write_pkt->result == Packet::Success);
3262631SN/A
3272631SN/A        if (res && data_write_req->getFlags() & LOCKED) {
3282631SN/A            *res = data_write_req->getScResult();
3292631SN/A        }
3302623SN/A    }
3312623SN/A
3322623SN/A    // This will need a new way to tell if it's hooked up to a cache or not.
3332623SN/A    if (data_write_req->getFlags() & UNCACHEABLE)
3342623SN/A        recordEvent("Uncached Write");
3352623SN/A
3362623SN/A    // If the write needs to have a fault on the access, consider calling
3372623SN/A    // changeStatus() and changing it to "bad addr write" or something.
3382623SN/A    return fault;
3392623SN/A}
3402623SN/A
3412623SN/A
3422623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3432623SN/Atemplate
3442623SN/AFault
3452623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
3462623SN/A                       unsigned flags, uint64_t *res);
3472623SN/A
3482623SN/Atemplate
3492623SN/AFault
3502623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
3512623SN/A                       unsigned flags, uint64_t *res);
3522623SN/A
3532623SN/Atemplate
3542623SN/AFault
3552623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
3562623SN/A                       unsigned flags, uint64_t *res);
3572623SN/A
3582623SN/Atemplate
3592623SN/AFault
3602623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
3612623SN/A                       unsigned flags, uint64_t *res);
3622623SN/A
3632623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
3642623SN/A
3652623SN/Atemplate<>
3662623SN/AFault
3672623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
3682623SN/A{
3692623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
3702623SN/A}
3712623SN/A
3722623SN/Atemplate<>
3732623SN/AFault
3742623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
3752623SN/A{
3762623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
3772623SN/A}
3782623SN/A
3792623SN/A
3802623SN/Atemplate<>
3812623SN/AFault
3822623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
3832623SN/A{
3842623SN/A    return write((uint32_t)data, addr, flags, res);
3852623SN/A}
3862623SN/A
3872623SN/A
3882623SN/Avoid
3892623SN/AAtomicSimpleCPU::tick()
3902623SN/A{
3912623SN/A    Tick latency = cycles(1); // instruction takes one cycle by default
3922623SN/A
3932623SN/A    for (int i = 0; i < width; ++i) {
3942623SN/A        numCycles++;
3952623SN/A
3962626SN/A        checkForInterrupts();
3972626SN/A
3982662Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(ifetch_req);
3992623SN/A
4002623SN/A        if (fault == NoFault) {
4012662Sstever@eecs.umich.edu            ifetch_pkt->reinitFromRequest();
4022662Sstever@eecs.umich.edu
4032662Sstever@eecs.umich.edu            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
4042623SN/A            // ifetch_req is initialized to read the instruction directly
4052623SN/A            // into the CPU object's inst field.
4062623SN/A
4072623SN/A            dcache_access = false; // assume no dcache access
4082623SN/A            preExecute();
4092623SN/A            fault = curStaticInst->execute(this, traceData);
4102623SN/A            postExecute();
4112623SN/A
4122623SN/A            if (simulate_stalls) {
4132623SN/A                // This calculation assumes that the icache and dcache
4142623SN/A                // access latencies are always a multiple of the CPU's
4152623SN/A                // cycle time.  If not, the next tick event may get
4162623SN/A                // scheduled at a non-integer multiple of the CPU
4172623SN/A                // cycle time.
4182662Sstever@eecs.umich.edu                Tick icache_stall = icache_latency - cycles(1);
4192623SN/A                Tick dcache_stall =
4202662Sstever@eecs.umich.edu                    dcache_access ? dcache_latency - cycles(1) : 0;
4212623SN/A                latency += icache_stall + dcache_stall;
4222623SN/A            }
4232623SN/A
4242623SN/A        }
4252623SN/A
4262623SN/A        advancePC(fault);
4272623SN/A    }
4282623SN/A
4292626SN/A    if (_status != Idle)
4302626SN/A        tickEvent.schedule(curTick + latency);
4312623SN/A}
4322623SN/A
4332623SN/A
4342623SN/A////////////////////////////////////////////////////////////////////////
4352623SN/A//
4362623SN/A//  AtomicSimpleCPU Simulation Object
4372623SN/A//
4382623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
4392623SN/A
4402623SN/A    Param<Counter> max_insts_any_thread;
4412623SN/A    Param<Counter> max_insts_all_threads;
4422623SN/A    Param<Counter> max_loads_any_thread;
4432623SN/A    Param<Counter> max_loads_all_threads;
4442623SN/A    SimObjectParam<MemObject *> mem;
4452623SN/A
4462623SN/A#if FULL_SYSTEM
4472623SN/A    SimObjectParam<AlphaITB *> itb;
4482623SN/A    SimObjectParam<AlphaDTB *> dtb;
4492623SN/A    SimObjectParam<System *> system;
4502623SN/A    Param<int> cpu_id;
4512623SN/A    Param<Tick> profile;
4522623SN/A#else
4532623SN/A    SimObjectParam<Process *> workload;
4542623SN/A#endif // FULL_SYSTEM
4552623SN/A
4562623SN/A    Param<int> clock;
4572623SN/A
4582623SN/A    Param<bool> defer_registration;
4592623SN/A    Param<int> width;
4602623SN/A    Param<bool> function_trace;
4612623SN/A    Param<Tick> function_trace_start;
4622623SN/A    Param<bool> simulate_stalls;
4632623SN/A
4642623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
4652623SN/A
4662623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
4672623SN/A
4682623SN/A    INIT_PARAM(max_insts_any_thread,
4692623SN/A               "terminate when any thread reaches this inst count"),
4702623SN/A    INIT_PARAM(max_insts_all_threads,
4712623SN/A               "terminate when all threads have reached this inst count"),
4722623SN/A    INIT_PARAM(max_loads_any_thread,
4732623SN/A               "terminate when any thread reaches this load count"),
4742623SN/A    INIT_PARAM(max_loads_all_threads,
4752623SN/A               "terminate when all threads have reached this load count"),
4762623SN/A    INIT_PARAM(mem, "memory"),
4772623SN/A
4782623SN/A#if FULL_SYSTEM
4792623SN/A    INIT_PARAM(itb, "Instruction TLB"),
4802623SN/A    INIT_PARAM(dtb, "Data TLB"),
4812623SN/A    INIT_PARAM(system, "system object"),
4822623SN/A    INIT_PARAM(cpu_id, "processor ID"),
4832623SN/A    INIT_PARAM(profile, ""),
4842623SN/A#else
4852623SN/A    INIT_PARAM(workload, "processes to run"),
4862623SN/A#endif // FULL_SYSTEM
4872623SN/A
4882623SN/A    INIT_PARAM(clock, "clock speed"),
4892623SN/A    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
4902623SN/A    INIT_PARAM(width, "cpu width"),
4912623SN/A    INIT_PARAM(function_trace, "Enable function trace"),
4922623SN/A    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
4932623SN/A    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
4942623SN/A
4952623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
4962623SN/A
4972623SN/A
4982623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU)
4992623SN/A{
5002623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
5012623SN/A    params->name = getInstanceName();
5022623SN/A    params->numberOfThreads = 1;
5032623SN/A    params->max_insts_any_thread = max_insts_any_thread;
5042623SN/A    params->max_insts_all_threads = max_insts_all_threads;
5052623SN/A    params->max_loads_any_thread = max_loads_any_thread;
5062623SN/A    params->max_loads_all_threads = max_loads_all_threads;
5072623SN/A    params->deferRegistration = defer_registration;
5082623SN/A    params->clock = clock;
5092623SN/A    params->functionTrace = function_trace;
5102623SN/A    params->functionTraceStart = function_trace_start;
5112623SN/A    params->width = width;
5122623SN/A    params->simulate_stalls = simulate_stalls;
5132623SN/A    params->mem = mem;
5142623SN/A
5152623SN/A#if FULL_SYSTEM
5162623SN/A    params->itb = itb;
5172623SN/A    params->dtb = dtb;
5182623SN/A    params->system = system;
5192623SN/A    params->cpu_id = cpu_id;
5202623SN/A    params->profile = profile;
5212623SN/A#else
5222623SN/A    params->process = workload;
5232623SN/A#endif
5242623SN/A
5252623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
5262623SN/A    return cpu;
5272623SN/A}
5282623SN/A
5292623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
5302623SN/A
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