atomic.cc revision 12710
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2012-2013,2015,2017 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/atomic.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 499647Sdam.sunwoo@arm.com#include "base/output.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 6011793Sbrandon.potter@amd.com#include "sim/full_system.hh" 612901Ssaidi@eecs.umich.edu#include "sim/system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/Avoid 672623SN/AAtomicSimpleCPU::init() 682623SN/A{ 6911147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 708921Sandreas.hansson@arm.com 7111148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 7211435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 7311435Smitch.hayenga@arm.com data_read_req.setContext(cid); 7411435Smitch.hayenga@arm.com data_write_req.setContext(cid); 752623SN/A} 762623SN/A 775529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 7812127Sspwilson2@wisc.edu : BaseSimpleCPU(p), 7912127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 8012127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 8112127Sspwilson2@wisc.edu width(p->width), locked(false), 825487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 835487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 849095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 859095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 8610537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 8710537Sandreas.hansson@arm.com ppCommit(nullptr) 882623SN/A{ 892623SN/A _status = Idle; 902623SN/A} 912623SN/A 922623SN/A 932623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 942623SN/A{ 956775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 966775SBrad.Beckmann@amd.com deschedule(tickEvent); 976775SBrad.Beckmann@amd.com } 982623SN/A} 992623SN/A 10010913Sandreas.sandberg@arm.comDrainState 10110913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1022623SN/A{ 10312276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 10412276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 10512276Sanouk.vanlaer@arm.com 1069448SAndreas.Sandberg@ARM.com if (switchedOut()) 10710913Sandreas.sandberg@arm.com return DrainState::Drained; 1082623SN/A 1099443SAndreas.Sandberg@ARM.com if (!isDrained()) { 11011147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 11110913Sandreas.sandberg@arm.com return DrainState::Draining; 1129443SAndreas.Sandberg@ARM.com } else { 1139443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1149443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1152915Sktlim@umich.edu 11611147Smitch.hayenga@arm.com activeThreads.clear(); 1179443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 11810913Sandreas.sandberg@arm.com return DrainState::Drained; 1199443SAndreas.Sandberg@ARM.com } 1209342SAndreas.Sandberg@arm.com} 1219342SAndreas.Sandberg@arm.com 1222915Sktlim@umich.eduvoid 12311148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 12411148Smitch.hayenga@arm.com{ 12511148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 12611148Smitch.hayenga@arm.com pkt->cmdString()); 12711148Smitch.hayenga@arm.com 12811148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 12911148Smitch.hayenga@arm.com if (tid != sender) { 13011321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 13111151Smitch.hayenga@arm.com wakeup(tid); 13211148Smitch.hayenga@arm.com } 13311148Smitch.hayenga@arm.com 13411148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 13511148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 13611148Smitch.hayenga@arm.com } 13711148Smitch.hayenga@arm.com } 13811148Smitch.hayenga@arm.com} 13911148Smitch.hayenga@arm.com 14011148Smitch.hayenga@arm.comvoid 1419342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1422915Sktlim@umich.edu{ 1439448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1449448SAndreas.Sandberg@ARM.com if (switchedOut()) 1455220Ssaidi@eecs.umich.edu return; 1465220Ssaidi@eecs.umich.edu 1474940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1489523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1493324Shsul@eecs.umich.edu 1509448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1519448SAndreas.Sandberg@ARM.com 15211147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 15311147Smitch.hayenga@arm.com 15411147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15511147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 15611147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 15711147Smitch.hayenga@arm.com activeThreads.push_back(tid); 15811147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 15911147Smitch.hayenga@arm.com 16011147Smitch.hayenga@arm.com // Tick if any threads active 16111147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 16211147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 16311147Smitch.hayenga@arm.com } 16411147Smitch.hayenga@arm.com } else { 16511147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 16611147Smitch.hayenga@arm.com } 1679448SAndreas.Sandberg@ARM.com } 16812276Sanouk.vanlaer@arm.com 16912276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 17012276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 1712623SN/A} 1722623SN/A 1739443SAndreas.Sandberg@ARM.combool 1749443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1759443SAndreas.Sandberg@ARM.com{ 17610913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1779443SAndreas.Sandberg@ARM.com return false; 1789443SAndreas.Sandberg@ARM.com 17911147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1809443SAndreas.Sandberg@ARM.com if (!isDrained()) 1819443SAndreas.Sandberg@ARM.com return false; 1829443SAndreas.Sandberg@ARM.com 1839443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 18410913Sandreas.sandberg@arm.com signalDrainDone(); 1859443SAndreas.Sandberg@ARM.com 1869443SAndreas.Sandberg@ARM.com return true; 1879443SAndreas.Sandberg@ARM.com} 1889443SAndreas.Sandberg@ARM.com 1899443SAndreas.Sandberg@ARM.com 1902623SN/Avoid 1912798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1922623SN/A{ 1939429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1949429SAndreas.Sandberg@ARM.com 1959443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1969342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1979443SAndreas.Sandberg@ARM.com assert(isDrained()); 1982623SN/A} 1992623SN/A 2002623SN/A 2012623SN/Avoid 2022623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2032623SN/A{ 2049429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2052623SN/A 2069443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2072623SN/A assert(!tickEvent.scheduled()); 2082623SN/A} 2092623SN/A 2109523SAndreas.Sandberg@ARM.comvoid 2119523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2129523SAndreas.Sandberg@ARM.com{ 2139524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2149523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2159523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2169523SAndreas.Sandberg@ARM.com } 2179523SAndreas.Sandberg@ARM.com} 2182623SN/A 2192623SN/Avoid 22010407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2212623SN/A{ 22210407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2234940Snate@binkert.org 22411147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2252623SN/A 22611147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 22711147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 22811147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 22910464SAndreas.Sandberg@ARM.com numCycles += delta; 2303686Sktlim@umich.edu 23111147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 23211147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 23311147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 23411147Smitch.hayenga@arm.com } 2359342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 23611147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 23711147Smitch.hayenga@arm.com == activeThreads.end()) { 23811147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 23911147Smitch.hayenga@arm.com } 24011526Sdavid.guillen@arm.com 24111526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2422623SN/A} 2432623SN/A 2442623SN/A 2452623SN/Avoid 2468737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2472623SN/A{ 2484940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2494940Snate@binkert.org 25011147Smitch.hayenga@arm.com assert(thread_num < numThreads); 25111147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2522623SN/A 2536043Sgblack@eecs.umich.edu if (_status == Idle) 2546043Sgblack@eecs.umich.edu return; 2556043Sgblack@eecs.umich.edu 2569342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2572626SN/A 25811147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2592623SN/A 26011147Smitch.hayenga@arm.com if (activeThreads.empty()) { 26111147Smitch.hayenga@arm.com _status = Idle; 26211147Smitch.hayenga@arm.com 26311147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 26411147Smitch.hayenga@arm.com deschedule(tickEvent); 26511147Smitch.hayenga@arm.com } 26611147Smitch.hayenga@arm.com } 26711147Smitch.hayenga@arm.com 26811526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2692623SN/A} 2702623SN/A 2712623SN/A 27210030SAli.Saidi@ARM.comTick 27310030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27410030SAli.Saidi@ARM.com{ 27510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27610030SAli.Saidi@ARM.com pkt->cmdString()); 27710030SAli.Saidi@ARM.com 27810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 27910529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 28011148Smitch.hayenga@arm.com 28111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 28211148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 28311151Smitch.hayenga@arm.com cpu->wakeup(tid); 28411148Smitch.hayenga@arm.com } 28510529Smorr@cs.wisc.edu } 28610529Smorr@cs.wisc.edu 28710030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 28811356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 28911356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 29011356Skrinat01@arm.com // the processor accordingly 29111356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 29210030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 29310030SAli.Saidi@ARM.com pkt->getAddr()); 29411147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 29511147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 29611147Smitch.hayenga@arm.com } 29710030SAli.Saidi@ARM.com } 29810030SAli.Saidi@ARM.com 29910030SAli.Saidi@ARM.com return 0; 30010030SAli.Saidi@ARM.com} 30110030SAli.Saidi@ARM.com 30210030SAli.Saidi@ARM.comvoid 30310030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 30410030SAli.Saidi@ARM.com{ 30510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 30610030SAli.Saidi@ARM.com pkt->cmdString()); 30710030SAli.Saidi@ARM.com 30810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 30910529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 31011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 31111321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 31211151Smitch.hayenga@arm.com cpu->wakeup(tid); 31311148Smitch.hayenga@arm.com } 31410529Smorr@cs.wisc.edu } 31510529Smorr@cs.wisc.edu 31610030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 31710030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 31810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 31910030SAli.Saidi@ARM.com pkt->getAddr()); 32011147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 32111147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 32211147Smitch.hayenga@arm.com } 32310030SAli.Saidi@ARM.com } 32410030SAli.Saidi@ARM.com} 32510030SAli.Saidi@ARM.com 3262623SN/AFault 32711608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 32811608Snikos.nikoleris@arm.com Request::Flags flags) 3292623SN/A{ 33011147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 33111147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 33211147Smitch.hayenga@arm.com 3333169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3344870Sstever@eecs.umich.edu Request *req = &data_read_req; 3352623SN/A 33610665SAli.Saidi@ARM.com if (traceData) 33710665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3382623SN/A 3394999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3407520Sgblack@eecs.umich.edu int fullSize = size; 3412623SN/A 3424999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3434999Sgblack@eecs.umich.edu //across a cache line boundary. 3449814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3454999Sgblack@eecs.umich.edu 3467520Sgblack@eecs.umich.edu if (secondAddr > addr) 3477520Sgblack@eecs.umich.edu size = secondAddr - addr; 3484999Sgblack@eecs.umich.edu 3494999Sgblack@eecs.umich.edu dcache_latency = 0; 3504999Sgblack@eecs.umich.edu 35110024Sdam.sunwoo@arm.com req->taskId(taskId()); 3527520Sgblack@eecs.umich.edu while (1) { 3538832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3544999Sgblack@eecs.umich.edu 3554999Sgblack@eecs.umich.edu // translate to physical address 35611147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 35711147Smitch.hayenga@arm.com BaseTLB::Read); 3584999Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu // Now do the access. 3606623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 36110739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3627520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3634999Sgblack@eecs.umich.edu 3648105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3654999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3664999Sgblack@eecs.umich.edu else { 3678931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3688931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3694999Sgblack@eecs.umich.edu else 3704999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3714999Sgblack@eecs.umich.edu } 3724999Sgblack@eecs.umich.edu dcache_access = true; 3735012Sgblack@eecs.umich.edu 3744999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3754999Sgblack@eecs.umich.edu 3766102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3774999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3784999Sgblack@eecs.umich.edu } 3794968Sacolyte@umich.edu } 3804986Ssaidi@eecs.umich.edu 3814999Sgblack@eecs.umich.edu //If there's a fault, return it 3826739Sgblack@eecs.umich.edu if (fault != NoFault) { 3836739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3846739Sgblack@eecs.umich.edu return NoFault; 3856739Sgblack@eecs.umich.edu } else { 3866739Sgblack@eecs.umich.edu return fault; 3876739Sgblack@eecs.umich.edu } 3886739Sgblack@eecs.umich.edu } 3896739Sgblack@eecs.umich.edu 3904999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3914999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3924999Sgblack@eecs.umich.edu { 39310760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3946078Sgblack@eecs.umich.edu assert(!locked); 3956078Sgblack@eecs.umich.edu locked = true; 3966078Sgblack@eecs.umich.edu } 39711147Smitch.hayenga@arm.com 3984999Sgblack@eecs.umich.edu return fault; 3994968Sacolyte@umich.edu } 4003170Sstever@eecs.umich.edu 4014999Sgblack@eecs.umich.edu /* 4024999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4034999Sgblack@eecs.umich.edu */ 4044999Sgblack@eecs.umich.edu 4054999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4067520Sgblack@eecs.umich.edu data += size; 4074999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4087520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4094999Sgblack@eecs.umich.edu //And access the right address. 4104999Sgblack@eecs.umich.edu addr = secondAddr; 4112623SN/A } 4122623SN/A} 4132623SN/A 41411303Ssteve.reinhardt@amd.comFault 41511608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 41611608Snikos.nikoleris@arm.com Request::Flags flags) 41711303Ssteve.reinhardt@amd.com{ 41811303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 41911303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 42011303Ssteve.reinhardt@amd.com} 4217520Sgblack@eecs.umich.edu 4222623SN/AFault 42311608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 42411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4252623SN/A{ 42611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 42711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 42810031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 42910031SAli.Saidi@ARM.com 43010031SAli.Saidi@ARM.com if (data == NULL) { 43110031SAli.Saidi@ARM.com assert(size <= 64); 43212355Snikos.nikoleris@arm.com assert(flags & Request::STORE_NO_DATA); 43310031SAli.Saidi@ARM.com // This must be a cache block cleaning request 43410031SAli.Saidi@ARM.com data = zero_array; 43510031SAli.Saidi@ARM.com } 43610031SAli.Saidi@ARM.com 4373169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4384870Sstever@eecs.umich.edu Request *req = &data_write_req; 4392623SN/A 44010665SAli.Saidi@ARM.com if (traceData) 44110665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4422623SN/A 4434999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4447520Sgblack@eecs.umich.edu int fullSize = size; 4452623SN/A 4464999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4474999Sgblack@eecs.umich.edu //across a cache line boundary. 4489814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4494999Sgblack@eecs.umich.edu 45011321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4517520Sgblack@eecs.umich.edu size = secondAddr - addr; 4524999Sgblack@eecs.umich.edu 4534999Sgblack@eecs.umich.edu dcache_latency = 0; 4544999Sgblack@eecs.umich.edu 45510024Sdam.sunwoo@arm.com req->taskId(taskId()); 45611321Ssteve.reinhardt@amd.com while (1) { 4578832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4584999Sgblack@eecs.umich.edu 4594999Sgblack@eecs.umich.edu // translate to physical address 46011147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4614999Sgblack@eecs.umich.edu 4624999Sgblack@eecs.umich.edu // Now do the access. 4634999Sgblack@eecs.umich.edu if (fault == NoFault) { 4644999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4654999Sgblack@eecs.umich.edu 4666102Sgblack@eecs.umich.edu if (req->isLLSC()) { 46710030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4684999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4694999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4704999Sgblack@eecs.umich.edu assert(res); 4714999Sgblack@eecs.umich.edu req->setExtraData(*res); 4724999Sgblack@eecs.umich.edu } 4734999Sgblack@eecs.umich.edu } 4744999Sgblack@eecs.umich.edu 4756623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 47612355Snikos.nikoleris@arm.com Packet pkt(req, Packet::makeWriteCmd(req)); 4777520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4784999Sgblack@eecs.umich.edu 4798105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4804999Sgblack@eecs.umich.edu dcache_latency += 4814999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4824999Sgblack@eecs.umich.edu } else { 4838931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4848931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4854999Sgblack@eecs.umich.edu else 4864999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 48711148Smitch.hayenga@arm.com 48811148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 48911148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 4904999Sgblack@eecs.umich.edu } 4914999Sgblack@eecs.umich.edu dcache_access = true; 4924999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4934999Sgblack@eecs.umich.edu 4944999Sgblack@eecs.umich.edu if (req->isSwap()) { 4954999Sgblack@eecs.umich.edu assert(res); 49610563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 4974999Sgblack@eecs.umich.edu } 4984999Sgblack@eecs.umich.edu } 4994999Sgblack@eecs.umich.edu 5004999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5014999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5024878Sstever@eecs.umich.edu } 5034040Ssaidi@eecs.umich.edu } 5044040Ssaidi@eecs.umich.edu 5054999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5064999Sgblack@eecs.umich.edu //stop now. 5074999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5084999Sgblack@eecs.umich.edu { 50910760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5106078Sgblack@eecs.umich.edu assert(locked); 5116078Sgblack@eecs.umich.edu locked = false; 5126078Sgblack@eecs.umich.edu } 51311147Smitch.hayenga@arm.com 51411147Smitch.hayenga@arm.com 5156739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5166739Sgblack@eecs.umich.edu return NoFault; 5176739Sgblack@eecs.umich.edu } else { 5186739Sgblack@eecs.umich.edu return fault; 5196739Sgblack@eecs.umich.edu } 5203170Sstever@eecs.umich.edu } 5213170Sstever@eecs.umich.edu 5224999Sgblack@eecs.umich.edu /* 5234999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5244999Sgblack@eecs.umich.edu */ 5254999Sgblack@eecs.umich.edu 5264999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5277520Sgblack@eecs.umich.edu data += size; 5284999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5297520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5304999Sgblack@eecs.umich.edu //And access the right address. 5314999Sgblack@eecs.umich.edu addr = secondAddr; 5322623SN/A } 5332623SN/A} 5342623SN/A 5352623SN/A 5362623SN/Avoid 5372623SN/AAtomicSimpleCPU::tick() 5382623SN/A{ 5394940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5404940Snate@binkert.org 54111147Smitch.hayenga@arm.com // Change thread if multi-threaded 54211147Smitch.hayenga@arm.com swapActiveThread(); 54311147Smitch.hayenga@arm.com 54411147Smitch.hayenga@arm.com // Set memroy request ids to current thread 54511147Smitch.hayenga@arm.com if (numThreads > 1) { 54611148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 54711148Smitch.hayenga@arm.com 54811435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 54911435Smitch.hayenga@arm.com data_read_req.setContext(cid); 55011435Smitch.hayenga@arm.com data_write_req.setContext(cid); 55111147Smitch.hayenga@arm.com } 55211147Smitch.hayenga@arm.com 55311147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 55411147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 55511147Smitch.hayenga@arm.com 5565487Snate@binkert.org Tick latency = 0; 5572623SN/A 5586078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5592623SN/A numCycles++; 56012284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5612623SN/A 56210596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5633387Sgblack@eecs.umich.edu checkForInterrupts(); 56410596Sgabeblack@google.com checkPcEventQueue(); 56510596Sgabeblack@google.com } 5662626SN/A 5678143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5689443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5699443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5708143SAli.Saidi@ARM.com return; 5719443SAndreas.Sandberg@ARM.com } 5725348Ssaidi@eecs.umich.edu 5735669Sgblack@eecs.umich.edu Fault fault = NoFault; 5745669Sgblack@eecs.umich.edu 5757720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5767720Sgblack@eecs.umich.edu 5777720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5787720Sgblack@eecs.umich.edu !curMacroStaticInst; 5797720Sgblack@eecs.umich.edu if (needToFetch) { 58010024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5815894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 58211147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5836023Snate@binkert.org BaseTLB::Execute); 5845894Sgblack@eecs.umich.edu } 5852623SN/A 5862623SN/A if (fault == NoFault) { 5874182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5884182Sgblack@eecs.umich.edu bool icache_access = false; 5894182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5902662Sstever@eecs.umich.edu 5917720Sgblack@eecs.umich.edu if (needToFetch) { 5929023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5935694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5945694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5955694Sgblack@eecs.umich.edu // this code should be uncommented. 5965669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 59711321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 5985669Sgblack@eecs.umich.edu //{ 5995669Sgblack@eecs.umich.edu icache_access = true; 6008949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6015669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6022623SN/A 6038931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6048931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6055669Sgblack@eecs.umich.edu else 6065669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6074968Sacolyte@umich.edu 6085669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6094968Sacolyte@umich.edu 6105669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6115669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6125669Sgblack@eecs.umich.edu //} 6135669Sgblack@eecs.umich.edu } 6144182Sgblack@eecs.umich.edu 6152623SN/A preExecute(); 6163814Ssaidi@eecs.umich.edu 61711877Sbrandon.potter@amd.com Tick stall_ticks = 0; 6185001Sgblack@eecs.umich.edu if (curStaticInst) { 61911147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6204998Sgblack@eecs.umich.edu 6214998Sgblack@eecs.umich.edu // keep an instruction count 62210381Sdam.sunwoo@arm.com if (fault == NoFault) { 6234998Sgblack@eecs.umich.edu countInst(); 62410651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 62510381Sdam.sunwoo@arm.com } 6267655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6275001Sgblack@eecs.umich.edu delete traceData; 6285001Sgblack@eecs.umich.edu traceData = NULL; 6295001Sgblack@eecs.umich.edu } 6304998Sgblack@eecs.umich.edu 63112710Sgiacomo.travaglini@arm.com if (fault != NoFault && 63212710Sgiacomo.travaglini@arm.com dynamic_pointer_cast<SyscallRetryFault>(fault)) { 63311877Sbrandon.potter@amd.com // Retry execution of system calls after a delay. 63411877Sbrandon.potter@amd.com // Prevents immediate re-execution since conditions which 63511877Sbrandon.potter@amd.com // caused the retry are unlikely to change every tick. 63611877Sbrandon.potter@amd.com stall_ticks += clockEdge(syscallRetryLatency) - curTick(); 63711877Sbrandon.potter@amd.com } 63811877Sbrandon.potter@amd.com 6394182Sgblack@eecs.umich.edu postExecute(); 6404182Sgblack@eecs.umich.edu } 6412623SN/A 6423814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6434539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6444539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6453814Ssaidi@eecs.umich.edu instCnt++; 6463814Ssaidi@eecs.umich.edu 6475487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6485487Snate@binkert.org stall_ticks += icache_latency; 6495487Snate@binkert.org 6505487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6515487Snate@binkert.org stall_ticks += dcache_latency; 6525487Snate@binkert.org 6535487Snate@binkert.org if (stall_ticks) { 6549180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6559180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6569180Sandreas.hansson@arm.com // period 6579180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6589180Sandreas.hansson@arm.com clockPeriod(); 6592623SN/A } 6602623SN/A 6612623SN/A } 66211321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6634182Sgblack@eecs.umich.edu advancePC(fault); 6642623SN/A } 6652623SN/A 6669443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6679443SAndreas.Sandberg@ARM.com return; 6689443SAndreas.Sandberg@ARM.com 6695487Snate@binkert.org // instruction takes at least one cycle 6709179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6719179Sandreas.hansson@arm.com latency = clockPeriod(); 6725487Snate@binkert.org 6732626SN/A if (_status != Idle) 67411147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6752623SN/A} 6762623SN/A 67710381Sdam.sunwoo@arm.comvoid 67810381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 67910381Sdam.sunwoo@arm.com{ 68010464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68110464SAndreas.Sandberg@ARM.com 68210381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68310381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68410381Sdam.sunwoo@arm.com} 6852623SN/A 6865315Sstever@gmail.comvoid 6875315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6885315Sstever@gmail.com{ 6895315Sstever@gmail.com dcachePort.printAddr(a); 6905315Sstever@gmail.com} 6915315Sstever@gmail.com 6922623SN/A//////////////////////////////////////////////////////////////////////// 6932623SN/A// 6942623SN/A// AtomicSimpleCPU Simulation Object 6952623SN/A// 6964762Snate@binkert.orgAtomicSimpleCPU * 6974762Snate@binkert.orgAtomicSimpleCPUParams::create() 6982623SN/A{ 6995529Snate@binkert.org return new AtomicSimpleCPU(this); 7002623SN/A} 701