atomic.cc revision 12284
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2012-2013,2015,2017 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/atomic.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 494040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 509647Sdam.sunwoo@arm.com#include "base/output.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 522623SN/A#include "cpu/exetrace.hh" 539443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 548232Snate@binkert.org#include "debug/ExecFaulting.hh" 558232Snate@binkert.org#include "debug/SimpleCPU.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 573348Sbinkertn@umich.edu#include "mem/packet_access.hh" 588926Sandreas.hansson@arm.com#include "mem/physical.hh" 594762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 607678Sgblack@eecs.umich.edu#include "sim/faults.hh" 6111793Sbrandon.potter@amd.com#include "sim/full_system.hh" 622901Ssaidi@eecs.umich.edu#include "sim/system.hh" 632623SN/A 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/AAtomicSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 718921Sandreas.hansson@arm.com 7211148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 7311435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 7411435Smitch.hayenga@arm.com data_read_req.setContext(cid); 7511435Smitch.hayenga@arm.com data_write_req.setContext(cid); 762623SN/A} 772623SN/A 785529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 7912127Sspwilson2@wisc.edu : BaseSimpleCPU(p), 8012127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 8112127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 8212127Sspwilson2@wisc.edu width(p->width), locked(false), 835487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 845487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 859095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 869095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 8710537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 8810537Sandreas.hansson@arm.com ppCommit(nullptr) 892623SN/A{ 902623SN/A _status = Idle; 912623SN/A} 922623SN/A 932623SN/A 942623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 952623SN/A{ 966775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 976775SBrad.Beckmann@amd.com deschedule(tickEvent); 986775SBrad.Beckmann@amd.com } 992623SN/A} 1002623SN/A 10110913Sandreas.sandberg@arm.comDrainState 10210913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1032623SN/A{ 10412276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 10512276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 10612276Sanouk.vanlaer@arm.com 1079448SAndreas.Sandberg@ARM.com if (switchedOut()) 10810913Sandreas.sandberg@arm.com return DrainState::Drained; 1092623SN/A 1109443SAndreas.Sandberg@ARM.com if (!isDrained()) { 11111147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 11210913Sandreas.sandberg@arm.com return DrainState::Draining; 1139443SAndreas.Sandberg@ARM.com } else { 1149443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1159443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1162915Sktlim@umich.edu 11711147Smitch.hayenga@arm.com activeThreads.clear(); 1189443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 11910913Sandreas.sandberg@arm.com return DrainState::Drained; 1209443SAndreas.Sandberg@ARM.com } 1219342SAndreas.Sandberg@arm.com} 1229342SAndreas.Sandberg@arm.com 1232915Sktlim@umich.eduvoid 12411148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 12511148Smitch.hayenga@arm.com{ 12611148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 12711148Smitch.hayenga@arm.com pkt->cmdString()); 12811148Smitch.hayenga@arm.com 12911148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13011148Smitch.hayenga@arm.com if (tid != sender) { 13111321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 13211151Smitch.hayenga@arm.com wakeup(tid); 13311148Smitch.hayenga@arm.com } 13411148Smitch.hayenga@arm.com 13511148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 13611148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 13711148Smitch.hayenga@arm.com } 13811148Smitch.hayenga@arm.com } 13911148Smitch.hayenga@arm.com} 14011148Smitch.hayenga@arm.com 14111148Smitch.hayenga@arm.comvoid 1429342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1432915Sktlim@umich.edu{ 1449448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1459448SAndreas.Sandberg@ARM.com if (switchedOut()) 1465220Ssaidi@eecs.umich.edu return; 1475220Ssaidi@eecs.umich.edu 1484940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1499523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1503324Shsul@eecs.umich.edu 1519448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1529448SAndreas.Sandberg@ARM.com 15311147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 15411147Smitch.hayenga@arm.com 15511147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15611147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 15711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 15811147Smitch.hayenga@arm.com activeThreads.push_back(tid); 15911147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 16011147Smitch.hayenga@arm.com 16111147Smitch.hayenga@arm.com // Tick if any threads active 16211147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 16311147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 16411147Smitch.hayenga@arm.com } 16511147Smitch.hayenga@arm.com } else { 16611147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 16711147Smitch.hayenga@arm.com } 1689448SAndreas.Sandberg@ARM.com } 16912276Sanouk.vanlaer@arm.com 17012276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 17112276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 1722623SN/A} 1732623SN/A 1749443SAndreas.Sandberg@ARM.combool 1759443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1769443SAndreas.Sandberg@ARM.com{ 17710913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1789443SAndreas.Sandberg@ARM.com return false; 1799443SAndreas.Sandberg@ARM.com 18011147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1819443SAndreas.Sandberg@ARM.com if (!isDrained()) 1829443SAndreas.Sandberg@ARM.com return false; 1839443SAndreas.Sandberg@ARM.com 1849443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 18510913Sandreas.sandberg@arm.com signalDrainDone(); 1869443SAndreas.Sandberg@ARM.com 1879443SAndreas.Sandberg@ARM.com return true; 1889443SAndreas.Sandberg@ARM.com} 1899443SAndreas.Sandberg@ARM.com 1909443SAndreas.Sandberg@ARM.com 1912623SN/Avoid 1922798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1932623SN/A{ 1949429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1959429SAndreas.Sandberg@ARM.com 1969443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1979342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1989443SAndreas.Sandberg@ARM.com assert(isDrained()); 1992623SN/A} 2002623SN/A 2012623SN/A 2022623SN/Avoid 2032623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2042623SN/A{ 2059429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2062623SN/A 2079443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2082623SN/A assert(!tickEvent.scheduled()); 2092623SN/A} 2102623SN/A 2119523SAndreas.Sandberg@ARM.comvoid 2129523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2139523SAndreas.Sandberg@ARM.com{ 2149524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2159523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2169523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2179523SAndreas.Sandberg@ARM.com } 2189523SAndreas.Sandberg@ARM.com} 2192623SN/A 2202623SN/Avoid 22110407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2222623SN/A{ 22310407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2244940Snate@binkert.org 22511147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2262623SN/A 22711147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 22811147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 22911147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 23010464SAndreas.Sandberg@ARM.com numCycles += delta; 2313686Sktlim@umich.edu 23211147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 23311147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 23411147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 23511147Smitch.hayenga@arm.com } 2369342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 23711147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 23811147Smitch.hayenga@arm.com == activeThreads.end()) { 23911147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 24011147Smitch.hayenga@arm.com } 24111526Sdavid.guillen@arm.com 24211526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Avoid 2478737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2482623SN/A{ 2494940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2504940Snate@binkert.org 25111147Smitch.hayenga@arm.com assert(thread_num < numThreads); 25211147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2532623SN/A 2546043Sgblack@eecs.umich.edu if (_status == Idle) 2556043Sgblack@eecs.umich.edu return; 2566043Sgblack@eecs.umich.edu 2579342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2582626SN/A 25911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2602623SN/A 26111147Smitch.hayenga@arm.com if (activeThreads.empty()) { 26211147Smitch.hayenga@arm.com _status = Idle; 26311147Smitch.hayenga@arm.com 26411147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 26511147Smitch.hayenga@arm.com deschedule(tickEvent); 26611147Smitch.hayenga@arm.com } 26711147Smitch.hayenga@arm.com } 26811147Smitch.hayenga@arm.com 26911526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2702623SN/A} 2712623SN/A 2722623SN/A 27310030SAli.Saidi@ARM.comTick 27410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27510030SAli.Saidi@ARM.com{ 27610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27710030SAli.Saidi@ARM.com pkt->cmdString()); 27810030SAli.Saidi@ARM.com 27910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 28010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 28111148Smitch.hayenga@arm.com 28211148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 28311148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 28411151Smitch.hayenga@arm.com cpu->wakeup(tid); 28511148Smitch.hayenga@arm.com } 28610529Smorr@cs.wisc.edu } 28710529Smorr@cs.wisc.edu 28810030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 28911356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 29011356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 29111356Skrinat01@arm.com // the processor accordingly 29211356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 29310030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 29410030SAli.Saidi@ARM.com pkt->getAddr()); 29511147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 29611147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 29711147Smitch.hayenga@arm.com } 29810030SAli.Saidi@ARM.com } 29910030SAli.Saidi@ARM.com 30010030SAli.Saidi@ARM.com return 0; 30110030SAli.Saidi@ARM.com} 30210030SAli.Saidi@ARM.com 30310030SAli.Saidi@ARM.comvoid 30410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 30510030SAli.Saidi@ARM.com{ 30610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 30710030SAli.Saidi@ARM.com pkt->cmdString()); 30810030SAli.Saidi@ARM.com 30910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 31010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 31111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 31211321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 31311151Smitch.hayenga@arm.com cpu->wakeup(tid); 31411148Smitch.hayenga@arm.com } 31510529Smorr@cs.wisc.edu } 31610529Smorr@cs.wisc.edu 31710030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 31810030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 31910030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 32010030SAli.Saidi@ARM.com pkt->getAddr()); 32111147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 32211147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 32311147Smitch.hayenga@arm.com } 32410030SAli.Saidi@ARM.com } 32510030SAli.Saidi@ARM.com} 32610030SAli.Saidi@ARM.com 3272623SN/AFault 32811608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 32911608Snikos.nikoleris@arm.com Request::Flags flags) 3302623SN/A{ 33111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 33211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 33311147Smitch.hayenga@arm.com 3343169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3354870Sstever@eecs.umich.edu Request *req = &data_read_req; 3362623SN/A 33710665SAli.Saidi@ARM.com if (traceData) 33810665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3392623SN/A 3404999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3417520Sgblack@eecs.umich.edu int fullSize = size; 3422623SN/A 3434999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3444999Sgblack@eecs.umich.edu //across a cache line boundary. 3459814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3464999Sgblack@eecs.umich.edu 3477520Sgblack@eecs.umich.edu if (secondAddr > addr) 3487520Sgblack@eecs.umich.edu size = secondAddr - addr; 3494999Sgblack@eecs.umich.edu 3504999Sgblack@eecs.umich.edu dcache_latency = 0; 3514999Sgblack@eecs.umich.edu 35210024Sdam.sunwoo@arm.com req->taskId(taskId()); 3537520Sgblack@eecs.umich.edu while (1) { 3548832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3554999Sgblack@eecs.umich.edu 3564999Sgblack@eecs.umich.edu // translate to physical address 35711147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 35811147Smitch.hayenga@arm.com BaseTLB::Read); 3594999Sgblack@eecs.umich.edu 3604999Sgblack@eecs.umich.edu // Now do the access. 3616623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 36210739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3637520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3644999Sgblack@eecs.umich.edu 3658105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3664999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3674999Sgblack@eecs.umich.edu else { 3688931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3698931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3704999Sgblack@eecs.umich.edu else 3714999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3724999Sgblack@eecs.umich.edu } 3734999Sgblack@eecs.umich.edu dcache_access = true; 3745012Sgblack@eecs.umich.edu 3754999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3764999Sgblack@eecs.umich.edu 3776102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3784999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3794999Sgblack@eecs.umich.edu } 3804968Sacolyte@umich.edu } 3814986Ssaidi@eecs.umich.edu 3824999Sgblack@eecs.umich.edu //If there's a fault, return it 3836739Sgblack@eecs.umich.edu if (fault != NoFault) { 3846739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3856739Sgblack@eecs.umich.edu return NoFault; 3866739Sgblack@eecs.umich.edu } else { 3876739Sgblack@eecs.umich.edu return fault; 3886739Sgblack@eecs.umich.edu } 3896739Sgblack@eecs.umich.edu } 3906739Sgblack@eecs.umich.edu 3914999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3924999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3934999Sgblack@eecs.umich.edu { 39410760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3956078Sgblack@eecs.umich.edu assert(!locked); 3966078Sgblack@eecs.umich.edu locked = true; 3976078Sgblack@eecs.umich.edu } 39811147Smitch.hayenga@arm.com 3994999Sgblack@eecs.umich.edu return fault; 4004968Sacolyte@umich.edu } 4013170Sstever@eecs.umich.edu 4024999Sgblack@eecs.umich.edu /* 4034999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4044999Sgblack@eecs.umich.edu */ 4054999Sgblack@eecs.umich.edu 4064999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4077520Sgblack@eecs.umich.edu data += size; 4084999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4097520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4104999Sgblack@eecs.umich.edu //And access the right address. 4114999Sgblack@eecs.umich.edu addr = secondAddr; 4122623SN/A } 4132623SN/A} 4142623SN/A 41511303Ssteve.reinhardt@amd.comFault 41611608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 41711608Snikos.nikoleris@arm.com Request::Flags flags) 41811303Ssteve.reinhardt@amd.com{ 41911303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 42011303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 42111303Ssteve.reinhardt@amd.com} 4227520Sgblack@eecs.umich.edu 4232623SN/AFault 42411608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 42511608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4262623SN/A{ 42711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 42811147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 42910031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 43010031SAli.Saidi@ARM.com 43110031SAli.Saidi@ARM.com if (data == NULL) { 43210031SAli.Saidi@ARM.com assert(size <= 64); 43310031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 43410031SAli.Saidi@ARM.com // This must be a cache block cleaning request 43510031SAli.Saidi@ARM.com data = zero_array; 43610031SAli.Saidi@ARM.com } 43710031SAli.Saidi@ARM.com 4383169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4394870Sstever@eecs.umich.edu Request *req = &data_write_req; 4402623SN/A 44110665SAli.Saidi@ARM.com if (traceData) 44210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4432623SN/A 4444999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4457520Sgblack@eecs.umich.edu int fullSize = size; 4462623SN/A 4474999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4484999Sgblack@eecs.umich.edu //across a cache line boundary. 4499814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4504999Sgblack@eecs.umich.edu 45111321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4527520Sgblack@eecs.umich.edu size = secondAddr - addr; 4534999Sgblack@eecs.umich.edu 4544999Sgblack@eecs.umich.edu dcache_latency = 0; 4554999Sgblack@eecs.umich.edu 45610024Sdam.sunwoo@arm.com req->taskId(taskId()); 45711321Ssteve.reinhardt@amd.com while (1) { 4588832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4594999Sgblack@eecs.umich.edu 4604999Sgblack@eecs.umich.edu // translate to physical address 46111147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4624999Sgblack@eecs.umich.edu 4634999Sgblack@eecs.umich.edu // Now do the access. 4644999Sgblack@eecs.umich.edu if (fault == NoFault) { 4654999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4664999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4674999Sgblack@eecs.umich.edu 4686102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4694999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 47010030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4714999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4724999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4734999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4744999Sgblack@eecs.umich.edu assert(res); 4754999Sgblack@eecs.umich.edu req->setExtraData(*res); 4764999Sgblack@eecs.umich.edu } 4774999Sgblack@eecs.umich.edu } 4784999Sgblack@eecs.umich.edu 4796623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4808949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4817520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4824999Sgblack@eecs.umich.edu 4838105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4844999Sgblack@eecs.umich.edu dcache_latency += 4854999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4864999Sgblack@eecs.umich.edu } else { 4878931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4888931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4894999Sgblack@eecs.umich.edu else 4904999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 49111148Smitch.hayenga@arm.com 49211148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 49311148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 4944999Sgblack@eecs.umich.edu } 4954999Sgblack@eecs.umich.edu dcache_access = true; 4964999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4974999Sgblack@eecs.umich.edu 4984999Sgblack@eecs.umich.edu if (req->isSwap()) { 4994999Sgblack@eecs.umich.edu assert(res); 50010563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 5014999Sgblack@eecs.umich.edu } 5024999Sgblack@eecs.umich.edu } 5034999Sgblack@eecs.umich.edu 5044999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5054999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5064878Sstever@eecs.umich.edu } 5074040Ssaidi@eecs.umich.edu } 5084040Ssaidi@eecs.umich.edu 5094999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5104999Sgblack@eecs.umich.edu //stop now. 5114999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5124999Sgblack@eecs.umich.edu { 51310760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5146078Sgblack@eecs.umich.edu assert(locked); 5156078Sgblack@eecs.umich.edu locked = false; 5166078Sgblack@eecs.umich.edu } 51711147Smitch.hayenga@arm.com 51811147Smitch.hayenga@arm.com 5196739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5206739Sgblack@eecs.umich.edu return NoFault; 5216739Sgblack@eecs.umich.edu } else { 5226739Sgblack@eecs.umich.edu return fault; 5236739Sgblack@eecs.umich.edu } 5243170Sstever@eecs.umich.edu } 5253170Sstever@eecs.umich.edu 5264999Sgblack@eecs.umich.edu /* 5274999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5284999Sgblack@eecs.umich.edu */ 5294999Sgblack@eecs.umich.edu 5304999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5317520Sgblack@eecs.umich.edu data += size; 5324999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5337520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5344999Sgblack@eecs.umich.edu //And access the right address. 5354999Sgblack@eecs.umich.edu addr = secondAddr; 5362623SN/A } 5372623SN/A} 5382623SN/A 5392623SN/A 5402623SN/Avoid 5412623SN/AAtomicSimpleCPU::tick() 5422623SN/A{ 5434940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5444940Snate@binkert.org 54511147Smitch.hayenga@arm.com // Change thread if multi-threaded 54611147Smitch.hayenga@arm.com swapActiveThread(); 54711147Smitch.hayenga@arm.com 54811147Smitch.hayenga@arm.com // Set memroy request ids to current thread 54911147Smitch.hayenga@arm.com if (numThreads > 1) { 55011148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 55111148Smitch.hayenga@arm.com 55211435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 55311435Smitch.hayenga@arm.com data_read_req.setContext(cid); 55411435Smitch.hayenga@arm.com data_write_req.setContext(cid); 55511147Smitch.hayenga@arm.com } 55611147Smitch.hayenga@arm.com 55711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 55811147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 55911147Smitch.hayenga@arm.com 5605487Snate@binkert.org Tick latency = 0; 5612623SN/A 5626078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5632623SN/A numCycles++; 56412284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5652623SN/A 56610596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5673387Sgblack@eecs.umich.edu checkForInterrupts(); 56810596Sgabeblack@google.com checkPcEventQueue(); 56910596Sgabeblack@google.com } 5702626SN/A 5718143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5729443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5739443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5748143SAli.Saidi@ARM.com return; 5759443SAndreas.Sandberg@ARM.com } 5765348Ssaidi@eecs.umich.edu 5775669Sgblack@eecs.umich.edu Fault fault = NoFault; 5785669Sgblack@eecs.umich.edu 5797720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5807720Sgblack@eecs.umich.edu 5817720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5827720Sgblack@eecs.umich.edu !curMacroStaticInst; 5837720Sgblack@eecs.umich.edu if (needToFetch) { 58410024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5855894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 58611147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5876023Snate@binkert.org BaseTLB::Execute); 5885894Sgblack@eecs.umich.edu } 5892623SN/A 5902623SN/A if (fault == NoFault) { 5914182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5924182Sgblack@eecs.umich.edu bool icache_access = false; 5934182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5942662Sstever@eecs.umich.edu 5957720Sgblack@eecs.umich.edu if (needToFetch) { 5969023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5975694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5985694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5995694Sgblack@eecs.umich.edu // this code should be uncommented. 6005669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 60111321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 6025669Sgblack@eecs.umich.edu //{ 6035669Sgblack@eecs.umich.edu icache_access = true; 6048949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6055669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6062623SN/A 6078931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6088931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6095669Sgblack@eecs.umich.edu else 6105669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6114968Sacolyte@umich.edu 6125669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6134968Sacolyte@umich.edu 6145669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6155669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6165669Sgblack@eecs.umich.edu //} 6175669Sgblack@eecs.umich.edu } 6184182Sgblack@eecs.umich.edu 6192623SN/A preExecute(); 6203814Ssaidi@eecs.umich.edu 62111877Sbrandon.potter@amd.com Tick stall_ticks = 0; 6225001Sgblack@eecs.umich.edu if (curStaticInst) { 62311147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6244998Sgblack@eecs.umich.edu 6254998Sgblack@eecs.umich.edu // keep an instruction count 62610381Sdam.sunwoo@arm.com if (fault == NoFault) { 6274998Sgblack@eecs.umich.edu countInst(); 62810651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 62910381Sdam.sunwoo@arm.com } 6307655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6315001Sgblack@eecs.umich.edu delete traceData; 6325001Sgblack@eecs.umich.edu traceData = NULL; 6335001Sgblack@eecs.umich.edu } 6344998Sgblack@eecs.umich.edu 63511877Sbrandon.potter@amd.com if (dynamic_pointer_cast<SyscallRetryFault>(fault)) { 63611877Sbrandon.potter@amd.com // Retry execution of system calls after a delay. 63711877Sbrandon.potter@amd.com // Prevents immediate re-execution since conditions which 63811877Sbrandon.potter@amd.com // caused the retry are unlikely to change every tick. 63911877Sbrandon.potter@amd.com stall_ticks += clockEdge(syscallRetryLatency) - curTick(); 64011877Sbrandon.potter@amd.com } 64111877Sbrandon.potter@amd.com 6424182Sgblack@eecs.umich.edu postExecute(); 6434182Sgblack@eecs.umich.edu } 6442623SN/A 6453814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6464539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6474539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6483814Ssaidi@eecs.umich.edu instCnt++; 6493814Ssaidi@eecs.umich.edu 6505487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6515487Snate@binkert.org stall_ticks += icache_latency; 6525487Snate@binkert.org 6535487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6545487Snate@binkert.org stall_ticks += dcache_latency; 6555487Snate@binkert.org 6565487Snate@binkert.org if (stall_ticks) { 6579180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6589180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6599180Sandreas.hansson@arm.com // period 6609180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6619180Sandreas.hansson@arm.com clockPeriod(); 6622623SN/A } 6632623SN/A 6642623SN/A } 66511321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6664182Sgblack@eecs.umich.edu advancePC(fault); 6672623SN/A } 6682623SN/A 6699443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6709443SAndreas.Sandberg@ARM.com return; 6719443SAndreas.Sandberg@ARM.com 6725487Snate@binkert.org // instruction takes at least one cycle 6739179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6749179Sandreas.hansson@arm.com latency = clockPeriod(); 6755487Snate@binkert.org 6762626SN/A if (_status != Idle) 67711147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6782623SN/A} 6792623SN/A 68010381Sdam.sunwoo@arm.comvoid 68110381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 68210381Sdam.sunwoo@arm.com{ 68310464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68410464SAndreas.Sandberg@ARM.com 68510381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68610381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68710381Sdam.sunwoo@arm.com} 6882623SN/A 6895315Sstever@gmail.comvoid 6905315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6915315Sstever@gmail.com{ 6925315Sstever@gmail.com dcachePort.printAddr(a); 6935315Sstever@gmail.com} 6945315Sstever@gmail.com 6952623SN/A//////////////////////////////////////////////////////////////////////// 6962623SN/A// 6972623SN/A// AtomicSimpleCPU Simulation Object 6982623SN/A// 6994762Snate@binkert.orgAtomicSimpleCPU * 7004762Snate@binkert.orgAtomicSimpleCPUParams::create() 7012623SN/A{ 7025529Snate@binkert.org return new AtomicSimpleCPU(this); 7032623SN/A} 704