atomic.cc revision 11793
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/atomic.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 494040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 509647Sdam.sunwoo@arm.com#include "base/output.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 522623SN/A#include "cpu/exetrace.hh" 539443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 548232Snate@binkert.org#include "debug/ExecFaulting.hh" 558232Snate@binkert.org#include "debug/SimpleCPU.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 573348Sbinkertn@umich.edu#include "mem/packet_access.hh" 588926Sandreas.hansson@arm.com#include "mem/physical.hh" 594762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 607678Sgblack@eecs.umich.edu#include "sim/faults.hh" 6111793Sbrandon.potter@amd.com#include "sim/full_system.hh" 622901Ssaidi@eecs.umich.edu#include "sim/system.hh" 632623SN/A 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 685606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 692623SN/A{ 702623SN/A} 712623SN/A 722623SN/A 732623SN/Avoid 742623SN/AAtomicSimpleCPU::TickEvent::process() 752623SN/A{ 762623SN/A cpu->tick(); 772623SN/A} 782623SN/A 792623SN/Aconst char * 805336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 812623SN/A{ 824873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 832623SN/A} 842623SN/A 852623SN/Avoid 862623SN/AAtomicSimpleCPU::init() 872623SN/A{ 8811147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 898921Sandreas.hansson@arm.com 9011148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 9111435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 9211435Smitch.hayenga@arm.com data_read_req.setContext(cid); 9311435Smitch.hayenga@arm.com data_write_req.setContext(cid); 942623SN/A} 952623SN/A 965529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 976078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 985487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 995487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1009095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1019095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 10210537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 10310537Sandreas.hansson@arm.com ppCommit(nullptr) 1042623SN/A{ 1052623SN/A _status = Idle; 1062623SN/A} 1072623SN/A 1082623SN/A 1092623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1102623SN/A{ 1116775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1126775SBrad.Beckmann@amd.com deschedule(tickEvent); 1136775SBrad.Beckmann@amd.com } 1142623SN/A} 1152623SN/A 11610913Sandreas.sandberg@arm.comDrainState 11710913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1182623SN/A{ 1199448SAndreas.Sandberg@ARM.com if (switchedOut()) 12010913Sandreas.sandberg@arm.com return DrainState::Drained; 1212623SN/A 1229443SAndreas.Sandberg@ARM.com if (!isDrained()) { 12311147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 12410913Sandreas.sandberg@arm.com return DrainState::Draining; 1259443SAndreas.Sandberg@ARM.com } else { 1269443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1279443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1282915Sktlim@umich.edu 12911147Smitch.hayenga@arm.com activeThreads.clear(); 1309443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 13110913Sandreas.sandberg@arm.com return DrainState::Drained; 1329443SAndreas.Sandberg@ARM.com } 1339342SAndreas.Sandberg@arm.com} 1349342SAndreas.Sandberg@arm.com 1352915Sktlim@umich.eduvoid 13611148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 13711148Smitch.hayenga@arm.com{ 13811148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 13911148Smitch.hayenga@arm.com pkt->cmdString()); 14011148Smitch.hayenga@arm.com 14111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 14211148Smitch.hayenga@arm.com if (tid != sender) { 14311321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 14411151Smitch.hayenga@arm.com wakeup(tid); 14511148Smitch.hayenga@arm.com } 14611148Smitch.hayenga@arm.com 14711148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 14811148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 14911148Smitch.hayenga@arm.com } 15011148Smitch.hayenga@arm.com } 15111148Smitch.hayenga@arm.com} 15211148Smitch.hayenga@arm.com 15311148Smitch.hayenga@arm.comvoid 1549342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1552915Sktlim@umich.edu{ 1569448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1579448SAndreas.Sandberg@ARM.com if (switchedOut()) 1585220Ssaidi@eecs.umich.edu return; 1595220Ssaidi@eecs.umich.edu 1604940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1619523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1623324Shsul@eecs.umich.edu 1639448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1649448SAndreas.Sandberg@ARM.com 16511147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 16611147Smitch.hayenga@arm.com 16711147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 16811147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 16911147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 17011147Smitch.hayenga@arm.com activeThreads.push_back(tid); 17111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 17211147Smitch.hayenga@arm.com 17311147Smitch.hayenga@arm.com // Tick if any threads active 17411147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 17511147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 17611147Smitch.hayenga@arm.com } 17711147Smitch.hayenga@arm.com } else { 17811147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 17911147Smitch.hayenga@arm.com } 1809448SAndreas.Sandberg@ARM.com } 1812623SN/A} 1822623SN/A 1839443SAndreas.Sandberg@ARM.combool 1849443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1859443SAndreas.Sandberg@ARM.com{ 18610913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1879443SAndreas.Sandberg@ARM.com return false; 1889443SAndreas.Sandberg@ARM.com 18911147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1909443SAndreas.Sandberg@ARM.com if (!isDrained()) 1919443SAndreas.Sandberg@ARM.com return false; 1929443SAndreas.Sandberg@ARM.com 1939443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 19410913Sandreas.sandberg@arm.com signalDrainDone(); 1959443SAndreas.Sandberg@ARM.com 1969443SAndreas.Sandberg@ARM.com return true; 1979443SAndreas.Sandberg@ARM.com} 1989443SAndreas.Sandberg@ARM.com 1999443SAndreas.Sandberg@ARM.com 2002623SN/Avoid 2012798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2022623SN/A{ 2039429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 2049429SAndreas.Sandberg@ARM.com 2059443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 2069342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2079443SAndreas.Sandberg@ARM.com assert(isDrained()); 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2132623SN/A{ 2149429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2152623SN/A 2169443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2172623SN/A assert(!tickEvent.scheduled()); 2182623SN/A} 2192623SN/A 2209523SAndreas.Sandberg@ARM.comvoid 2219523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2229523SAndreas.Sandberg@ARM.com{ 2239524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2249523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2259523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2269523SAndreas.Sandberg@ARM.com } 2279523SAndreas.Sandberg@ARM.com} 2282623SN/A 2292623SN/Avoid 23010407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2312623SN/A{ 23210407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2334940Snate@binkert.org 23411147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2352623SN/A 23611147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 23711147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 23811147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 23910464SAndreas.Sandberg@ARM.com numCycles += delta; 24010464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2413686Sktlim@umich.edu 24211147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 24311147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 24411147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 24511147Smitch.hayenga@arm.com } 2469342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 24711147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 24811147Smitch.hayenga@arm.com == activeThreads.end()) { 24911147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 25011147Smitch.hayenga@arm.com } 25111526Sdavid.guillen@arm.com 25211526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2532623SN/A} 2542623SN/A 2552623SN/A 2562623SN/Avoid 2578737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2582623SN/A{ 2594940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2604940Snate@binkert.org 26111147Smitch.hayenga@arm.com assert(thread_num < numThreads); 26211147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2632623SN/A 2646043Sgblack@eecs.umich.edu if (_status == Idle) 2656043Sgblack@eecs.umich.edu return; 2666043Sgblack@eecs.umich.edu 2679342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2682626SN/A 26911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2702623SN/A 27111147Smitch.hayenga@arm.com if (activeThreads.empty()) { 27211147Smitch.hayenga@arm.com _status = Idle; 27311147Smitch.hayenga@arm.com 27411147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 27511147Smitch.hayenga@arm.com deschedule(tickEvent); 27611147Smitch.hayenga@arm.com } 27711147Smitch.hayenga@arm.com } 27811147Smitch.hayenga@arm.com 27911526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2802623SN/A} 2812623SN/A 2822623SN/A 28310030SAli.Saidi@ARM.comTick 28410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 28510030SAli.Saidi@ARM.com{ 28610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 28710030SAli.Saidi@ARM.com pkt->cmdString()); 28810030SAli.Saidi@ARM.com 28910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 29010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 29111148Smitch.hayenga@arm.com 29211148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 29311148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 29411151Smitch.hayenga@arm.com cpu->wakeup(tid); 29511148Smitch.hayenga@arm.com } 29610529Smorr@cs.wisc.edu } 29710529Smorr@cs.wisc.edu 29810030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29911356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 30011356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 30111356Skrinat01@arm.com // the processor accordingly 30211356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 30310030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30410030SAli.Saidi@ARM.com pkt->getAddr()); 30511147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 30611147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 30711147Smitch.hayenga@arm.com } 30810030SAli.Saidi@ARM.com } 30910030SAli.Saidi@ARM.com 31010030SAli.Saidi@ARM.com return 0; 31110030SAli.Saidi@ARM.com} 31210030SAli.Saidi@ARM.com 31310030SAli.Saidi@ARM.comvoid 31410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 31510030SAli.Saidi@ARM.com{ 31610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 31710030SAli.Saidi@ARM.com pkt->cmdString()); 31810030SAli.Saidi@ARM.com 31910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 32010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 32111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 32211321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 32311151Smitch.hayenga@arm.com cpu->wakeup(tid); 32411148Smitch.hayenga@arm.com } 32510529Smorr@cs.wisc.edu } 32610529Smorr@cs.wisc.edu 32710030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 32810030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 32910030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 33010030SAli.Saidi@ARM.com pkt->getAddr()); 33111147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 33211147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 33311147Smitch.hayenga@arm.com } 33410030SAli.Saidi@ARM.com } 33510030SAli.Saidi@ARM.com} 33610030SAli.Saidi@ARM.com 3372623SN/AFault 33811608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 33911608Snikos.nikoleris@arm.com Request::Flags flags) 3402623SN/A{ 34111147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 34211147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 34311147Smitch.hayenga@arm.com 3443169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3454870Sstever@eecs.umich.edu Request *req = &data_read_req; 3462623SN/A 34710665SAli.Saidi@ARM.com if (traceData) 34810665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3492623SN/A 3504999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3517520Sgblack@eecs.umich.edu int fullSize = size; 3522623SN/A 3534999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3544999Sgblack@eecs.umich.edu //across a cache line boundary. 3559814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3564999Sgblack@eecs.umich.edu 3577520Sgblack@eecs.umich.edu if (secondAddr > addr) 3587520Sgblack@eecs.umich.edu size = secondAddr - addr; 3594999Sgblack@eecs.umich.edu 3604999Sgblack@eecs.umich.edu dcache_latency = 0; 3614999Sgblack@eecs.umich.edu 36210024Sdam.sunwoo@arm.com req->taskId(taskId()); 3637520Sgblack@eecs.umich.edu while (1) { 3648832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3654999Sgblack@eecs.umich.edu 3664999Sgblack@eecs.umich.edu // translate to physical address 36711147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 36811147Smitch.hayenga@arm.com BaseTLB::Read); 3694999Sgblack@eecs.umich.edu 3704999Sgblack@eecs.umich.edu // Now do the access. 3716623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 37210739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3737520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3744999Sgblack@eecs.umich.edu 3758105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3764999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3774999Sgblack@eecs.umich.edu else { 3788931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3798931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3804999Sgblack@eecs.umich.edu else 3814999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3824999Sgblack@eecs.umich.edu } 3834999Sgblack@eecs.umich.edu dcache_access = true; 3845012Sgblack@eecs.umich.edu 3854999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3864999Sgblack@eecs.umich.edu 3876102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3884999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3894999Sgblack@eecs.umich.edu } 3904968Sacolyte@umich.edu } 3914986Ssaidi@eecs.umich.edu 3924999Sgblack@eecs.umich.edu //If there's a fault, return it 3936739Sgblack@eecs.umich.edu if (fault != NoFault) { 3946739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3956739Sgblack@eecs.umich.edu return NoFault; 3966739Sgblack@eecs.umich.edu } else { 3976739Sgblack@eecs.umich.edu return fault; 3986739Sgblack@eecs.umich.edu } 3996739Sgblack@eecs.umich.edu } 4006739Sgblack@eecs.umich.edu 4014999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 4024999Sgblack@eecs.umich.edu if (secondAddr <= addr) 4034999Sgblack@eecs.umich.edu { 40410760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 4056078Sgblack@eecs.umich.edu assert(!locked); 4066078Sgblack@eecs.umich.edu locked = true; 4076078Sgblack@eecs.umich.edu } 40811147Smitch.hayenga@arm.com 4094999Sgblack@eecs.umich.edu return fault; 4104968Sacolyte@umich.edu } 4113170Sstever@eecs.umich.edu 4124999Sgblack@eecs.umich.edu /* 4134999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4144999Sgblack@eecs.umich.edu */ 4154999Sgblack@eecs.umich.edu 4164999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4177520Sgblack@eecs.umich.edu data += size; 4184999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4197520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4204999Sgblack@eecs.umich.edu //And access the right address. 4214999Sgblack@eecs.umich.edu addr = secondAddr; 4222623SN/A } 4232623SN/A} 4242623SN/A 42511303Ssteve.reinhardt@amd.comFault 42611608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42711608Snikos.nikoleris@arm.com Request::Flags flags) 42811303Ssteve.reinhardt@amd.com{ 42911303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 43011303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 43111303Ssteve.reinhardt@amd.com} 4327520Sgblack@eecs.umich.edu 4332623SN/AFault 43411608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 43511608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4362623SN/A{ 43711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 43811147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43910031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 44010031SAli.Saidi@ARM.com 44110031SAli.Saidi@ARM.com if (data == NULL) { 44210031SAli.Saidi@ARM.com assert(size <= 64); 44310031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 44410031SAli.Saidi@ARM.com // This must be a cache block cleaning request 44510031SAli.Saidi@ARM.com data = zero_array; 44610031SAli.Saidi@ARM.com } 44710031SAli.Saidi@ARM.com 4483169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4494870Sstever@eecs.umich.edu Request *req = &data_write_req; 4502623SN/A 45110665SAli.Saidi@ARM.com if (traceData) 45210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4532623SN/A 4544999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4557520Sgblack@eecs.umich.edu int fullSize = size; 4562623SN/A 4574999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4584999Sgblack@eecs.umich.edu //across a cache line boundary. 4599814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4604999Sgblack@eecs.umich.edu 46111321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4627520Sgblack@eecs.umich.edu size = secondAddr - addr; 4634999Sgblack@eecs.umich.edu 4644999Sgblack@eecs.umich.edu dcache_latency = 0; 4654999Sgblack@eecs.umich.edu 46610024Sdam.sunwoo@arm.com req->taskId(taskId()); 46711321Ssteve.reinhardt@amd.com while (1) { 4688832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4694999Sgblack@eecs.umich.edu 4704999Sgblack@eecs.umich.edu // translate to physical address 47111147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4724999Sgblack@eecs.umich.edu 4734999Sgblack@eecs.umich.edu // Now do the access. 4744999Sgblack@eecs.umich.edu if (fault == NoFault) { 4754999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4764999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4774999Sgblack@eecs.umich.edu 4786102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4794999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 48010030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4814999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4824999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4834999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4844999Sgblack@eecs.umich.edu assert(res); 4854999Sgblack@eecs.umich.edu req->setExtraData(*res); 4864999Sgblack@eecs.umich.edu } 4874999Sgblack@eecs.umich.edu } 4884999Sgblack@eecs.umich.edu 4896623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4908949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4917520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4924999Sgblack@eecs.umich.edu 4938105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4944999Sgblack@eecs.umich.edu dcache_latency += 4954999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4964999Sgblack@eecs.umich.edu } else { 4978931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4988931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4994999Sgblack@eecs.umich.edu else 5004999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 50111148Smitch.hayenga@arm.com 50211148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 50311148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 5044999Sgblack@eecs.umich.edu } 5054999Sgblack@eecs.umich.edu dcache_access = true; 5064999Sgblack@eecs.umich.edu assert(!pkt.isError()); 5074999Sgblack@eecs.umich.edu 5084999Sgblack@eecs.umich.edu if (req->isSwap()) { 5094999Sgblack@eecs.umich.edu assert(res); 51010563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 5114999Sgblack@eecs.umich.edu } 5124999Sgblack@eecs.umich.edu } 5134999Sgblack@eecs.umich.edu 5144999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5154999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5164878Sstever@eecs.umich.edu } 5174040Ssaidi@eecs.umich.edu } 5184040Ssaidi@eecs.umich.edu 5194999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5204999Sgblack@eecs.umich.edu //stop now. 5214999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5224999Sgblack@eecs.umich.edu { 52310760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5246078Sgblack@eecs.umich.edu assert(locked); 5256078Sgblack@eecs.umich.edu locked = false; 5266078Sgblack@eecs.umich.edu } 52711147Smitch.hayenga@arm.com 52811147Smitch.hayenga@arm.com 5296739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5306739Sgblack@eecs.umich.edu return NoFault; 5316739Sgblack@eecs.umich.edu } else { 5326739Sgblack@eecs.umich.edu return fault; 5336739Sgblack@eecs.umich.edu } 5343170Sstever@eecs.umich.edu } 5353170Sstever@eecs.umich.edu 5364999Sgblack@eecs.umich.edu /* 5374999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5384999Sgblack@eecs.umich.edu */ 5394999Sgblack@eecs.umich.edu 5404999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5417520Sgblack@eecs.umich.edu data += size; 5424999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5437520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5444999Sgblack@eecs.umich.edu //And access the right address. 5454999Sgblack@eecs.umich.edu addr = secondAddr; 5462623SN/A } 5472623SN/A} 5482623SN/A 5492623SN/A 5502623SN/Avoid 5512623SN/AAtomicSimpleCPU::tick() 5522623SN/A{ 5534940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5544940Snate@binkert.org 55511147Smitch.hayenga@arm.com // Change thread if multi-threaded 55611147Smitch.hayenga@arm.com swapActiveThread(); 55711147Smitch.hayenga@arm.com 55811147Smitch.hayenga@arm.com // Set memroy request ids to current thread 55911147Smitch.hayenga@arm.com if (numThreads > 1) { 56011148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 56111148Smitch.hayenga@arm.com 56211435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 56311435Smitch.hayenga@arm.com data_read_req.setContext(cid); 56411435Smitch.hayenga@arm.com data_write_req.setContext(cid); 56511147Smitch.hayenga@arm.com } 56611147Smitch.hayenga@arm.com 56711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 56811147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 56911147Smitch.hayenga@arm.com 5705487Snate@binkert.org Tick latency = 0; 5712623SN/A 5726078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5732623SN/A numCycles++; 57410464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5752623SN/A 57610596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5773387Sgblack@eecs.umich.edu checkForInterrupts(); 57810596Sgabeblack@google.com checkPcEventQueue(); 57910596Sgabeblack@google.com } 5802626SN/A 5818143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5829443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5839443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5848143SAli.Saidi@ARM.com return; 5859443SAndreas.Sandberg@ARM.com } 5865348Ssaidi@eecs.umich.edu 5875669Sgblack@eecs.umich.edu Fault fault = NoFault; 5885669Sgblack@eecs.umich.edu 5897720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5907720Sgblack@eecs.umich.edu 5917720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5927720Sgblack@eecs.umich.edu !curMacroStaticInst; 5937720Sgblack@eecs.umich.edu if (needToFetch) { 59410024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5955894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 59611147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5976023Snate@binkert.org BaseTLB::Execute); 5985894Sgblack@eecs.umich.edu } 5992623SN/A 6002623SN/A if (fault == NoFault) { 6014182Sgblack@eecs.umich.edu Tick icache_latency = 0; 6024182Sgblack@eecs.umich.edu bool icache_access = false; 6034182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 6042662Sstever@eecs.umich.edu 6057720Sgblack@eecs.umich.edu if (needToFetch) { 6069023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 6075694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 6085694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 6095694Sgblack@eecs.umich.edu // this code should be uncommented. 6105669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 61111321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 6125669Sgblack@eecs.umich.edu //{ 6135669Sgblack@eecs.umich.edu icache_access = true; 6148949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6155669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6162623SN/A 6178931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6188931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6195669Sgblack@eecs.umich.edu else 6205669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6214968Sacolyte@umich.edu 6225669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6234968Sacolyte@umich.edu 6245669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6255669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6265669Sgblack@eecs.umich.edu //} 6275669Sgblack@eecs.umich.edu } 6284182Sgblack@eecs.umich.edu 6292623SN/A preExecute(); 6303814Ssaidi@eecs.umich.edu 6315001Sgblack@eecs.umich.edu if (curStaticInst) { 63211147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6334998Sgblack@eecs.umich.edu 6344998Sgblack@eecs.umich.edu // keep an instruction count 63510381Sdam.sunwoo@arm.com if (fault == NoFault) { 6364998Sgblack@eecs.umich.edu countInst(); 63710651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 63810381Sdam.sunwoo@arm.com } 6397655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6405001Sgblack@eecs.umich.edu delete traceData; 6415001Sgblack@eecs.umich.edu traceData = NULL; 6425001Sgblack@eecs.umich.edu } 6434998Sgblack@eecs.umich.edu 6444182Sgblack@eecs.umich.edu postExecute(); 6454182Sgblack@eecs.umich.edu } 6462623SN/A 6473814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6484539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6494539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6503814Ssaidi@eecs.umich.edu instCnt++; 6513814Ssaidi@eecs.umich.edu 6525487Snate@binkert.org Tick stall_ticks = 0; 6535487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6545487Snate@binkert.org stall_ticks += icache_latency; 6555487Snate@binkert.org 6565487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6575487Snate@binkert.org stall_ticks += dcache_latency; 6585487Snate@binkert.org 6595487Snate@binkert.org if (stall_ticks) { 6609180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6619180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6629180Sandreas.hansson@arm.com // period 6639180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6649180Sandreas.hansson@arm.com clockPeriod(); 6652623SN/A } 6662623SN/A 6672623SN/A } 66811321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6694182Sgblack@eecs.umich.edu advancePC(fault); 6702623SN/A } 6712623SN/A 6729443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6739443SAndreas.Sandberg@ARM.com return; 6749443SAndreas.Sandberg@ARM.com 6755487Snate@binkert.org // instruction takes at least one cycle 6769179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6779179Sandreas.hansson@arm.com latency = clockPeriod(); 6785487Snate@binkert.org 6792626SN/A if (_status != Idle) 68011147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6812623SN/A} 6822623SN/A 68310381Sdam.sunwoo@arm.comvoid 68410381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 68510381Sdam.sunwoo@arm.com{ 68610464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68710464SAndreas.Sandberg@ARM.com 68810381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68910381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 69010381Sdam.sunwoo@arm.com} 6912623SN/A 6925315Sstever@gmail.comvoid 6935315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6945315Sstever@gmail.com{ 6955315Sstever@gmail.com dcachePort.printAddr(a); 6965315Sstever@gmail.com} 6975315Sstever@gmail.com 6982623SN/A//////////////////////////////////////////////////////////////////////// 6992623SN/A// 7002623SN/A// AtomicSimpleCPU Simulation Object 7012623SN/A// 7024762Snate@binkert.orgAtomicSimpleCPU * 7034762Snate@binkert.orgAtomicSimpleCPUParams::create() 7042623SN/A{ 7055529Snate@binkert.org return new AtomicSimpleCPU(this); 7062623SN/A} 707