atomic.cc revision 11608
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 489647Sdam.sunwoo@arm.com#include "base/output.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 508229Snate@binkert.org#include "cpu/simple/atomic.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 675606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 682623SN/A{ 692623SN/A} 702623SN/A 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::TickEvent::process() 742623SN/A{ 752623SN/A cpu->tick(); 762623SN/A} 772623SN/A 782623SN/Aconst char * 795336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 802623SN/A{ 814873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/AAtomicSimpleCPU::init() 862623SN/A{ 8711147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 888921Sandreas.hansson@arm.com 8911148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 9011435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 9111435Smitch.hayenga@arm.com data_read_req.setContext(cid); 9211435Smitch.hayenga@arm.com data_write_req.setContext(cid); 932623SN/A} 942623SN/A 955529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 966078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 975487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 985487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 999095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1009095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 10110537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 10210537Sandreas.hansson@arm.com ppCommit(nullptr) 1032623SN/A{ 1042623SN/A _status = Idle; 1052623SN/A} 1062623SN/A 1072623SN/A 1082623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1092623SN/A{ 1106775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1116775SBrad.Beckmann@amd.com deschedule(tickEvent); 1126775SBrad.Beckmann@amd.com } 1132623SN/A} 1142623SN/A 11510913Sandreas.sandberg@arm.comDrainState 11610913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1172623SN/A{ 1189448SAndreas.Sandberg@ARM.com if (switchedOut()) 11910913Sandreas.sandberg@arm.com return DrainState::Drained; 1202623SN/A 1219443SAndreas.Sandberg@ARM.com if (!isDrained()) { 12211147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 12310913Sandreas.sandberg@arm.com return DrainState::Draining; 1249443SAndreas.Sandberg@ARM.com } else { 1259443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1269443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1272915Sktlim@umich.edu 12811147Smitch.hayenga@arm.com activeThreads.clear(); 1299443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 13010913Sandreas.sandberg@arm.com return DrainState::Drained; 1319443SAndreas.Sandberg@ARM.com } 1329342SAndreas.Sandberg@arm.com} 1339342SAndreas.Sandberg@arm.com 1342915Sktlim@umich.eduvoid 13511148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 13611148Smitch.hayenga@arm.com{ 13711148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 13811148Smitch.hayenga@arm.com pkt->cmdString()); 13911148Smitch.hayenga@arm.com 14011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 14111148Smitch.hayenga@arm.com if (tid != sender) { 14211321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 14311151Smitch.hayenga@arm.com wakeup(tid); 14411148Smitch.hayenga@arm.com } 14511148Smitch.hayenga@arm.com 14611148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 14711148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 14811148Smitch.hayenga@arm.com } 14911148Smitch.hayenga@arm.com } 15011148Smitch.hayenga@arm.com} 15111148Smitch.hayenga@arm.com 15211148Smitch.hayenga@arm.comvoid 1539342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1542915Sktlim@umich.edu{ 1559448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1569448SAndreas.Sandberg@ARM.com if (switchedOut()) 1575220Ssaidi@eecs.umich.edu return; 1585220Ssaidi@eecs.umich.edu 1594940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1609523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1613324Shsul@eecs.umich.edu 1629448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1639448SAndreas.Sandberg@ARM.com 16411147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 16711147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 16811147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 16911147Smitch.hayenga@arm.com activeThreads.push_back(tid); 17011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 17111147Smitch.hayenga@arm.com 17211147Smitch.hayenga@arm.com // Tick if any threads active 17311147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 17411147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 17511147Smitch.hayenga@arm.com } 17611147Smitch.hayenga@arm.com } else { 17711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 17811147Smitch.hayenga@arm.com } 1799448SAndreas.Sandberg@ARM.com } 1802623SN/A} 1812623SN/A 1829443SAndreas.Sandberg@ARM.combool 1839443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1849443SAndreas.Sandberg@ARM.com{ 18510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1869443SAndreas.Sandberg@ARM.com return false; 1879443SAndreas.Sandberg@ARM.com 18811147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1899443SAndreas.Sandberg@ARM.com if (!isDrained()) 1909443SAndreas.Sandberg@ARM.com return false; 1919443SAndreas.Sandberg@ARM.com 1929443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 19310913Sandreas.sandberg@arm.com signalDrainDone(); 1949443SAndreas.Sandberg@ARM.com 1959443SAndreas.Sandberg@ARM.com return true; 1969443SAndreas.Sandberg@ARM.com} 1979443SAndreas.Sandberg@ARM.com 1989443SAndreas.Sandberg@ARM.com 1992623SN/Avoid 2002798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2012623SN/A{ 2029429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 2039429SAndreas.Sandberg@ARM.com 2049443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 2059342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2069443SAndreas.Sandberg@ARM.com assert(isDrained()); 2072623SN/A} 2082623SN/A 2092623SN/A 2102623SN/Avoid 2112623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2122623SN/A{ 2139429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2142623SN/A 2159443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2162623SN/A assert(!tickEvent.scheduled()); 2172623SN/A} 2182623SN/A 2199523SAndreas.Sandberg@ARM.comvoid 2209523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2219523SAndreas.Sandberg@ARM.com{ 2229524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2239523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2249523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2259523SAndreas.Sandberg@ARM.com } 2269523SAndreas.Sandberg@ARM.com} 2272623SN/A 2282623SN/Avoid 22910407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2302623SN/A{ 23110407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2324940Snate@binkert.org 23311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2342623SN/A 23511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 23611147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 23711147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 23810464SAndreas.Sandberg@ARM.com numCycles += delta; 23910464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2403686Sktlim@umich.edu 24111147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 24211147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 24311147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 24411147Smitch.hayenga@arm.com } 2459342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 24611147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 24711147Smitch.hayenga@arm.com == activeThreads.end()) { 24811147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 24911147Smitch.hayenga@arm.com } 25011526Sdavid.guillen@arm.com 25111526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2522623SN/A} 2532623SN/A 2542623SN/A 2552623SN/Avoid 2568737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2572623SN/A{ 2584940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2594940Snate@binkert.org 26011147Smitch.hayenga@arm.com assert(thread_num < numThreads); 26111147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2622623SN/A 2636043Sgblack@eecs.umich.edu if (_status == Idle) 2646043Sgblack@eecs.umich.edu return; 2656043Sgblack@eecs.umich.edu 2669342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2672626SN/A 26811147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2692623SN/A 27011147Smitch.hayenga@arm.com if (activeThreads.empty()) { 27111147Smitch.hayenga@arm.com _status = Idle; 27211147Smitch.hayenga@arm.com 27311147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 27411147Smitch.hayenga@arm.com deschedule(tickEvent); 27511147Smitch.hayenga@arm.com } 27611147Smitch.hayenga@arm.com } 27711147Smitch.hayenga@arm.com 27811526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2792623SN/A} 2802623SN/A 2812623SN/A 28210030SAli.Saidi@ARM.comTick 28310030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 28410030SAli.Saidi@ARM.com{ 28510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 28610030SAli.Saidi@ARM.com pkt->cmdString()); 28710030SAli.Saidi@ARM.com 28810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 28910529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 29011148Smitch.hayenga@arm.com 29111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 29211148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 29311151Smitch.hayenga@arm.com cpu->wakeup(tid); 29411148Smitch.hayenga@arm.com } 29510529Smorr@cs.wisc.edu } 29610529Smorr@cs.wisc.edu 29710030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29811356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 29911356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 30011356Skrinat01@arm.com // the processor accordingly 30111356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 30210030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30310030SAli.Saidi@ARM.com pkt->getAddr()); 30411147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 30511147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 30611147Smitch.hayenga@arm.com } 30710030SAli.Saidi@ARM.com } 30810030SAli.Saidi@ARM.com 30910030SAli.Saidi@ARM.com return 0; 31010030SAli.Saidi@ARM.com} 31110030SAli.Saidi@ARM.com 31210030SAli.Saidi@ARM.comvoid 31310030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 31410030SAli.Saidi@ARM.com{ 31510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 31610030SAli.Saidi@ARM.com pkt->cmdString()); 31710030SAli.Saidi@ARM.com 31810529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 31910529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 32011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 32111321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 32211151Smitch.hayenga@arm.com cpu->wakeup(tid); 32311148Smitch.hayenga@arm.com } 32410529Smorr@cs.wisc.edu } 32510529Smorr@cs.wisc.edu 32610030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 32710030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 32810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 32910030SAli.Saidi@ARM.com pkt->getAddr()); 33011147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 33111147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 33211147Smitch.hayenga@arm.com } 33310030SAli.Saidi@ARM.com } 33410030SAli.Saidi@ARM.com} 33510030SAli.Saidi@ARM.com 3362623SN/AFault 33711608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 33811608Snikos.nikoleris@arm.com Request::Flags flags) 3392623SN/A{ 34011147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 34111147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 34211147Smitch.hayenga@arm.com 3433169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3444870Sstever@eecs.umich.edu Request *req = &data_read_req; 3452623SN/A 34610665SAli.Saidi@ARM.com if (traceData) 34710665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3482623SN/A 3494999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3507520Sgblack@eecs.umich.edu int fullSize = size; 3512623SN/A 3524999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3534999Sgblack@eecs.umich.edu //across a cache line boundary. 3549814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3554999Sgblack@eecs.umich.edu 3567520Sgblack@eecs.umich.edu if (secondAddr > addr) 3577520Sgblack@eecs.umich.edu size = secondAddr - addr; 3584999Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu dcache_latency = 0; 3604999Sgblack@eecs.umich.edu 36110024Sdam.sunwoo@arm.com req->taskId(taskId()); 3627520Sgblack@eecs.umich.edu while (1) { 3638832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3644999Sgblack@eecs.umich.edu 3654999Sgblack@eecs.umich.edu // translate to physical address 36611147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 36711147Smitch.hayenga@arm.com BaseTLB::Read); 3684999Sgblack@eecs.umich.edu 3694999Sgblack@eecs.umich.edu // Now do the access. 3706623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 37110739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3727520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3734999Sgblack@eecs.umich.edu 3748105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3754999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3764999Sgblack@eecs.umich.edu else { 3778931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3788931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3794999Sgblack@eecs.umich.edu else 3804999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3814999Sgblack@eecs.umich.edu } 3824999Sgblack@eecs.umich.edu dcache_access = true; 3835012Sgblack@eecs.umich.edu 3844999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3854999Sgblack@eecs.umich.edu 3866102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3874999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3884999Sgblack@eecs.umich.edu } 3894968Sacolyte@umich.edu } 3904986Ssaidi@eecs.umich.edu 3914999Sgblack@eecs.umich.edu //If there's a fault, return it 3926739Sgblack@eecs.umich.edu if (fault != NoFault) { 3936739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3946739Sgblack@eecs.umich.edu return NoFault; 3956739Sgblack@eecs.umich.edu } else { 3966739Sgblack@eecs.umich.edu return fault; 3976739Sgblack@eecs.umich.edu } 3986739Sgblack@eecs.umich.edu } 3996739Sgblack@eecs.umich.edu 4004999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 4014999Sgblack@eecs.umich.edu if (secondAddr <= addr) 4024999Sgblack@eecs.umich.edu { 40310760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 4046078Sgblack@eecs.umich.edu assert(!locked); 4056078Sgblack@eecs.umich.edu locked = true; 4066078Sgblack@eecs.umich.edu } 40711147Smitch.hayenga@arm.com 4084999Sgblack@eecs.umich.edu return fault; 4094968Sacolyte@umich.edu } 4103170Sstever@eecs.umich.edu 4114999Sgblack@eecs.umich.edu /* 4124999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4134999Sgblack@eecs.umich.edu */ 4144999Sgblack@eecs.umich.edu 4154999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4167520Sgblack@eecs.umich.edu data += size; 4174999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4187520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4194999Sgblack@eecs.umich.edu //And access the right address. 4204999Sgblack@eecs.umich.edu addr = secondAddr; 4212623SN/A } 4222623SN/A} 4232623SN/A 42411303Ssteve.reinhardt@amd.comFault 42511608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 42611608Snikos.nikoleris@arm.com Request::Flags flags) 42711303Ssteve.reinhardt@amd.com{ 42811303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 42911303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 43011303Ssteve.reinhardt@amd.com} 4317520Sgblack@eecs.umich.edu 4322623SN/AFault 43311608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 43411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4352623SN/A{ 43611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 43711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43810031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 43910031SAli.Saidi@ARM.com 44010031SAli.Saidi@ARM.com if (data == NULL) { 44110031SAli.Saidi@ARM.com assert(size <= 64); 44210031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 44310031SAli.Saidi@ARM.com // This must be a cache block cleaning request 44410031SAli.Saidi@ARM.com data = zero_array; 44510031SAli.Saidi@ARM.com } 44610031SAli.Saidi@ARM.com 4473169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4484870Sstever@eecs.umich.edu Request *req = &data_write_req; 4492623SN/A 45010665SAli.Saidi@ARM.com if (traceData) 45110665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4522623SN/A 4534999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4547520Sgblack@eecs.umich.edu int fullSize = size; 4552623SN/A 4564999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4574999Sgblack@eecs.umich.edu //across a cache line boundary. 4589814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4594999Sgblack@eecs.umich.edu 46011321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4617520Sgblack@eecs.umich.edu size = secondAddr - addr; 4624999Sgblack@eecs.umich.edu 4634999Sgblack@eecs.umich.edu dcache_latency = 0; 4644999Sgblack@eecs.umich.edu 46510024Sdam.sunwoo@arm.com req->taskId(taskId()); 46611321Ssteve.reinhardt@amd.com while (1) { 4678832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4684999Sgblack@eecs.umich.edu 4694999Sgblack@eecs.umich.edu // translate to physical address 47011147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4714999Sgblack@eecs.umich.edu 4724999Sgblack@eecs.umich.edu // Now do the access. 4734999Sgblack@eecs.umich.edu if (fault == NoFault) { 4744999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4754999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4764999Sgblack@eecs.umich.edu 4776102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4784999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 47910030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4804999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4814999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4824999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4834999Sgblack@eecs.umich.edu assert(res); 4844999Sgblack@eecs.umich.edu req->setExtraData(*res); 4854999Sgblack@eecs.umich.edu } 4864999Sgblack@eecs.umich.edu } 4874999Sgblack@eecs.umich.edu 4886623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4898949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4907520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4914999Sgblack@eecs.umich.edu 4928105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4934999Sgblack@eecs.umich.edu dcache_latency += 4944999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4954999Sgblack@eecs.umich.edu } else { 4968931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4978931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4984999Sgblack@eecs.umich.edu else 4994999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 50011148Smitch.hayenga@arm.com 50111148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 50211148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 5034999Sgblack@eecs.umich.edu } 5044999Sgblack@eecs.umich.edu dcache_access = true; 5054999Sgblack@eecs.umich.edu assert(!pkt.isError()); 5064999Sgblack@eecs.umich.edu 5074999Sgblack@eecs.umich.edu if (req->isSwap()) { 5084999Sgblack@eecs.umich.edu assert(res); 50910563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 5104999Sgblack@eecs.umich.edu } 5114999Sgblack@eecs.umich.edu } 5124999Sgblack@eecs.umich.edu 5134999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5144999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5154878Sstever@eecs.umich.edu } 5164040Ssaidi@eecs.umich.edu } 5174040Ssaidi@eecs.umich.edu 5184999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5194999Sgblack@eecs.umich.edu //stop now. 5204999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5214999Sgblack@eecs.umich.edu { 52210760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5236078Sgblack@eecs.umich.edu assert(locked); 5246078Sgblack@eecs.umich.edu locked = false; 5256078Sgblack@eecs.umich.edu } 52611147Smitch.hayenga@arm.com 52711147Smitch.hayenga@arm.com 5286739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5296739Sgblack@eecs.umich.edu return NoFault; 5306739Sgblack@eecs.umich.edu } else { 5316739Sgblack@eecs.umich.edu return fault; 5326739Sgblack@eecs.umich.edu } 5333170Sstever@eecs.umich.edu } 5343170Sstever@eecs.umich.edu 5354999Sgblack@eecs.umich.edu /* 5364999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5374999Sgblack@eecs.umich.edu */ 5384999Sgblack@eecs.umich.edu 5394999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5407520Sgblack@eecs.umich.edu data += size; 5414999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5427520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5434999Sgblack@eecs.umich.edu //And access the right address. 5444999Sgblack@eecs.umich.edu addr = secondAddr; 5452623SN/A } 5462623SN/A} 5472623SN/A 5482623SN/A 5492623SN/Avoid 5502623SN/AAtomicSimpleCPU::tick() 5512623SN/A{ 5524940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5534940Snate@binkert.org 55411147Smitch.hayenga@arm.com // Change thread if multi-threaded 55511147Smitch.hayenga@arm.com swapActiveThread(); 55611147Smitch.hayenga@arm.com 55711147Smitch.hayenga@arm.com // Set memroy request ids to current thread 55811147Smitch.hayenga@arm.com if (numThreads > 1) { 55911148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 56011148Smitch.hayenga@arm.com 56111435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 56211435Smitch.hayenga@arm.com data_read_req.setContext(cid); 56311435Smitch.hayenga@arm.com data_write_req.setContext(cid); 56411147Smitch.hayenga@arm.com } 56511147Smitch.hayenga@arm.com 56611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 56711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 56811147Smitch.hayenga@arm.com 5695487Snate@binkert.org Tick latency = 0; 5702623SN/A 5716078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5722623SN/A numCycles++; 57310464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5742623SN/A 57510596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5763387Sgblack@eecs.umich.edu checkForInterrupts(); 57710596Sgabeblack@google.com checkPcEventQueue(); 57810596Sgabeblack@google.com } 5792626SN/A 5808143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5819443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5829443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5838143SAli.Saidi@ARM.com return; 5849443SAndreas.Sandberg@ARM.com } 5855348Ssaidi@eecs.umich.edu 5865669Sgblack@eecs.umich.edu Fault fault = NoFault; 5875669Sgblack@eecs.umich.edu 5887720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5897720Sgblack@eecs.umich.edu 5907720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5917720Sgblack@eecs.umich.edu !curMacroStaticInst; 5927720Sgblack@eecs.umich.edu if (needToFetch) { 59310024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5945894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 59511147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5966023Snate@binkert.org BaseTLB::Execute); 5975894Sgblack@eecs.umich.edu } 5982623SN/A 5992623SN/A if (fault == NoFault) { 6004182Sgblack@eecs.umich.edu Tick icache_latency = 0; 6014182Sgblack@eecs.umich.edu bool icache_access = false; 6024182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 6032662Sstever@eecs.umich.edu 6047720Sgblack@eecs.umich.edu if (needToFetch) { 6059023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 6065694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 6075694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 6085694Sgblack@eecs.umich.edu // this code should be uncommented. 6095669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 61011321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 6115669Sgblack@eecs.umich.edu //{ 6125669Sgblack@eecs.umich.edu icache_access = true; 6138949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6145669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6152623SN/A 6168931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6178931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6185669Sgblack@eecs.umich.edu else 6195669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6204968Sacolyte@umich.edu 6215669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6224968Sacolyte@umich.edu 6235669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6245669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6255669Sgblack@eecs.umich.edu //} 6265669Sgblack@eecs.umich.edu } 6274182Sgblack@eecs.umich.edu 6282623SN/A preExecute(); 6293814Ssaidi@eecs.umich.edu 6305001Sgblack@eecs.umich.edu if (curStaticInst) { 63111147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6324998Sgblack@eecs.umich.edu 6334998Sgblack@eecs.umich.edu // keep an instruction count 63410381Sdam.sunwoo@arm.com if (fault == NoFault) { 6354998Sgblack@eecs.umich.edu countInst(); 63610651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 63710381Sdam.sunwoo@arm.com } 6387655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6395001Sgblack@eecs.umich.edu delete traceData; 6405001Sgblack@eecs.umich.edu traceData = NULL; 6415001Sgblack@eecs.umich.edu } 6424998Sgblack@eecs.umich.edu 6434182Sgblack@eecs.umich.edu postExecute(); 6444182Sgblack@eecs.umich.edu } 6452623SN/A 6463814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6474539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6484539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6493814Ssaidi@eecs.umich.edu instCnt++; 6503814Ssaidi@eecs.umich.edu 6515487Snate@binkert.org Tick stall_ticks = 0; 6525487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6535487Snate@binkert.org stall_ticks += icache_latency; 6545487Snate@binkert.org 6555487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6565487Snate@binkert.org stall_ticks += dcache_latency; 6575487Snate@binkert.org 6585487Snate@binkert.org if (stall_ticks) { 6599180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6609180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6619180Sandreas.hansson@arm.com // period 6629180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6639180Sandreas.hansson@arm.com clockPeriod(); 6642623SN/A } 6652623SN/A 6662623SN/A } 66711321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6684182Sgblack@eecs.umich.edu advancePC(fault); 6692623SN/A } 6702623SN/A 6719443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6729443SAndreas.Sandberg@ARM.com return; 6739443SAndreas.Sandberg@ARM.com 6745487Snate@binkert.org // instruction takes at least one cycle 6759179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6769179Sandreas.hansson@arm.com latency = clockPeriod(); 6775487Snate@binkert.org 6782626SN/A if (_status != Idle) 67911147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6802623SN/A} 6812623SN/A 68210381Sdam.sunwoo@arm.comvoid 68310381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 68410381Sdam.sunwoo@arm.com{ 68510464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68610464SAndreas.Sandberg@ARM.com 68710381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68810381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68910381Sdam.sunwoo@arm.com} 6902623SN/A 6915315Sstever@gmail.comvoid 6925315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6935315Sstever@gmail.com{ 6945315Sstever@gmail.com dcachePort.printAddr(a); 6955315Sstever@gmail.com} 6965315Sstever@gmail.com 6972623SN/A//////////////////////////////////////////////////////////////////////// 6982623SN/A// 6992623SN/A// AtomicSimpleCPU Simulation Object 7002623SN/A// 7014762Snate@binkert.orgAtomicSimpleCPU * 7024762Snate@binkert.orgAtomicSimpleCPUParams::create() 7032623SN/A{ 7045529Snate@binkert.org return new AtomicSimpleCPU(this); 7052623SN/A} 706