atomic.cc revision 11356
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 489647Sdam.sunwoo@arm.com#include "base/output.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 508229Snate@binkert.org#include "cpu/simple/atomic.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 675606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 682623SN/A{ 692623SN/A} 702623SN/A 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::TickEvent::process() 742623SN/A{ 752623SN/A cpu->tick(); 762623SN/A} 772623SN/A 782623SN/Aconst char * 795336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 802623SN/A{ 814873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/AAtomicSimpleCPU::init() 862623SN/A{ 8711147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 888921Sandreas.hansson@arm.com 8911148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 9011148Smitch.hayenga@arm.com ifetch_req.setThreadContext(cid, 0); 9111148Smitch.hayenga@arm.com data_read_req.setThreadContext(cid, 0); 9211148Smitch.hayenga@arm.com data_write_req.setThreadContext(cid, 0); 932623SN/A} 942623SN/A 955529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 966078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 975487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 985487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 999095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1009095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 10110537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 10210537Sandreas.hansson@arm.com ppCommit(nullptr) 1032623SN/A{ 1042623SN/A _status = Idle; 1052623SN/A} 1062623SN/A 1072623SN/A 1082623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1092623SN/A{ 1106775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1116775SBrad.Beckmann@amd.com deschedule(tickEvent); 1126775SBrad.Beckmann@amd.com } 1132623SN/A} 1142623SN/A 11510913Sandreas.sandberg@arm.comDrainState 11610913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1172623SN/A{ 1189448SAndreas.Sandberg@ARM.com if (switchedOut()) 11910913Sandreas.sandberg@arm.com return DrainState::Drained; 1202623SN/A 1219443SAndreas.Sandberg@ARM.com if (!isDrained()) { 12211147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 12310913Sandreas.sandberg@arm.com return DrainState::Draining; 1249443SAndreas.Sandberg@ARM.com } else { 1259443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1269443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1272915Sktlim@umich.edu 12811147Smitch.hayenga@arm.com activeThreads.clear(); 1299443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 13010913Sandreas.sandberg@arm.com return DrainState::Drained; 1319443SAndreas.Sandberg@ARM.com } 1329342SAndreas.Sandberg@arm.com} 1339342SAndreas.Sandberg@arm.com 1342915Sktlim@umich.eduvoid 13511148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 13611148Smitch.hayenga@arm.com{ 13711148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 13811148Smitch.hayenga@arm.com pkt->cmdString()); 13911148Smitch.hayenga@arm.com 14011148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 14111148Smitch.hayenga@arm.com if (tid != sender) { 14211321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 14311151Smitch.hayenga@arm.com wakeup(tid); 14411148Smitch.hayenga@arm.com } 14511148Smitch.hayenga@arm.com 14611148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 14711148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 14811148Smitch.hayenga@arm.com } 14911148Smitch.hayenga@arm.com } 15011148Smitch.hayenga@arm.com} 15111148Smitch.hayenga@arm.com 15211148Smitch.hayenga@arm.comvoid 1539342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1542915Sktlim@umich.edu{ 1559448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1569448SAndreas.Sandberg@ARM.com if (switchedOut()) 1575220Ssaidi@eecs.umich.edu return; 1585220Ssaidi@eecs.umich.edu 1594940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1609523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1613324Shsul@eecs.umich.edu 1629448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1639448SAndreas.Sandberg@ARM.com 16411147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 16711147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 16811147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 16911147Smitch.hayenga@arm.com activeThreads.push_back(tid); 17011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 17111147Smitch.hayenga@arm.com 17211147Smitch.hayenga@arm.com // Tick if any threads active 17311147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 17411147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 17511147Smitch.hayenga@arm.com } 17611147Smitch.hayenga@arm.com } else { 17711147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 17811147Smitch.hayenga@arm.com } 1799448SAndreas.Sandberg@ARM.com } 1802623SN/A} 1812623SN/A 1829443SAndreas.Sandberg@ARM.combool 1839443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1849443SAndreas.Sandberg@ARM.com{ 18510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1869443SAndreas.Sandberg@ARM.com return false; 1879443SAndreas.Sandberg@ARM.com 18811147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1899443SAndreas.Sandberg@ARM.com if (!isDrained()) 1909443SAndreas.Sandberg@ARM.com return false; 1919443SAndreas.Sandberg@ARM.com 1929443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 19310913Sandreas.sandberg@arm.com signalDrainDone(); 1949443SAndreas.Sandberg@ARM.com 1959443SAndreas.Sandberg@ARM.com return true; 1969443SAndreas.Sandberg@ARM.com} 1979443SAndreas.Sandberg@ARM.com 1989443SAndreas.Sandberg@ARM.com 1992623SN/Avoid 2002798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2012623SN/A{ 2029429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 2039429SAndreas.Sandberg@ARM.com 2049443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 2059342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2069443SAndreas.Sandberg@ARM.com assert(isDrained()); 2072623SN/A} 2082623SN/A 2092623SN/A 2102623SN/Avoid 2112623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2122623SN/A{ 2139429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2142623SN/A 2159443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2162623SN/A assert(!tickEvent.scheduled()); 2172623SN/A} 2182623SN/A 2199523SAndreas.Sandberg@ARM.comvoid 2209523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2219523SAndreas.Sandberg@ARM.com{ 2229524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2239523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2249523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2259523SAndreas.Sandberg@ARM.com } 2269523SAndreas.Sandberg@ARM.com} 2272623SN/A 2282623SN/Avoid 22910407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2302623SN/A{ 23110407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2324940Snate@binkert.org 23311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2342623SN/A 23511147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 23611147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 23711147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 23810464SAndreas.Sandberg@ARM.com numCycles += delta; 23910464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2403686Sktlim@umich.edu 24111147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 24211147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 24311147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 24411147Smitch.hayenga@arm.com } 2459342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 24611147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 24711147Smitch.hayenga@arm.com == activeThreads.end()) { 24811147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 24911147Smitch.hayenga@arm.com } 2502623SN/A} 2512623SN/A 2522623SN/A 2532623SN/Avoid 2548737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2552623SN/A{ 2564940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2574940Snate@binkert.org 25811147Smitch.hayenga@arm.com assert(thread_num < numThreads); 25911147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2602623SN/A 2616043Sgblack@eecs.umich.edu if (_status == Idle) 2626043Sgblack@eecs.umich.edu return; 2636043Sgblack@eecs.umich.edu 2649342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2652626SN/A 26611147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2672623SN/A 26811147Smitch.hayenga@arm.com if (activeThreads.empty()) { 26911147Smitch.hayenga@arm.com _status = Idle; 27011147Smitch.hayenga@arm.com 27111147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 27211147Smitch.hayenga@arm.com deschedule(tickEvent); 27311147Smitch.hayenga@arm.com } 27411147Smitch.hayenga@arm.com } 27511147Smitch.hayenga@arm.com 2762623SN/A} 2772623SN/A 2782623SN/A 27910030SAli.Saidi@ARM.comTick 28010030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 28110030SAli.Saidi@ARM.com{ 28210030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 28310030SAli.Saidi@ARM.com pkt->cmdString()); 28410030SAli.Saidi@ARM.com 28510529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 28610529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 28711148Smitch.hayenga@arm.com 28811148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 28911148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 29011151Smitch.hayenga@arm.com cpu->wakeup(tid); 29111148Smitch.hayenga@arm.com } 29210529Smorr@cs.wisc.edu } 29310529Smorr@cs.wisc.edu 29410030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29511356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 29611356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 29711356Skrinat01@arm.com // the processor accordingly 29811356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 29910030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30010030SAli.Saidi@ARM.com pkt->getAddr()); 30111147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 30211147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 30311147Smitch.hayenga@arm.com } 30410030SAli.Saidi@ARM.com } 30510030SAli.Saidi@ARM.com 30610030SAli.Saidi@ARM.com return 0; 30710030SAli.Saidi@ARM.com} 30810030SAli.Saidi@ARM.com 30910030SAli.Saidi@ARM.comvoid 31010030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 31110030SAli.Saidi@ARM.com{ 31210030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 31310030SAli.Saidi@ARM.com pkt->cmdString()); 31410030SAli.Saidi@ARM.com 31510529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 31610529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 31711148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 31811321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 31911151Smitch.hayenga@arm.com cpu->wakeup(tid); 32011148Smitch.hayenga@arm.com } 32110529Smorr@cs.wisc.edu } 32210529Smorr@cs.wisc.edu 32310030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 32410030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 32510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 32610030SAli.Saidi@ARM.com pkt->getAddr()); 32711147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 32811147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 32911147Smitch.hayenga@arm.com } 33010030SAli.Saidi@ARM.com } 33110030SAli.Saidi@ARM.com} 33210030SAli.Saidi@ARM.com 3332623SN/AFault 3348444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3358444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3362623SN/A{ 33711147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 33811147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 33911147Smitch.hayenga@arm.com 3403169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3414870Sstever@eecs.umich.edu Request *req = &data_read_req; 3422623SN/A 34310665SAli.Saidi@ARM.com if (traceData) 34410665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3452623SN/A 3464999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3477520Sgblack@eecs.umich.edu int fullSize = size; 3482623SN/A 3494999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3504999Sgblack@eecs.umich.edu //across a cache line boundary. 3519814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3524999Sgblack@eecs.umich.edu 3537520Sgblack@eecs.umich.edu if (secondAddr > addr) 3547520Sgblack@eecs.umich.edu size = secondAddr - addr; 3554999Sgblack@eecs.umich.edu 3564999Sgblack@eecs.umich.edu dcache_latency = 0; 3574999Sgblack@eecs.umich.edu 35810024Sdam.sunwoo@arm.com req->taskId(taskId()); 3597520Sgblack@eecs.umich.edu while (1) { 3608832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3614999Sgblack@eecs.umich.edu 3624999Sgblack@eecs.umich.edu // translate to physical address 36311147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 36411147Smitch.hayenga@arm.com BaseTLB::Read); 3654999Sgblack@eecs.umich.edu 3664999Sgblack@eecs.umich.edu // Now do the access. 3676623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 36810739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3697520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3704999Sgblack@eecs.umich.edu 3718105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3724999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3734999Sgblack@eecs.umich.edu else { 3748931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3758931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3764999Sgblack@eecs.umich.edu else 3774999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3784999Sgblack@eecs.umich.edu } 3794999Sgblack@eecs.umich.edu dcache_access = true; 3805012Sgblack@eecs.umich.edu 3814999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3824999Sgblack@eecs.umich.edu 3836102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3844999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3854999Sgblack@eecs.umich.edu } 3864968Sacolyte@umich.edu } 3874986Ssaidi@eecs.umich.edu 3884999Sgblack@eecs.umich.edu //If there's a fault, return it 3896739Sgblack@eecs.umich.edu if (fault != NoFault) { 3906739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3916739Sgblack@eecs.umich.edu return NoFault; 3926739Sgblack@eecs.umich.edu } else { 3936739Sgblack@eecs.umich.edu return fault; 3946739Sgblack@eecs.umich.edu } 3956739Sgblack@eecs.umich.edu } 3966739Sgblack@eecs.umich.edu 3974999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3984999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3994999Sgblack@eecs.umich.edu { 40010760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 4016078Sgblack@eecs.umich.edu assert(!locked); 4026078Sgblack@eecs.umich.edu locked = true; 4036078Sgblack@eecs.umich.edu } 40411147Smitch.hayenga@arm.com 4054999Sgblack@eecs.umich.edu return fault; 4064968Sacolyte@umich.edu } 4073170Sstever@eecs.umich.edu 4084999Sgblack@eecs.umich.edu /* 4094999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4104999Sgblack@eecs.umich.edu */ 4114999Sgblack@eecs.umich.edu 4124999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4137520Sgblack@eecs.umich.edu data += size; 4144999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4157520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4164999Sgblack@eecs.umich.edu //And access the right address. 4174999Sgblack@eecs.umich.edu addr = secondAddr; 4182623SN/A } 4192623SN/A} 4202623SN/A 42111303Ssteve.reinhardt@amd.comFault 42211303Ssteve.reinhardt@amd.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 42311303Ssteve.reinhardt@amd.com{ 42411303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 42511303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 42611303Ssteve.reinhardt@amd.com} 4277520Sgblack@eecs.umich.edu 4282623SN/AFault 4298444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 4308444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4312623SN/A{ 43211147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 43311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43410031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 43510031SAli.Saidi@ARM.com 43610031SAli.Saidi@ARM.com if (data == NULL) { 43710031SAli.Saidi@ARM.com assert(size <= 64); 43810031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 43910031SAli.Saidi@ARM.com // This must be a cache block cleaning request 44010031SAli.Saidi@ARM.com data = zero_array; 44110031SAli.Saidi@ARM.com } 44210031SAli.Saidi@ARM.com 4433169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4444870Sstever@eecs.umich.edu Request *req = &data_write_req; 4452623SN/A 44610665SAli.Saidi@ARM.com if (traceData) 44710665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4482623SN/A 4494999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4507520Sgblack@eecs.umich.edu int fullSize = size; 4512623SN/A 4524999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4534999Sgblack@eecs.umich.edu //across a cache line boundary. 4549814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4554999Sgblack@eecs.umich.edu 45611321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4577520Sgblack@eecs.umich.edu size = secondAddr - addr; 4584999Sgblack@eecs.umich.edu 4594999Sgblack@eecs.umich.edu dcache_latency = 0; 4604999Sgblack@eecs.umich.edu 46110024Sdam.sunwoo@arm.com req->taskId(taskId()); 46211321Ssteve.reinhardt@amd.com while (1) { 4638832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4644999Sgblack@eecs.umich.edu 4654999Sgblack@eecs.umich.edu // translate to physical address 46611147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4674999Sgblack@eecs.umich.edu 4684999Sgblack@eecs.umich.edu // Now do the access. 4694999Sgblack@eecs.umich.edu if (fault == NoFault) { 4704999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4714999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4724999Sgblack@eecs.umich.edu 4736102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4744999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 47510030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4764999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4774999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4784999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4794999Sgblack@eecs.umich.edu assert(res); 4804999Sgblack@eecs.umich.edu req->setExtraData(*res); 4814999Sgblack@eecs.umich.edu } 4824999Sgblack@eecs.umich.edu } 4834999Sgblack@eecs.umich.edu 4846623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4858949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4867520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4874999Sgblack@eecs.umich.edu 4888105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4894999Sgblack@eecs.umich.edu dcache_latency += 4904999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4914999Sgblack@eecs.umich.edu } else { 4928931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4938931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4944999Sgblack@eecs.umich.edu else 4954999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 49611148Smitch.hayenga@arm.com 49711148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 49811148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 4994999Sgblack@eecs.umich.edu } 5004999Sgblack@eecs.umich.edu dcache_access = true; 5014999Sgblack@eecs.umich.edu assert(!pkt.isError()); 5024999Sgblack@eecs.umich.edu 5034999Sgblack@eecs.umich.edu if (req->isSwap()) { 5044999Sgblack@eecs.umich.edu assert(res); 50510563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 5064999Sgblack@eecs.umich.edu } 5074999Sgblack@eecs.umich.edu } 5084999Sgblack@eecs.umich.edu 5094999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5104999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5114878Sstever@eecs.umich.edu } 5124040Ssaidi@eecs.umich.edu } 5134040Ssaidi@eecs.umich.edu 5144999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5154999Sgblack@eecs.umich.edu //stop now. 5164999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5174999Sgblack@eecs.umich.edu { 51810760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5196078Sgblack@eecs.umich.edu assert(locked); 5206078Sgblack@eecs.umich.edu locked = false; 5216078Sgblack@eecs.umich.edu } 52211147Smitch.hayenga@arm.com 52311147Smitch.hayenga@arm.com 5246739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5256739Sgblack@eecs.umich.edu return NoFault; 5266739Sgblack@eecs.umich.edu } else { 5276739Sgblack@eecs.umich.edu return fault; 5286739Sgblack@eecs.umich.edu } 5293170Sstever@eecs.umich.edu } 5303170Sstever@eecs.umich.edu 5314999Sgblack@eecs.umich.edu /* 5324999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5334999Sgblack@eecs.umich.edu */ 5344999Sgblack@eecs.umich.edu 5354999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5367520Sgblack@eecs.umich.edu data += size; 5374999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5387520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5394999Sgblack@eecs.umich.edu //And access the right address. 5404999Sgblack@eecs.umich.edu addr = secondAddr; 5412623SN/A } 5422623SN/A} 5432623SN/A 5442623SN/A 5452623SN/Avoid 5462623SN/AAtomicSimpleCPU::tick() 5472623SN/A{ 5484940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5494940Snate@binkert.org 55011147Smitch.hayenga@arm.com // Change thread if multi-threaded 55111147Smitch.hayenga@arm.com swapActiveThread(); 55211147Smitch.hayenga@arm.com 55311147Smitch.hayenga@arm.com // Set memroy request ids to current thread 55411147Smitch.hayenga@arm.com if (numThreads > 1) { 55511148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 55611148Smitch.hayenga@arm.com 55711148Smitch.hayenga@arm.com ifetch_req.setThreadContext(cid, curThread); 55811148Smitch.hayenga@arm.com data_read_req.setThreadContext(cid, curThread); 55911148Smitch.hayenga@arm.com data_write_req.setThreadContext(cid, curThread); 56011147Smitch.hayenga@arm.com } 56111147Smitch.hayenga@arm.com 56211147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 56311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 56411147Smitch.hayenga@arm.com 5655487Snate@binkert.org Tick latency = 0; 5662623SN/A 5676078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5682623SN/A numCycles++; 56910464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5702623SN/A 57110596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5723387Sgblack@eecs.umich.edu checkForInterrupts(); 57310596Sgabeblack@google.com checkPcEventQueue(); 57410596Sgabeblack@google.com } 5752626SN/A 5768143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5779443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5789443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5798143SAli.Saidi@ARM.com return; 5809443SAndreas.Sandberg@ARM.com } 5815348Ssaidi@eecs.umich.edu 5825669Sgblack@eecs.umich.edu Fault fault = NoFault; 5835669Sgblack@eecs.umich.edu 5847720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5857720Sgblack@eecs.umich.edu 5867720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5877720Sgblack@eecs.umich.edu !curMacroStaticInst; 5887720Sgblack@eecs.umich.edu if (needToFetch) { 58910024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5905894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 59111147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5926023Snate@binkert.org BaseTLB::Execute); 5935894Sgblack@eecs.umich.edu } 5942623SN/A 5952623SN/A if (fault == NoFault) { 5964182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5974182Sgblack@eecs.umich.edu bool icache_access = false; 5984182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5992662Sstever@eecs.umich.edu 6007720Sgblack@eecs.umich.edu if (needToFetch) { 6019023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 6025694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 6035694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 6045694Sgblack@eecs.umich.edu // this code should be uncommented. 6055669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 60611321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 6075669Sgblack@eecs.umich.edu //{ 6085669Sgblack@eecs.umich.edu icache_access = true; 6098949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6105669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6112623SN/A 6128931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6138931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6145669Sgblack@eecs.umich.edu else 6155669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6164968Sacolyte@umich.edu 6175669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6184968Sacolyte@umich.edu 6195669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6205669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6215669Sgblack@eecs.umich.edu //} 6225669Sgblack@eecs.umich.edu } 6234182Sgblack@eecs.umich.edu 6242623SN/A preExecute(); 6253814Ssaidi@eecs.umich.edu 6265001Sgblack@eecs.umich.edu if (curStaticInst) { 62711147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6284998Sgblack@eecs.umich.edu 6294998Sgblack@eecs.umich.edu // keep an instruction count 63010381Sdam.sunwoo@arm.com if (fault == NoFault) { 6314998Sgblack@eecs.umich.edu countInst(); 63210651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 63310381Sdam.sunwoo@arm.com } 6347655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6355001Sgblack@eecs.umich.edu delete traceData; 6365001Sgblack@eecs.umich.edu traceData = NULL; 6375001Sgblack@eecs.umich.edu } 6384998Sgblack@eecs.umich.edu 6394182Sgblack@eecs.umich.edu postExecute(); 6404182Sgblack@eecs.umich.edu } 6412623SN/A 6423814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6434539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6444539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6453814Ssaidi@eecs.umich.edu instCnt++; 6463814Ssaidi@eecs.umich.edu 6475487Snate@binkert.org Tick stall_ticks = 0; 6485487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6495487Snate@binkert.org stall_ticks += icache_latency; 6505487Snate@binkert.org 6515487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6525487Snate@binkert.org stall_ticks += dcache_latency; 6535487Snate@binkert.org 6545487Snate@binkert.org if (stall_ticks) { 6559180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6569180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6579180Sandreas.hansson@arm.com // period 6589180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6599180Sandreas.hansson@arm.com clockPeriod(); 6602623SN/A } 6612623SN/A 6622623SN/A } 66311321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6644182Sgblack@eecs.umich.edu advancePC(fault); 6652623SN/A } 6662623SN/A 6679443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6689443SAndreas.Sandberg@ARM.com return; 6699443SAndreas.Sandberg@ARM.com 6705487Snate@binkert.org // instruction takes at least one cycle 6719179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6729179Sandreas.hansson@arm.com latency = clockPeriod(); 6735487Snate@binkert.org 6742626SN/A if (_status != Idle) 67511147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6762623SN/A} 6772623SN/A 67810381Sdam.sunwoo@arm.comvoid 67910381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 68010381Sdam.sunwoo@arm.com{ 68110464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68210464SAndreas.Sandberg@ARM.com 68310381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68410381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68510381Sdam.sunwoo@arm.com} 6862623SN/A 6875315Sstever@gmail.comvoid 6885315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6895315Sstever@gmail.com{ 6905315Sstever@gmail.com dcachePort.printAddr(a); 6915315Sstever@gmail.com} 6925315Sstever@gmail.com 6932623SN/A//////////////////////////////////////////////////////////////////////// 6942623SN/A// 6952623SN/A// AtomicSimpleCPU Simulation Object 6962623SN/A// 6974762Snate@binkert.orgAtomicSimpleCPU * 6984762Snate@binkert.orgAtomicSimpleCPUParams::create() 6992623SN/A{ 7005529Snate@binkert.org return new AtomicSimpleCPU(this); 7012623SN/A} 702