atomic.cc revision 10760
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 489647Sdam.sunwoo@arm.com#include "base/output.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 508229Snate@binkert.org#include "cpu/simple/atomic.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 675606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 682623SN/A{ 692623SN/A} 702623SN/A 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::TickEvent::process() 742623SN/A{ 752623SN/A cpu->tick(); 762623SN/A} 772623SN/A 782623SN/Aconst char * 795336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 802623SN/A{ 814873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/AAtomicSimpleCPU::init() 862623SN/A{ 872623SN/A BaseCPU::init(); 888921Sandreas.hansson@arm.com 898921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 908921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 918921Sandreas.hansson@arm.com 929433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 938779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 948779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 958779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 968779Sgblack@eecs.umich.edu // initialize CPU, including PC 978779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 988779Sgblack@eecs.umich.edu } 992623SN/A } 1008706Sandreas.hansson@arm.com 1015714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1025712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1035712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1045712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1052623SN/A} 1062623SN/A 1075529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1086078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1095487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1105487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1119443SAndreas.Sandberg@ARM.com drain_manager(NULL), 1129095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1139095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 11410537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 11510537Sandreas.hansson@arm.com ppCommit(nullptr) 1162623SN/A{ 1172623SN/A _status = Idle; 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1222623SN/A{ 1236775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1246775SBrad.Beckmann@amd.com deschedule(tickEvent); 1256775SBrad.Beckmann@amd.com } 1262623SN/A} 1272623SN/A 1289443SAndreas.Sandberg@ARM.comunsigned int 1299443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::drain(DrainManager *dm) 1302623SN/A{ 1319443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1329448SAndreas.Sandberg@ARM.com if (switchedOut()) 1339443SAndreas.Sandberg@ARM.com return 0; 1342623SN/A 1359443SAndreas.Sandberg@ARM.com if (!isDrained()) { 1369443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1379443SAndreas.Sandberg@ARM.com drain_manager = dm; 1389443SAndreas.Sandberg@ARM.com return 1; 1399443SAndreas.Sandberg@ARM.com } else { 1409443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1419443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1422915Sktlim@umich.edu 1439443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 1449443SAndreas.Sandberg@ARM.com return 0; 1459443SAndreas.Sandberg@ARM.com } 1469342SAndreas.Sandberg@arm.com} 1479342SAndreas.Sandberg@arm.com 1482915Sktlim@umich.eduvoid 1499342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1502915Sktlim@umich.edu{ 1519448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1529443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1539448SAndreas.Sandberg@ARM.com if (switchedOut()) 1545220Ssaidi@eecs.umich.edu return; 1555220Ssaidi@eecs.umich.edu 1564940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1579523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1583324Shsul@eecs.umich.edu 1599448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1609448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1619448SAndreas.Sandberg@ARM.com fatal("The atomic CPU only supports one thread.\n"); 1629448SAndreas.Sandberg@ARM.com 1639448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1649443SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 1659448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1669837Slena@cs.wisc,edu notIdleFraction = 1; 1679448SAndreas.Sandberg@ARM.com } else { 1689448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1699837Slena@cs.wisc,edu notIdleFraction = 0; 1709448SAndreas.Sandberg@ARM.com } 1719443SAndreas.Sandberg@ARM.com 1727897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1732623SN/A} 1742623SN/A 1759443SAndreas.Sandberg@ARM.combool 1769443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1779443SAndreas.Sandberg@ARM.com{ 1789443SAndreas.Sandberg@ARM.com if (!drain_manager) 1799443SAndreas.Sandberg@ARM.com return false; 1809443SAndreas.Sandberg@ARM.com 1819443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1829443SAndreas.Sandberg@ARM.com if (!isDrained()) 1839443SAndreas.Sandberg@ARM.com return false; 1849443SAndreas.Sandberg@ARM.com 1859443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1869443SAndreas.Sandberg@ARM.com drain_manager->signalDrainDone(); 1879443SAndreas.Sandberg@ARM.com drain_manager = NULL; 1889443SAndreas.Sandberg@ARM.com 1899443SAndreas.Sandberg@ARM.com return true; 1909443SAndreas.Sandberg@ARM.com} 1919443SAndreas.Sandberg@ARM.com 1929443SAndreas.Sandberg@ARM.com 1932623SN/Avoid 1942798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1952623SN/A{ 1969429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1979429SAndreas.Sandberg@ARM.com 1989443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1999342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2009443SAndreas.Sandberg@ARM.com assert(isDrained()); 2012623SN/A} 2022623SN/A 2032623SN/A 2042623SN/Avoid 2052623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2062623SN/A{ 2079429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2082623SN/A 2099443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2102623SN/A assert(!tickEvent.scheduled()); 2112623SN/A 2125712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2135712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2145712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2152623SN/A} 2162623SN/A 2179523SAndreas.Sandberg@ARM.comvoid 2189523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2199523SAndreas.Sandberg@ARM.com{ 2209524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2219523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2229523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2239523SAndreas.Sandberg@ARM.com } 2249523SAndreas.Sandberg@ARM.com} 2252623SN/A 2262623SN/Avoid 22710407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2282623SN/A{ 22910407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2304940Snate@binkert.org 2312623SN/A assert(thread_num == 0); 2322683Sktlim@umich.edu assert(thread); 2332623SN/A 2342623SN/A assert(_status == Idle); 2352623SN/A assert(!tickEvent.scheduled()); 2362623SN/A 2379837Slena@cs.wisc,edu notIdleFraction = 1; 23810464SAndreas.Sandberg@ARM.com Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend); 23910464SAndreas.Sandberg@ARM.com numCycles += delta; 24010464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2413686Sktlim@umich.edu 2423430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 24310407Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 2449342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2498737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2502623SN/A{ 2514940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2524940Snate@binkert.org 2532623SN/A assert(thread_num == 0); 2542683Sktlim@umich.edu assert(thread); 2552623SN/A 2566043Sgblack@eecs.umich.edu if (_status == Idle) 2576043Sgblack@eecs.umich.edu return; 2586043Sgblack@eecs.umich.edu 2599342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2602626SN/A 2612626SN/A // tick event may not be scheduled if this gets called from inside 2622626SN/A // an instruction's execution, e.g. "quiesce" 2632626SN/A if (tickEvent.scheduled()) 2645606Snate@binkert.org deschedule(tickEvent); 2652623SN/A 2669837Slena@cs.wisc,edu notIdleFraction = 0; 2672623SN/A _status = Idle; 2682623SN/A} 2692623SN/A 2702623SN/A 27110030SAli.Saidi@ARM.comTick 27210030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27310030SAli.Saidi@ARM.com{ 27410030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27510030SAli.Saidi@ARM.com pkt->cmdString()); 27610030SAli.Saidi@ARM.com 27710529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 27810529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 27910529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 28010529Smorr@cs.wisc.edu cpu->wakeup(); 28110529Smorr@cs.wisc.edu } 28210529Smorr@cs.wisc.edu 28310030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 28410030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 28510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 28610030SAli.Saidi@ARM.com pkt->getAddr()); 28710030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 28810030SAli.Saidi@ARM.com } 28910030SAli.Saidi@ARM.com 29010030SAli.Saidi@ARM.com return 0; 29110030SAli.Saidi@ARM.com} 29210030SAli.Saidi@ARM.com 29310030SAli.Saidi@ARM.comvoid 29410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 29510030SAli.Saidi@ARM.com{ 29610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 29710030SAli.Saidi@ARM.com pkt->cmdString()); 29810030SAli.Saidi@ARM.com 29910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 30010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 30110529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 30210529Smorr@cs.wisc.edu cpu->wakeup(); 30310529Smorr@cs.wisc.edu } 30410529Smorr@cs.wisc.edu 30510030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 30610030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 30710030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30810030SAli.Saidi@ARM.com pkt->getAddr()); 30910030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 31010030SAli.Saidi@ARM.com } 31110030SAli.Saidi@ARM.com} 31210030SAli.Saidi@ARM.com 3132623SN/AFault 3148444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3158444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3162623SN/A{ 3173169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3184870Sstever@eecs.umich.edu Request *req = &data_read_req; 3192623SN/A 32010665SAli.Saidi@ARM.com if (traceData) 32110665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3222623SN/A 3234999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3247520Sgblack@eecs.umich.edu int fullSize = size; 3252623SN/A 3264999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3274999Sgblack@eecs.umich.edu //across a cache line boundary. 3289814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3294999Sgblack@eecs.umich.edu 3307520Sgblack@eecs.umich.edu if (secondAddr > addr) 3317520Sgblack@eecs.umich.edu size = secondAddr - addr; 3324999Sgblack@eecs.umich.edu 3334999Sgblack@eecs.umich.edu dcache_latency = 0; 3344999Sgblack@eecs.umich.edu 33510024Sdam.sunwoo@arm.com req->taskId(taskId()); 3367520Sgblack@eecs.umich.edu while (1) { 3378832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3384999Sgblack@eecs.umich.edu 3394999Sgblack@eecs.umich.edu // translate to physical address 3406023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3414999Sgblack@eecs.umich.edu 3424999Sgblack@eecs.umich.edu // Now do the access. 3436623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 34410739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3457520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3464999Sgblack@eecs.umich.edu 3478105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3484999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3494999Sgblack@eecs.umich.edu else { 3508931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3518931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3524999Sgblack@eecs.umich.edu else 3534999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3544999Sgblack@eecs.umich.edu } 3554999Sgblack@eecs.umich.edu dcache_access = true; 3565012Sgblack@eecs.umich.edu 3574999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3584999Sgblack@eecs.umich.edu 3596102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3604999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3614999Sgblack@eecs.umich.edu } 3624968Sacolyte@umich.edu } 3634986Ssaidi@eecs.umich.edu 3644999Sgblack@eecs.umich.edu //If there's a fault, return it 3656739Sgblack@eecs.umich.edu if (fault != NoFault) { 3666739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3676739Sgblack@eecs.umich.edu return NoFault; 3686739Sgblack@eecs.umich.edu } else { 3696739Sgblack@eecs.umich.edu return fault; 3706739Sgblack@eecs.umich.edu } 3716739Sgblack@eecs.umich.edu } 3726739Sgblack@eecs.umich.edu 3734999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3744999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3754999Sgblack@eecs.umich.edu { 37610760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3776078Sgblack@eecs.umich.edu assert(!locked); 3786078Sgblack@eecs.umich.edu locked = true; 3796078Sgblack@eecs.umich.edu } 3804999Sgblack@eecs.umich.edu return fault; 3814968Sacolyte@umich.edu } 3823170Sstever@eecs.umich.edu 3834999Sgblack@eecs.umich.edu /* 3844999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3854999Sgblack@eecs.umich.edu */ 3864999Sgblack@eecs.umich.edu 3874999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3887520Sgblack@eecs.umich.edu data += size; 3894999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3907520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3914999Sgblack@eecs.umich.edu //And access the right address. 3924999Sgblack@eecs.umich.edu addr = secondAddr; 3932623SN/A } 3942623SN/A} 3952623SN/A 3967520Sgblack@eecs.umich.edu 3972623SN/AFault 3988444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3998444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4002623SN/A{ 40110031SAli.Saidi@ARM.com 40210031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 40310031SAli.Saidi@ARM.com 40410031SAli.Saidi@ARM.com if (data == NULL) { 40510031SAli.Saidi@ARM.com assert(size <= 64); 40610031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 40710031SAli.Saidi@ARM.com // This must be a cache block cleaning request 40810031SAli.Saidi@ARM.com data = zero_array; 40910031SAli.Saidi@ARM.com } 41010031SAli.Saidi@ARM.com 4113169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4124870Sstever@eecs.umich.edu Request *req = &data_write_req; 4132623SN/A 41410665SAli.Saidi@ARM.com if (traceData) 41510665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4162623SN/A 4174999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4187520Sgblack@eecs.umich.edu int fullSize = size; 4192623SN/A 4204999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4214999Sgblack@eecs.umich.edu //across a cache line boundary. 4229814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4234999Sgblack@eecs.umich.edu 4244999Sgblack@eecs.umich.edu if(secondAddr > addr) 4257520Sgblack@eecs.umich.edu size = secondAddr - addr; 4264999Sgblack@eecs.umich.edu 4274999Sgblack@eecs.umich.edu dcache_latency = 0; 4284999Sgblack@eecs.umich.edu 42910024Sdam.sunwoo@arm.com req->taskId(taskId()); 4304999Sgblack@eecs.umich.edu while(1) { 4318832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4324999Sgblack@eecs.umich.edu 4334999Sgblack@eecs.umich.edu // translate to physical address 4346023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4354999Sgblack@eecs.umich.edu 4364999Sgblack@eecs.umich.edu // Now do the access. 4374999Sgblack@eecs.umich.edu if (fault == NoFault) { 4384999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4394999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4404999Sgblack@eecs.umich.edu 4416102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4424999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 44310030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4444999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4454999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4464999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4474999Sgblack@eecs.umich.edu assert(res); 4484999Sgblack@eecs.umich.edu req->setExtraData(*res); 4494999Sgblack@eecs.umich.edu } 4504999Sgblack@eecs.umich.edu } 4514999Sgblack@eecs.umich.edu 4526623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4538949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4547520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4554999Sgblack@eecs.umich.edu 4568105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4574999Sgblack@eecs.umich.edu dcache_latency += 4584999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4594999Sgblack@eecs.umich.edu } else { 4608931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4618931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4624999Sgblack@eecs.umich.edu else 4634999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4644999Sgblack@eecs.umich.edu } 4654999Sgblack@eecs.umich.edu dcache_access = true; 4664999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4674999Sgblack@eecs.umich.edu 4684999Sgblack@eecs.umich.edu if (req->isSwap()) { 4694999Sgblack@eecs.umich.edu assert(res); 47010563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 4714999Sgblack@eecs.umich.edu } 4724999Sgblack@eecs.umich.edu } 4734999Sgblack@eecs.umich.edu 4744999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4754999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4764878Sstever@eecs.umich.edu } 4774040Ssaidi@eecs.umich.edu } 4784040Ssaidi@eecs.umich.edu 4794999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4804999Sgblack@eecs.umich.edu //stop now. 4814999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4824999Sgblack@eecs.umich.edu { 48310760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 4846078Sgblack@eecs.umich.edu assert(locked); 4856078Sgblack@eecs.umich.edu locked = false; 4866078Sgblack@eecs.umich.edu } 4876739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4886739Sgblack@eecs.umich.edu return NoFault; 4896739Sgblack@eecs.umich.edu } else { 4906739Sgblack@eecs.umich.edu return fault; 4916739Sgblack@eecs.umich.edu } 4923170Sstever@eecs.umich.edu } 4933170Sstever@eecs.umich.edu 4944999Sgblack@eecs.umich.edu /* 4954999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4964999Sgblack@eecs.umich.edu */ 4974999Sgblack@eecs.umich.edu 4984999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4997520Sgblack@eecs.umich.edu data += size; 5004999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5017520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5024999Sgblack@eecs.umich.edu //And access the right address. 5034999Sgblack@eecs.umich.edu addr = secondAddr; 5042623SN/A } 5052623SN/A} 5062623SN/A 5072623SN/A 5082623SN/Avoid 5092623SN/AAtomicSimpleCPU::tick() 5102623SN/A{ 5114940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5124940Snate@binkert.org 5135487Snate@binkert.org Tick latency = 0; 5142623SN/A 5156078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5162623SN/A numCycles++; 51710464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5182623SN/A 51910596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5203387Sgblack@eecs.umich.edu checkForInterrupts(); 52110596Sgabeblack@google.com checkPcEventQueue(); 52210596Sgabeblack@google.com } 5232626SN/A 5248143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5259443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5269443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5278143SAli.Saidi@ARM.com return; 5289443SAndreas.Sandberg@ARM.com } 5295348Ssaidi@eecs.umich.edu 5305669Sgblack@eecs.umich.edu Fault fault = NoFault; 5315669Sgblack@eecs.umich.edu 5327720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5337720Sgblack@eecs.umich.edu 5347720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5357720Sgblack@eecs.umich.edu !curMacroStaticInst; 5367720Sgblack@eecs.umich.edu if (needToFetch) { 53710024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5385894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 5396023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 5406023Snate@binkert.org BaseTLB::Execute); 5415894Sgblack@eecs.umich.edu } 5422623SN/A 5432623SN/A if (fault == NoFault) { 5444182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5454182Sgblack@eecs.umich.edu bool icache_access = false; 5464182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5472662Sstever@eecs.umich.edu 5487720Sgblack@eecs.umich.edu if (needToFetch) { 5499023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5505694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5515694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5525694Sgblack@eecs.umich.edu // this code should be uncommented. 5535669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5549023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 5555669Sgblack@eecs.umich.edu //{ 5565669Sgblack@eecs.umich.edu icache_access = true; 5578949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 5585669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5592623SN/A 5608931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5618931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5625669Sgblack@eecs.umich.edu else 5635669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5644968Sacolyte@umich.edu 5655669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5664968Sacolyte@umich.edu 5675669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5685669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5695669Sgblack@eecs.umich.edu //} 5705669Sgblack@eecs.umich.edu } 5714182Sgblack@eecs.umich.edu 5722623SN/A preExecute(); 5733814Ssaidi@eecs.umich.edu 5745001Sgblack@eecs.umich.edu if (curStaticInst) { 5754182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5764998Sgblack@eecs.umich.edu 5774998Sgblack@eecs.umich.edu // keep an instruction count 57810381Sdam.sunwoo@arm.com if (fault == NoFault) { 5794998Sgblack@eecs.umich.edu countInst(); 58010651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 58110381Sdam.sunwoo@arm.com } 5827655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5835001Sgblack@eecs.umich.edu delete traceData; 5845001Sgblack@eecs.umich.edu traceData = NULL; 5855001Sgblack@eecs.umich.edu } 5864998Sgblack@eecs.umich.edu 5874182Sgblack@eecs.umich.edu postExecute(); 5884182Sgblack@eecs.umich.edu } 5892623SN/A 5903814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5914539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5924539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5933814Ssaidi@eecs.umich.edu instCnt++; 5943814Ssaidi@eecs.umich.edu 5955487Snate@binkert.org Tick stall_ticks = 0; 5965487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5975487Snate@binkert.org stall_ticks += icache_latency; 5985487Snate@binkert.org 5995487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6005487Snate@binkert.org stall_ticks += dcache_latency; 6015487Snate@binkert.org 6025487Snate@binkert.org if (stall_ticks) { 6039180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6049180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6059180Sandreas.hansson@arm.com // period 6069180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6079180Sandreas.hansson@arm.com clockPeriod(); 6082623SN/A } 6092623SN/A 6102623SN/A } 6114377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 6124182Sgblack@eecs.umich.edu advancePC(fault); 6132623SN/A } 6142623SN/A 6159443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6169443SAndreas.Sandberg@ARM.com return; 6179443SAndreas.Sandberg@ARM.com 6185487Snate@binkert.org // instruction takes at least one cycle 6199179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6209179Sandreas.hansson@arm.com latency = clockPeriod(); 6215487Snate@binkert.org 6222626SN/A if (_status != Idle) 6237823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 6242623SN/A} 6252623SN/A 62610381Sdam.sunwoo@arm.comvoid 62710381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 62810381Sdam.sunwoo@arm.com{ 62910464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 63010464SAndreas.Sandberg@ARM.com 63110381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 63210381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 63310381Sdam.sunwoo@arm.com} 6342623SN/A 6355315Sstever@gmail.comvoid 6365315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6375315Sstever@gmail.com{ 6385315Sstever@gmail.com dcachePort.printAddr(a); 6395315Sstever@gmail.com} 6405315Sstever@gmail.com 6412623SN/A//////////////////////////////////////////////////////////////////////// 6422623SN/A// 6432623SN/A// AtomicSimpleCPU Simulation Object 6442623SN/A// 6454762Snate@binkert.orgAtomicSimpleCPU * 6464762Snate@binkert.orgAtomicSimpleCPUParams::create() 6472623SN/A{ 6485529Snate@binkert.org numThreads = 1; 6498779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 6504762Snate@binkert.org panic("only one workload allowed"); 6515529Snate@binkert.org return new AtomicSimpleCPU(this); 6522623SN/A} 653