atomic.cc revision 10651
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 489647Sdam.sunwoo@arm.com#include "base/output.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 508229Snate@binkert.org#include "cpu/simple/atomic.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 675606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 682623SN/A{ 692623SN/A} 702623SN/A 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::TickEvent::process() 742623SN/A{ 752623SN/A cpu->tick(); 762623SN/A} 772623SN/A 782623SN/Aconst char * 795336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 802623SN/A{ 814873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/AAtomicSimpleCPU::init() 862623SN/A{ 872623SN/A BaseCPU::init(); 888921Sandreas.hansson@arm.com 898921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 908921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 918921Sandreas.hansson@arm.com 929433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 938779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 948779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 958779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 968779Sgblack@eecs.umich.edu // initialize CPU, including PC 978779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 988779Sgblack@eecs.umich.edu } 992623SN/A } 1008706Sandreas.hansson@arm.com 1015714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1025712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1035712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1045712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1052623SN/A} 1062623SN/A 1075529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1086078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1095487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1105487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1119443SAndreas.Sandberg@ARM.com drain_manager(NULL), 1129095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1139095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 11410537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 11510537Sandreas.hansson@arm.com ppCommit(nullptr) 1162623SN/A{ 1172623SN/A _status = Idle; 1182623SN/A} 1192623SN/A 1202623SN/A 1212623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1222623SN/A{ 1236775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1246775SBrad.Beckmann@amd.com deschedule(tickEvent); 1256775SBrad.Beckmann@amd.com } 1262623SN/A} 1272623SN/A 1289443SAndreas.Sandberg@ARM.comunsigned int 1299443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::drain(DrainManager *dm) 1302623SN/A{ 1319443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1329448SAndreas.Sandberg@ARM.com if (switchedOut()) 1339443SAndreas.Sandberg@ARM.com return 0; 1342623SN/A 1359443SAndreas.Sandberg@ARM.com if (!isDrained()) { 1369443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1379443SAndreas.Sandberg@ARM.com drain_manager = dm; 1389443SAndreas.Sandberg@ARM.com return 1; 1399443SAndreas.Sandberg@ARM.com } else { 1409443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1419443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1422915Sktlim@umich.edu 1439443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 1449443SAndreas.Sandberg@ARM.com return 0; 1459443SAndreas.Sandberg@ARM.com } 1469342SAndreas.Sandberg@arm.com} 1479342SAndreas.Sandberg@arm.com 1482915Sktlim@umich.eduvoid 1499342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1502915Sktlim@umich.edu{ 1519448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1529443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1539448SAndreas.Sandberg@ARM.com if (switchedOut()) 1545220Ssaidi@eecs.umich.edu return; 1555220Ssaidi@eecs.umich.edu 1564940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1579523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1583324Shsul@eecs.umich.edu 1599448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1609448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1619448SAndreas.Sandberg@ARM.com fatal("The atomic CPU only supports one thread.\n"); 1629448SAndreas.Sandberg@ARM.com 1639448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1649443SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 1659448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1669837Slena@cs.wisc,edu notIdleFraction = 1; 1679448SAndreas.Sandberg@ARM.com } else { 1689448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1699837Slena@cs.wisc,edu notIdleFraction = 0; 1709448SAndreas.Sandberg@ARM.com } 1719443SAndreas.Sandberg@ARM.com 1727897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1732623SN/A} 1742623SN/A 1759443SAndreas.Sandberg@ARM.combool 1769443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1779443SAndreas.Sandberg@ARM.com{ 1789443SAndreas.Sandberg@ARM.com if (!drain_manager) 1799443SAndreas.Sandberg@ARM.com return false; 1809443SAndreas.Sandberg@ARM.com 1819443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1829443SAndreas.Sandberg@ARM.com if (!isDrained()) 1839443SAndreas.Sandberg@ARM.com return false; 1849443SAndreas.Sandberg@ARM.com 1859443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1869443SAndreas.Sandberg@ARM.com drain_manager->signalDrainDone(); 1879443SAndreas.Sandberg@ARM.com drain_manager = NULL; 1889443SAndreas.Sandberg@ARM.com 1899443SAndreas.Sandberg@ARM.com return true; 1909443SAndreas.Sandberg@ARM.com} 1919443SAndreas.Sandberg@ARM.com 1929443SAndreas.Sandberg@ARM.com 1932623SN/Avoid 1942798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1952623SN/A{ 1969429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1979429SAndreas.Sandberg@ARM.com 1989443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1999342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2009443SAndreas.Sandberg@ARM.com assert(isDrained()); 2012623SN/A} 2022623SN/A 2032623SN/A 2042623SN/Avoid 2052623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2062623SN/A{ 2079429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2082623SN/A 2099443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2102623SN/A assert(!tickEvent.scheduled()); 2112623SN/A 2125712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2135712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2145712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2152623SN/A} 2162623SN/A 2179523SAndreas.Sandberg@ARM.comvoid 2189523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2199523SAndreas.Sandberg@ARM.com{ 2209524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2219523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2229523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2239523SAndreas.Sandberg@ARM.com } 2249523SAndreas.Sandberg@ARM.com} 2252623SN/A 2262623SN/Avoid 22710407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2282623SN/A{ 22910407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2304940Snate@binkert.org 2312623SN/A assert(thread_num == 0); 2322683Sktlim@umich.edu assert(thread); 2332623SN/A 2342623SN/A assert(_status == Idle); 2352623SN/A assert(!tickEvent.scheduled()); 2362623SN/A 2379837Slena@cs.wisc,edu notIdleFraction = 1; 23810464SAndreas.Sandberg@ARM.com Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend); 23910464SAndreas.Sandberg@ARM.com numCycles += delta; 24010464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2413686Sktlim@umich.edu 2423430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 24310407Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 2449342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2498737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2502623SN/A{ 2514940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2524940Snate@binkert.org 2532623SN/A assert(thread_num == 0); 2542683Sktlim@umich.edu assert(thread); 2552623SN/A 2566043Sgblack@eecs.umich.edu if (_status == Idle) 2576043Sgblack@eecs.umich.edu return; 2586043Sgblack@eecs.umich.edu 2599342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2602626SN/A 2612626SN/A // tick event may not be scheduled if this gets called from inside 2622626SN/A // an instruction's execution, e.g. "quiesce" 2632626SN/A if (tickEvent.scheduled()) 2645606Snate@binkert.org deschedule(tickEvent); 2652623SN/A 2669837Slena@cs.wisc,edu notIdleFraction = 0; 2672623SN/A _status = Idle; 2682623SN/A} 2692623SN/A 2702623SN/A 27110030SAli.Saidi@ARM.comTick 27210030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27310030SAli.Saidi@ARM.com{ 27410030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27510030SAli.Saidi@ARM.com pkt->cmdString()); 27610030SAli.Saidi@ARM.com 27710529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 27810529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 27910529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 28010529Smorr@cs.wisc.edu cpu->wakeup(); 28110529Smorr@cs.wisc.edu } 28210529Smorr@cs.wisc.edu 28310030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 28410030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 28510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 28610030SAli.Saidi@ARM.com pkt->getAddr()); 28710030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 28810030SAli.Saidi@ARM.com } 28910030SAli.Saidi@ARM.com 29010030SAli.Saidi@ARM.com return 0; 29110030SAli.Saidi@ARM.com} 29210030SAli.Saidi@ARM.com 29310030SAli.Saidi@ARM.comvoid 29410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 29510030SAli.Saidi@ARM.com{ 29610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 29710030SAli.Saidi@ARM.com pkt->cmdString()); 29810030SAli.Saidi@ARM.com 29910529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 30010529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 30110529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 30210529Smorr@cs.wisc.edu cpu->wakeup(); 30310529Smorr@cs.wisc.edu } 30410529Smorr@cs.wisc.edu 30510030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 30610030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 30710030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30810030SAli.Saidi@ARM.com pkt->getAddr()); 30910030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 31010030SAli.Saidi@ARM.com } 31110030SAli.Saidi@ARM.com} 31210030SAli.Saidi@ARM.com 3132623SN/AFault 3148444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3158444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3162623SN/A{ 3173169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3184870Sstever@eecs.umich.edu Request *req = &data_read_req; 3192623SN/A 3202623SN/A if (traceData) { 3212623SN/A traceData->setAddr(addr); 3222623SN/A } 3232623SN/A 3244999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3257520Sgblack@eecs.umich.edu int fullSize = size; 3262623SN/A 3274999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3284999Sgblack@eecs.umich.edu //across a cache line boundary. 3299814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3304999Sgblack@eecs.umich.edu 3317520Sgblack@eecs.umich.edu if (secondAddr > addr) 3327520Sgblack@eecs.umich.edu size = secondAddr - addr; 3334999Sgblack@eecs.umich.edu 3344999Sgblack@eecs.umich.edu dcache_latency = 0; 3354999Sgblack@eecs.umich.edu 33610024Sdam.sunwoo@arm.com req->taskId(taskId()); 3377520Sgblack@eecs.umich.edu while (1) { 3388832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3394999Sgblack@eecs.umich.edu 3404999Sgblack@eecs.umich.edu // translate to physical address 3416023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3424999Sgblack@eecs.umich.edu 3434999Sgblack@eecs.umich.edu // Now do the access. 3446623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 34510342SCurtis.Dunham@arm.com Packet pkt(req, MemCmd::ReadReq); 34610342SCurtis.Dunham@arm.com pkt.refineCommand(); 3477520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3484999Sgblack@eecs.umich.edu 3498105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3504999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3514999Sgblack@eecs.umich.edu else { 3528931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3538931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3544999Sgblack@eecs.umich.edu else 3554999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3564999Sgblack@eecs.umich.edu } 3574999Sgblack@eecs.umich.edu dcache_access = true; 3585012Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3604999Sgblack@eecs.umich.edu 3616102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3624999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3634999Sgblack@eecs.umich.edu } 3644968Sacolyte@umich.edu } 3654986Ssaidi@eecs.umich.edu 3664999Sgblack@eecs.umich.edu //If there's a fault, return it 3676739Sgblack@eecs.umich.edu if (fault != NoFault) { 3686739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3696739Sgblack@eecs.umich.edu return NoFault; 3706739Sgblack@eecs.umich.edu } else { 3716739Sgblack@eecs.umich.edu return fault; 3726739Sgblack@eecs.umich.edu } 3736739Sgblack@eecs.umich.edu } 3746739Sgblack@eecs.umich.edu 3754999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3764999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3774999Sgblack@eecs.umich.edu { 3786078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3796078Sgblack@eecs.umich.edu assert(!locked); 3806078Sgblack@eecs.umich.edu locked = true; 3816078Sgblack@eecs.umich.edu } 3824999Sgblack@eecs.umich.edu return fault; 3834968Sacolyte@umich.edu } 3843170Sstever@eecs.umich.edu 3854999Sgblack@eecs.umich.edu /* 3864999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3874999Sgblack@eecs.umich.edu */ 3884999Sgblack@eecs.umich.edu 3894999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3907520Sgblack@eecs.umich.edu data += size; 3914999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3927520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3934999Sgblack@eecs.umich.edu //And access the right address. 3944999Sgblack@eecs.umich.edu addr = secondAddr; 3952623SN/A } 3962623SN/A} 3972623SN/A 3987520Sgblack@eecs.umich.edu 3992623SN/AFault 4008444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 4018444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 4022623SN/A{ 40310031SAli.Saidi@ARM.com 40410031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 40510031SAli.Saidi@ARM.com 40610031SAli.Saidi@ARM.com if (data == NULL) { 40710031SAli.Saidi@ARM.com assert(size <= 64); 40810031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 40910031SAli.Saidi@ARM.com // This must be a cache block cleaning request 41010031SAli.Saidi@ARM.com data = zero_array; 41110031SAli.Saidi@ARM.com } 41210031SAli.Saidi@ARM.com 4133169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4144870Sstever@eecs.umich.edu Request *req = &data_write_req; 4152623SN/A 4162623SN/A if (traceData) { 4172623SN/A traceData->setAddr(addr); 4182623SN/A } 4192623SN/A 4204999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4217520Sgblack@eecs.umich.edu int fullSize = size; 4222623SN/A 4234999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4244999Sgblack@eecs.umich.edu //across a cache line boundary. 4259814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4264999Sgblack@eecs.umich.edu 4274999Sgblack@eecs.umich.edu if(secondAddr > addr) 4287520Sgblack@eecs.umich.edu size = secondAddr - addr; 4294999Sgblack@eecs.umich.edu 4304999Sgblack@eecs.umich.edu dcache_latency = 0; 4314999Sgblack@eecs.umich.edu 43210024Sdam.sunwoo@arm.com req->taskId(taskId()); 4334999Sgblack@eecs.umich.edu while(1) { 4348832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4354999Sgblack@eecs.umich.edu 4364999Sgblack@eecs.umich.edu // translate to physical address 4376023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4384999Sgblack@eecs.umich.edu 4394999Sgblack@eecs.umich.edu // Now do the access. 4404999Sgblack@eecs.umich.edu if (fault == NoFault) { 4414999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4424999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4434999Sgblack@eecs.umich.edu 4446102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4454999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 44610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4474999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4484999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4494999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4504999Sgblack@eecs.umich.edu assert(res); 4514999Sgblack@eecs.umich.edu req->setExtraData(*res); 4524999Sgblack@eecs.umich.edu } 4534999Sgblack@eecs.umich.edu } 4544999Sgblack@eecs.umich.edu 4556623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4568949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4577520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4584999Sgblack@eecs.umich.edu 4598105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4604999Sgblack@eecs.umich.edu dcache_latency += 4614999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4624999Sgblack@eecs.umich.edu } else { 4638931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4648931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4654999Sgblack@eecs.umich.edu else 4664999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4674999Sgblack@eecs.umich.edu } 4684999Sgblack@eecs.umich.edu dcache_access = true; 4694999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4704999Sgblack@eecs.umich.edu 4714999Sgblack@eecs.umich.edu if (req->isSwap()) { 4724999Sgblack@eecs.umich.edu assert(res); 47310563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 4744999Sgblack@eecs.umich.edu } 4754999Sgblack@eecs.umich.edu } 4764999Sgblack@eecs.umich.edu 4774999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4784999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4794878Sstever@eecs.umich.edu } 4804040Ssaidi@eecs.umich.edu } 4814040Ssaidi@eecs.umich.edu 4824999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4834999Sgblack@eecs.umich.edu //stop now. 4844999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4854999Sgblack@eecs.umich.edu { 4866078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4876078Sgblack@eecs.umich.edu assert(locked); 4886078Sgblack@eecs.umich.edu locked = false; 4896078Sgblack@eecs.umich.edu } 4906739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4916739Sgblack@eecs.umich.edu return NoFault; 4926739Sgblack@eecs.umich.edu } else { 4936739Sgblack@eecs.umich.edu return fault; 4946739Sgblack@eecs.umich.edu } 4953170Sstever@eecs.umich.edu } 4963170Sstever@eecs.umich.edu 4974999Sgblack@eecs.umich.edu /* 4984999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4994999Sgblack@eecs.umich.edu */ 5004999Sgblack@eecs.umich.edu 5014999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5027520Sgblack@eecs.umich.edu data += size; 5034999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5047520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5054999Sgblack@eecs.umich.edu //And access the right address. 5064999Sgblack@eecs.umich.edu addr = secondAddr; 5072623SN/A } 5082623SN/A} 5092623SN/A 5102623SN/A 5112623SN/Avoid 5122623SN/AAtomicSimpleCPU::tick() 5132623SN/A{ 5144940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5154940Snate@binkert.org 5165487Snate@binkert.org Tick latency = 0; 5172623SN/A 5186078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5192623SN/A numCycles++; 52010464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5212623SN/A 52210596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5233387Sgblack@eecs.umich.edu checkForInterrupts(); 52410596Sgabeblack@google.com checkPcEventQueue(); 52510596Sgabeblack@google.com } 5262626SN/A 5278143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5289443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5299443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5308143SAli.Saidi@ARM.com return; 5319443SAndreas.Sandberg@ARM.com } 5325348Ssaidi@eecs.umich.edu 5335669Sgblack@eecs.umich.edu Fault fault = NoFault; 5345669Sgblack@eecs.umich.edu 5357720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5367720Sgblack@eecs.umich.edu 5377720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5387720Sgblack@eecs.umich.edu !curMacroStaticInst; 5397720Sgblack@eecs.umich.edu if (needToFetch) { 54010024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5415894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 5426023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 5436023Snate@binkert.org BaseTLB::Execute); 5445894Sgblack@eecs.umich.edu } 5452623SN/A 5462623SN/A if (fault == NoFault) { 5474182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5484182Sgblack@eecs.umich.edu bool icache_access = false; 5494182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5502662Sstever@eecs.umich.edu 5517720Sgblack@eecs.umich.edu if (needToFetch) { 5529023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5535694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5545694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5555694Sgblack@eecs.umich.edu // this code should be uncommented. 5565669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5579023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 5585669Sgblack@eecs.umich.edu //{ 5595669Sgblack@eecs.umich.edu icache_access = true; 5608949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 5615669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5622623SN/A 5638931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5648931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5655669Sgblack@eecs.umich.edu else 5665669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5674968Sacolyte@umich.edu 5685669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5694968Sacolyte@umich.edu 5705669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5715669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5725669Sgblack@eecs.umich.edu //} 5735669Sgblack@eecs.umich.edu } 5744182Sgblack@eecs.umich.edu 5752623SN/A preExecute(); 5763814Ssaidi@eecs.umich.edu 5775001Sgblack@eecs.umich.edu if (curStaticInst) { 5784182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5794998Sgblack@eecs.umich.edu 5804998Sgblack@eecs.umich.edu // keep an instruction count 58110381Sdam.sunwoo@arm.com if (fault == NoFault) { 5824998Sgblack@eecs.umich.edu countInst(); 58310651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 58410381Sdam.sunwoo@arm.com } 5857655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5865001Sgblack@eecs.umich.edu delete traceData; 5875001Sgblack@eecs.umich.edu traceData = NULL; 5885001Sgblack@eecs.umich.edu } 5894998Sgblack@eecs.umich.edu 5904182Sgblack@eecs.umich.edu postExecute(); 5914182Sgblack@eecs.umich.edu } 5922623SN/A 5933814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5944539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5954539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5963814Ssaidi@eecs.umich.edu instCnt++; 5973814Ssaidi@eecs.umich.edu 5985487Snate@binkert.org Tick stall_ticks = 0; 5995487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6005487Snate@binkert.org stall_ticks += icache_latency; 6015487Snate@binkert.org 6025487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6035487Snate@binkert.org stall_ticks += dcache_latency; 6045487Snate@binkert.org 6055487Snate@binkert.org if (stall_ticks) { 6069180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6079180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6089180Sandreas.hansson@arm.com // period 6099180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6109180Sandreas.hansson@arm.com clockPeriod(); 6112623SN/A } 6122623SN/A 6132623SN/A } 6144377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 6154182Sgblack@eecs.umich.edu advancePC(fault); 6162623SN/A } 6172623SN/A 6189443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6199443SAndreas.Sandberg@ARM.com return; 6209443SAndreas.Sandberg@ARM.com 6215487Snate@binkert.org // instruction takes at least one cycle 6229179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6239179Sandreas.hansson@arm.com latency = clockPeriod(); 6245487Snate@binkert.org 6252626SN/A if (_status != Idle) 6267823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 6272623SN/A} 6282623SN/A 62910381Sdam.sunwoo@arm.comvoid 63010381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 63110381Sdam.sunwoo@arm.com{ 63210464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 63310464SAndreas.Sandberg@ARM.com 63410381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 63510381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 63610381Sdam.sunwoo@arm.com} 6372623SN/A 6385315Sstever@gmail.comvoid 6395315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6405315Sstever@gmail.com{ 6415315Sstever@gmail.com dcachePort.printAddr(a); 6425315Sstever@gmail.com} 6435315Sstever@gmail.com 6442623SN/A//////////////////////////////////////////////////////////////////////// 6452623SN/A// 6462623SN/A// AtomicSimpleCPU Simulation Object 6472623SN/A// 6484762Snate@binkert.orgAtomicSimpleCPU * 6494762Snate@binkert.orgAtomicSimpleCPUParams::create() 6502623SN/A{ 6515529Snate@binkert.org numThreads = 1; 6528779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 6534762Snate@binkert.org panic("only one workload allowed"); 6545529Snate@binkert.org return new AtomicSimpleCPU(this); 6552623SN/A} 656