reg_class.hh revision 12104
19913Ssteve.reinhardt@amd.com/* 212104Snathanael.premillieu@arm.com * Copyright (c) 2016 ARM Limited 312104Snathanael.premillieu@arm.com * All rights reserved 412104Snathanael.premillieu@arm.com * 512104Snathanael.premillieu@arm.com * The license below extends only to copyright in the software and shall 612104Snathanael.premillieu@arm.com * not be construed as granting a license to any other intellectual 712104Snathanael.premillieu@arm.com * property including but not limited to intellectual property relating 812104Snathanael.premillieu@arm.com * to a hardware implementation of the functionality of the software 912104Snathanael.premillieu@arm.com * licensed hereunder. You may use the software subject to the license 1012104Snathanael.premillieu@arm.com * terms below provided that you ensure that this notice is replicated 1112104Snathanael.premillieu@arm.com * unmodified and in its entirety in all distributions of the software, 1212104Snathanael.premillieu@arm.com * modified or unmodified, in source code or in binary form. 1312104Snathanael.premillieu@arm.com * 149913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 159913Ssteve.reinhardt@amd.com * All rights reserved 169913Ssteve.reinhardt@amd.com *. 179913Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 189913Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 199913Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 209913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 219913Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 229913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 239913Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 249913Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 259913Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 269913Ssteve.reinhardt@amd.com * this software without specific prior written permission. 279913Ssteve.reinhardt@amd.com * 289913Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299913Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309913Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319913Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329913Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339913Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349913Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359913Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369913Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379913Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389913Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399913Ssteve.reinhardt@amd.com * 409913Ssteve.reinhardt@amd.com * Authors: Steve Reinhardt 4112104Snathanael.premillieu@arm.com * Nathanael Premillieu 429913Ssteve.reinhardt@amd.com */ 439913Ssteve.reinhardt@amd.com 449913Ssteve.reinhardt@amd.com#ifndef __CPU__REG_CLASS_HH__ 459913Ssteve.reinhardt@amd.com#define __CPU__REG_CLASS_HH__ 469913Ssteve.reinhardt@amd.com 479913Ssteve.reinhardt@amd.com#include <cassert> 489913Ssteve.reinhardt@amd.com#include <cstddef> 499913Ssteve.reinhardt@amd.com 5012104Snathanael.premillieu@arm.com#include "arch/generic/types.hh" 519913Ssteve.reinhardt@amd.com#include "arch/registers.hh" 529913Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 539913Ssteve.reinhardt@amd.com 549913Ssteve.reinhardt@amd.com/// Enumerate the classes of registers. 559913Ssteve.reinhardt@amd.comenum RegClass { 569913Ssteve.reinhardt@amd.com IntRegClass, ///< Integer register 579913Ssteve.reinhardt@amd.com FloatRegClass, ///< Floating-point register 589920Syasuko.eckert@amd.com CCRegClass, ///< Condition-code register 599913Ssteve.reinhardt@amd.com MiscRegClass ///< Control (misc) register 609913Ssteve.reinhardt@amd.com}; 619913Ssteve.reinhardt@amd.com 629913Ssteve.reinhardt@amd.com/// Number of register classes. This value is not part of the enum, 639913Ssteve.reinhardt@amd.com/// because putting it there makes the compiler complain about 649913Ssteve.reinhardt@amd.com/// unhandled cases in some switch statements. 659913Ssteve.reinhardt@amd.comconst int NumRegClasses = MiscRegClass + 1; 669913Ssteve.reinhardt@amd.com 6712104Snathanael.premillieu@arm.com/// Register ID: describe an architectural register with its class and index. 6812104Snathanael.premillieu@arm.com/// This structure is used instead of just the register index to disambiguate 6912104Snathanael.premillieu@arm.com/// between different classes of registers. 7012104Snathanael.premillieu@arm.com/// For example, a integer register with index 3 is represented by 7112104Snathanael.premillieu@arm.com/// Regid(IntRegClass, 3). 7212104Snathanael.premillieu@arm.comstruct RegId { 7312104Snathanael.premillieu@arm.com RegClass regClass; 7412104Snathanael.premillieu@arm.com RegIndex regIdx; 7512104Snathanael.premillieu@arm.com RegId() {}; 7612104Snathanael.premillieu@arm.com RegId(RegClass reg_class, RegIndex reg_idx) 7712104Snathanael.premillieu@arm.com : regClass(reg_class), regIdx(reg_idx) 7812104Snathanael.premillieu@arm.com {} 799913Ssteve.reinhardt@amd.com 8012104Snathanael.premillieu@arm.com bool operator==(const RegId& that) const { 8112104Snathanael.premillieu@arm.com return regClass == that.regClass && regIdx == that.regIdx; 829913Ssteve.reinhardt@amd.com } 839913Ssteve.reinhardt@amd.com 8412104Snathanael.premillieu@arm.com bool operator!=(const RegId& that) const { 8512104Snathanael.premillieu@arm.com return !(*this==that); 8612104Snathanael.premillieu@arm.com } 8712104Snathanael.premillieu@arm.com 8812104Snathanael.premillieu@arm.com /** 8912104Snathanael.premillieu@arm.com * Returns true if this register is a zero register (needs to have a 9012104Snathanael.premillieu@arm.com * constant zero value throughout the execution) 9112104Snathanael.premillieu@arm.com */ 9212104Snathanael.premillieu@arm.com bool isZeroReg() const 9312104Snathanael.premillieu@arm.com { 9412104Snathanael.premillieu@arm.com return (regIdx == TheISA::ZeroReg && 9512104Snathanael.premillieu@arm.com (regClass == IntRegClass || 9612104Snathanael.premillieu@arm.com (THE_ISA == ALPHA_ISA && regClass == FloatRegClass))); 9712104Snathanael.premillieu@arm.com } 9812104Snathanael.premillieu@arm.com 9912104Snathanael.premillieu@arm.com /** 10012104Snathanael.premillieu@arm.com * Return true if this register can be renamed 10112104Snathanael.premillieu@arm.com */ 10212104Snathanael.premillieu@arm.com bool isRenameable() 10312104Snathanael.premillieu@arm.com { 10412104Snathanael.premillieu@arm.com return regClass != MiscRegClass; 10512104Snathanael.premillieu@arm.com } 10612104Snathanael.premillieu@arm.com 10712104Snathanael.premillieu@arm.com static const RegId zeroReg; 10812104Snathanael.premillieu@arm.com}; 1099913Ssteve.reinhardt@amd.com 1109913Ssteve.reinhardt@amd.com/// Map enum values to strings for debugging 1119913Ssteve.reinhardt@amd.comextern const char *RegClassStrings[]; 1129913Ssteve.reinhardt@amd.com#endif // __CPU__REG_CLASS_HH__ 113