indirect.hh revision 13654:dc3878f03a0c
111988Sandreas.sandberg@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2014 ARM Limited 38839Sandreas.hansson@arm.com * All rights reserved. 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68839Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78839Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98839Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118839Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128839Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 133101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 148579Ssteve.reinhardt@amd.com * this software without specific prior written permission. 153101Sstever@eecs.umich.edu * 163101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273101Sstever@eecs.umich.edu * 283101Sstever@eecs.umich.edu * Authors: Mitch Hayenga 293101Sstever@eecs.umich.edu */ 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu#ifndef __CPU_PRED_INDIRECT_HH__ 323101Sstever@eecs.umich.edu#define __CPU_PRED_INDIRECT_HH__ 333101Sstever@eecs.umich.edu 343101Sstever@eecs.umich.edu#include <deque> 353101Sstever@eecs.umich.edu 363101Sstever@eecs.umich.edu#include "arch/isa_traits.hh" 373101Sstever@eecs.umich.edu#include "config/the_isa.hh" 383101Sstever@eecs.umich.edu#include "cpu/inst_seq.hh" 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.educlass IndirectPredictor 413101Sstever@eecs.umich.edu{ 427778Sgblack@eecs.umich.edu public: 438839Sandreas.hansson@arm.com IndirectPredictor(bool hash_ghr, bool hash_targets, 443101Sstever@eecs.umich.edu unsigned num_sets, unsigned num_ways, 453101Sstever@eecs.umich.edu unsigned tag_bits, unsigned path_len, 463101Sstever@eecs.umich.edu unsigned inst_shift, unsigned num_threads); 473101Sstever@eecs.umich.edu bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid); 483101Sstever@eecs.umich.edu void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, 493101Sstever@eecs.umich.edu ThreadID tid); 503101Sstever@eecs.umich.edu void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history); 513101Sstever@eecs.umich.edu void squash(InstSeqNum seq_num, ThreadID tid); 523101Sstever@eecs.umich.edu void recordTarget(InstSeqNum seq_num, const TheISA::PCState& target, 533101Sstever@eecs.umich.edu ThreadID tid); 543101Sstever@eecs.umich.edu void updateDirectionInfo(ThreadID tid, bool taken, 553101Sstever@eecs.umich.edu void* & indirect_history); 563101Sstever@eecs.umich.edu void changeDirectionPrediction(ThreadID tid, void * indirect_history, 573101Sstever@eecs.umich.edu bool actually_taken); 583101Sstever@eecs.umich.edu void deleteDirectionInfo(ThreadID tid, void * indirect_history); 593101Sstever@eecs.umich.edu 603101Sstever@eecs.umich.edu private: 613101Sstever@eecs.umich.edu const bool hashGHR; 623885Sbinkertn@umich.edu const bool hashTargets; 633885Sbinkertn@umich.edu const unsigned numSets; 644762Snate@binkert.org const unsigned numWays; 653885Sbinkertn@umich.edu const unsigned tagBits; 663885Sbinkertn@umich.edu const unsigned pathLength; 677528Ssteve.reinhardt@amd.com const unsigned instShift; 683885Sbinkertn@umich.edu 694380Sbinkertn@umich.edu struct IPredEntry 704167Sbinkertn@umich.edu { 713102Sstever@eecs.umich.edu IPredEntry() : tag(0), target(0) { } 723101Sstever@eecs.umich.edu Addr tag; 734762Snate@binkert.org TheISA::PCState target; 744762Snate@binkert.org }; 754762Snate@binkert.org 764762Snate@binkert.org std::vector<std::vector<IPredEntry> > targetCache; 774762Snate@binkert.org 784762Snate@binkert.org Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid); 794762Snate@binkert.org Addr getTag(Addr br_addr); 804762Snate@binkert.org 814762Snate@binkert.org struct HistoryEntry 825033Smilesck@eecs.umich.edu { 835033Smilesck@eecs.umich.edu HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num) 845033Smilesck@eecs.umich.edu : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { } 855033Smilesck@eecs.umich.edu Addr pcAddr; 865033Smilesck@eecs.umich.edu Addr targetAddr; 875033Smilesck@eecs.umich.edu InstSeqNum seqNum; 885033Smilesck@eecs.umich.edu }; 895033Smilesck@eecs.umich.edu 905033Smilesck@eecs.umich.edu 915033Smilesck@eecs.umich.edu struct ThreadInfo { 923101Sstever@eecs.umich.edu ThreadInfo() : headHistEntry(0), ghr(0) { } 933101Sstever@eecs.umich.edu 943101Sstever@eecs.umich.edu std::deque<HistoryEntry> pathHist; 955033Smilesck@eecs.umich.edu unsigned headHistEntry; 9610267SGeoffrey.Blake@arm.com unsigned ghr; 978596Ssteve.reinhardt@amd.com }; 988596Ssteve.reinhardt@amd.com 998596Ssteve.reinhardt@amd.com std::vector<ThreadInfo> threadInfo; 1008596Ssteve.reinhardt@amd.com}; 1017673Snate@binkert.org 1027673Snate@binkert.org#endif // __CPU_PRED_INDIRECT_HH__ 1037673Snate@binkert.org