op_class.hh revision 7760
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Nathan Binkert 41 */ 42 43#ifndef __CPU__OP_CLASS_HH__ 44#define __CPU__OP_CLASS_HH__ 45 46#include "enums/OpClass.hh" 47 48/* 49 * Do a bunch of wonky stuff to maintain backward compatability so I 50 * don't have to change code in a zillion places. 51 */ 52using Enums::OpClass; 53using Enums::No_OpClass; 54using Enums::Num_OpClass; 55 56const OpClass IntAluOp = Enums::IntAlu; 57const OpClass IntMultOp = Enums::IntMult; 58const OpClass IntDivOp = Enums::IntDiv; 59const OpClass FloatAddOp = Enums::FloatAdd; 60const OpClass FloatCmpOp = Enums::FloatCmp; 61const OpClass FloatCvtOp = Enums::FloatCvt; 62const OpClass FloatMultOp = Enums::FloatMult; 63const OpClass FloatDivOp = Enums::FloatDiv; 64const OpClass FloatSqrtOp = Enums::FloatSqrt; 65const OpClass SimdAddOp = Enums::SimdAdd; 66const OpClass SimdAddAccOp = Enums::SimdAddAcc; 67const OpClass SimdAluOp = Enums::SimdAlu; 68const OpClass SimdCmpOp = Enums::SimdCmp; 69const OpClass SimdCvtOp = Enums::SimdCvt; 70const OpClass SimdMiscOp = Enums::SimdMisc; 71const OpClass SimdMultOp = Enums::SimdMult; 72const OpClass SimdMultAccOp = Enums::SimdMultAcc; 73const OpClass SimdShiftOp = Enums::SimdShift; 74const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; 75const OpClass SimdSqrtOp = Enums::SimdSqrt; 76const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; 77const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; 78const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; 79const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt; 80const OpClass SimdFloatDivOp = Enums::SimdFloatDiv; 81const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; 82const OpClass SimdFloatMultOp = Enums::SimdFloatMult; 83const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; 84const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; 85const OpClass MemReadOp = Enums::MemRead; 86const OpClass MemWriteOp = Enums::MemWrite; 87const OpClass IprAccessOp = Enums::IprAccess; 88const OpClass InstPrefetchOp = Enums::InstPrefetch; 89const OpClass Num_OpClasses = Num_OpClass; 90 91#endif // __CPU__OP_CLASS_HH__ 92