op_class.hh revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322410SN/A#ifndef __CPU__OP_CLASS_HH__ 332410SN/A#define __CPU__OP_CLASS_HH__ 342SN/A 352SN/A/** 362SN/A * @file 372SN/A * Definition of operation classes. 382SN/A */ 392SN/A 402SN/A/** 412SN/A * Instruction operation classes. These classes are used for 422SN/A * assigning instructions to functional units. 432SN/A */ 442SN/Aenum OpClass { 452410SN/A No_OpClass = 0, ///< Instruction does not use a functional unit 462410SN/A IntAluOp, ///< Integer ALU operaton (add/sub/logical) 472410SN/A IntMultOp, ///< Integer multiply 482410SN/A IntDivOp, ///< Integer divide 492410SN/A FloatAddOp, ///< Floating point add/subtract 502410SN/A FloatCmpOp, ///< Floating point comparison 512410SN/A FloatCvtOp, ///< Floating point<->integer conversion 522410SN/A FloatMultOp, ///< Floating point multiply 532410SN/A FloatDivOp, ///< Floating point divide 542410SN/A FloatSqrtOp, ///< Floating point square root 552410SN/A MemReadOp, ///< Memory read port 562410SN/A MemWriteOp, ///< Memory write port 572410SN/A IprAccessOp, ///< Internal Processor Register read/write port 582410SN/A InstPrefetchOp, ///< Instruction prefetch port (on I-cache) 592410SN/A Num_OpClasses ///< Total number of operation classes 602SN/A}; 612SN/A 622SN/A/** 632410SN/A * Array mapping OpClass enum values to strings. Defined in op_class.cc. 642SN/A */ 652SN/Aextern const char *opClassStrings[]; 662SN/A 672410SN/A#endif // __CPU__OP_CLASS_HH__ 68