op_class.hh revision 13168
16019Shines@cs.fsu.edu/* 212259Sgiacomo.travaglini@arm.com * Copyright (c) 2010,2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Nathan Binkert 416735Sgblack@eecs.umich.edu */ 426735Sgblack@eecs.umich.edu 4310037SARM gem5 Developers#ifndef __CPU__OP_CLASS_HH__ 4410037SARM gem5 Developers#define __CPU__OP_CLASS_HH__ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#include "enums/OpClass.hh" 476019Shines@cs.fsu.edu 4811793Sbrandon.potter@amd.com/* 4911793Sbrandon.potter@amd.com * Do a bunch of wonky stuff to maintain backward compatability so I 5010037SARM gem5 Developers * don't have to change code in a zillion places. 5110037SARM gem5 Developers */ 5210037SARM gem5 Developersusing Enums::OpClass; 538229Snate@binkert.orgusing Enums::No_OpClass; 548229Snate@binkert.org 556019Shines@cs.fsu.edustatic const OpClass IntAluOp = Enums::IntAlu; 568232Snate@binkert.orgstatic const OpClass IntMultOp = Enums::IntMult; 578782Sgblack@eecs.umich.edustatic const OpClass IntDivOp = Enums::IntDiv; 586019Shines@cs.fsu.edustatic const OpClass FloatAddOp = Enums::FloatAdd; 596019Shines@cs.fsu.edustatic const OpClass FloatCmpOp = Enums::FloatCmp; 606019Shines@cs.fsu.edustatic const OpClass FloatCvtOp = Enums::FloatCvt; 616019Shines@cs.fsu.edustatic const OpClass FloatMultOp = Enums::FloatMult; 6210037SARM gem5 Developersstatic const OpClass FloatMultAccOp = Enums::FloatMultAcc; 6310037SARM gem5 Developersstatic const OpClass FloatDivOp = Enums::FloatDiv; 6410037SARM gem5 Developersstatic const OpClass FloatMiscOp = Enums::FloatMisc; 6510037SARM gem5 Developersstatic const OpClass FloatSqrtOp = Enums::FloatSqrt; 6610037SARM gem5 Developersstatic const OpClass SimdAddOp = Enums::SimdAdd; 6710037SARM gem5 Developersstatic const OpClass SimdAddAccOp = Enums::SimdAddAcc; 6810037SARM gem5 Developersstatic const OpClass SimdAluOp = Enums::SimdAlu; 6910037SARM gem5 Developersstatic const OpClass SimdCmpOp = Enums::SimdCmp; 7010037SARM gem5 Developersstatic const OpClass SimdCvtOp = Enums::SimdCvt; 7110037SARM gem5 Developersstatic const OpClass SimdMiscOp = Enums::SimdMisc; 7210037SARM gem5 Developersstatic const OpClass SimdMultOp = Enums::SimdMult; 7310037SARM gem5 Developersstatic const OpClass SimdMultAccOp = Enums::SimdMultAcc; 7410037SARM gem5 Developersstatic const OpClass SimdShiftOp = Enums::SimdShift; 7510037SARM gem5 Developersstatic const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; 7610037SARM gem5 Developersstatic const OpClass SimdSqrtOp = Enums::SimdSqrt; 7710037SARM gem5 Developersstatic const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; 7810037SARM gem5 Developersstatic const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; 7910037SARM gem5 Developersstatic const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; 8010037SARM gem5 Developersstatic const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt; 8110037SARM gem5 Developersstatic const OpClass SimdFloatDivOp = Enums::SimdFloatDiv; 8210037SARM gem5 Developersstatic const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; 8310037SARM gem5 Developersstatic const OpClass SimdFloatMultOp = Enums::SimdFloatMult; 8410037SARM gem5 Developersstatic const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; 8510037SARM gem5 Developersstatic const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; 8610037SARM gem5 Developersstatic const OpClass SimdSha1HashOp = Enums::SimdSha1Hash; 8710037SARM gem5 Developersstatic const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2; 8810037SARM gem5 Developersstatic const OpClass SimdSha256HashOp = Enums::SimdSha256Hash; 8910037SARM gem5 Developersstatic const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2; 9010037SARM gem5 Developersstatic const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2; 9110037SARM gem5 Developersstatic const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3; 9210037SARM gem5 Developersstatic const OpClass MemReadOp = Enums::MemRead; 9310037SARM gem5 Developersstatic const OpClass MemWriteOp = Enums::MemWrite; 9410037SARM gem5 Developersstatic const OpClass FloatMemReadOp = Enums::FloatMemRead; 9510037SARM gem5 Developersstatic const OpClass FloatMemWriteOp = Enums::FloatMemWrite; 9610037SARM gem5 Developersstatic const OpClass IprAccessOp = Enums::IprAccess; 9710037SARM gem5 Developersstatic const OpClass InstPrefetchOp = Enums::InstPrefetch; 9810037SARM gem5 Developersstatic const OpClass Num_OpClasses = Enums::Num_OpClass; 9910037SARM gem5 Developers 10010037SARM gem5 Developers#endif // __CPU__OP_CLASS_HH__ 10110037SARM gem5 Developers