thread_state.hh revision 2680:246e7104f744
12SN/A/* 21762SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __CPU_O3_THREAD_STATE_HH__ 302SN/A#define __CPU_O3_THREAD_STATE_HH__ 312SN/A 321388SN/A#include "arch/faults.hh" 332SN/A#include "arch/isa_traits.hh" 342SN/A#include "cpu/thread_context.hh" 352SN/A#include "cpu/thread_state.hh" 361191SN/A 371191SN/Aclass Event; 381191SN/Aclass Process; 391388SN/A 405529Snate@binkert.org#if FULL_SYSTEM 411717SN/Aclass EndQuiesceEvent; 422651Ssaidi@eecs.umich.educlass FunctionProfile; 432680Sktlim@umich.educlass ProfileNode; 441977SN/A#else 455529Snate@binkert.orgclass FunctionalMemory; 463144Shsul@eecs.umich.educlass Process; 472190SN/A#endif 4856SN/A 492190SN/A/** 502SN/A * Class that has various thread state, such as the status, the 512359SN/A * current instruction being processed, whether or not the thread has 522359SN/A * a trap pending or is being externally updated, the ThreadContext 532359SN/A * pointer, etc. It also handles anything related to a specific 542SN/A * thread's process, such as syscalls and checking valid addresses. 552SN/A */ 562SN/Atemplate <class Impl> 572SN/Astruct O3ThreadState : public ThreadState { 582SN/A typedef ThreadContext::Status Status; 592SN/A typedef typename Impl::FullCPU FullCPU; 602SN/A 612SN/A /** Current status of the thread. */ 622SN/A Status _status; 635606Snate@binkert.org 645606Snate@binkert.org /** Current instruction the thread is committing. Only set and 655606Snate@binkert.org * used for DTB faults currently. 663126Sktlim@umich.edu */ 673126Sktlim@umich.edu TheISA::MachInst inst; 685606Snate@binkert.org 693126Sktlim@umich.edu private: 703126Sktlim@umich.edu /** Pointer to the CPU. */ 712356SN/A FullCPU *cpu; 722356SN/A public: 732356SN/A /** Whether or not the thread is currently in syscall mode, and 742367SN/A * thus able to be externally updated without squashing. 752356SN/A */ 765100Ssaidi@eecs.umich.edu bool inSyscall; 772367SN/A 782356SN/A /** Whether or not the thread is currently waiting on a trap, and 792356SN/A * thus able to be externally updated without squashing. 802356SN/A */ 812367SN/A bool trapPending; 822367SN/A 832367SN/A#if FULL_SYSTEM 842367SN/A O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem) 852356SN/A : ThreadState(-1, _thread_num, _mem), 865606Snate@binkert.org inSyscall(0), trapPending(0) 872356SN/A { } 882356SN/A#else 892356SN/A O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid, 905336Shines@cs.fsu.edu MemObject *mem) 912356SN/A : ThreadState(-1, _thread_num, mem, _process, _asid), 924873Sstever@eecs.umich.edu cpu(_cpu), inSyscall(0), trapPending(0) 932356SN/A { } 942356SN/A#endif 951858SN/A 961400SN/A /** Pointer to the ThreadContext of this thread. */ 975712Shsul@eecs.umich.edu ThreadContext *tc; 985712Shsul@eecs.umich.edu 995529Snate@binkert.org /** Returns a pointer to the TC of this thread. */ 1003661Srdreslin@umich.edu ThreadContext *getTC() { return tc; } 1012SN/A 1021400SN/A /** Returns the status of this thread. */ 1035712Shsul@eecs.umich.edu Status status() const { return _status; } 1045529Snate@binkert.org 1053661Srdreslin@umich.edu /** Sets the status of this thread. */ 1062SN/A void setStatus(Status new_status) { _status = new_status; } 1072SN/A 1082359SN/A /** Sets the current instruction being committed. */ 1091062SN/A void setInst(TheISA::MachInst _inst) { inst = _inst; } 1105712Shsul@eecs.umich.edu 1115712Shsul@eecs.umich.edu /** Reads the number of instructions functionally executed and 1125712Shsul@eecs.umich.edu * committed. 1135712Shsul@eecs.umich.edu */ 1145712Shsul@eecs.umich.edu Counter readFuncExeInst() { return funcExeInst; } 1152SN/A 1162SN/A /** Sets the total number of instructions functionally executed 1172SN/A * and committed. 1185712Shsul@eecs.umich.edu */ 1195712Shsul@eecs.umich.edu void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 1202SN/A 1212SN/A#if !FULL_SYSTEM 1222SN/A /** Handles the syscall. */ 1232SN/A void syscall(int64_t callnum) { process->syscall(callnum, tc); } 1241354SN/A#endif 1252SN/A}; 126503SN/A 1272SN/A#endif // __CPU_O3_THREAD_STATE_HH__ 1282SN/A