thread_context_impl.hh revision 9920:028e4da64b42 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#include "arch/kernel_stats.hh"
46#include "arch/registers.hh"
47#include "config/the_isa.hh"
48#include "cpu/o3/thread_context.hh"
49#include "cpu/quiesce_event.hh"
50#include "debug/O3CPU.hh"
51
52template <class Impl>
53FSTranslatingPortProxy&
54O3ThreadContext<Impl>::getVirtProxy()
55{
56    return thread->getVirtProxy();
57}
58
59template <class Impl>
60void
61O3ThreadContext<Impl>::dumpFuncProfile()
62{
63    thread->dumpFuncProfile();
64}
65
66template <class Impl>
67void
68O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
69{
70    ::takeOverFrom(*this, *old_context);
71    TheISA::Decoder *newDecoder = getDecoderPtr();
72    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
73    newDecoder->takeOverFrom(oldDecoder);
74
75    thread->kernelStats = old_context->getKernelStats();
76    thread->funcExeInst = old_context->readFuncExeInst();
77
78    thread->noSquashFromTC = false;
79    thread->trapPending = false;
80}
81
82template <class Impl>
83void
84O3ThreadContext<Impl>::activate(Cycles delay)
85{
86    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
87            threadId());
88
89    if (thread->status() == ThreadContext::Active)
90        return;
91
92    thread->lastActivate = curTick();
93    thread->setStatus(ThreadContext::Active);
94
95    // status() == Suspended
96    cpu->activateContext(thread->threadId(), delay);
97}
98
99template <class Impl>
100void
101O3ThreadContext<Impl>::suspend(Cycles delay)
102{
103    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
104            threadId());
105
106    if (thread->status() == ThreadContext::Suspended)
107        return;
108
109    thread->lastActivate = curTick();
110    thread->lastSuspend = curTick();
111
112    thread->setStatus(ThreadContext::Suspended);
113    cpu->suspendContext(thread->threadId());
114}
115
116template <class Impl>
117void
118O3ThreadContext<Impl>::halt(Cycles delay)
119{
120    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
121            threadId());
122
123    if (thread->status() == ThreadContext::Halted)
124        return;
125
126    thread->setStatus(ThreadContext::Halted);
127    cpu->haltContext(thread->threadId());
128}
129
130template <class Impl>
131void
132O3ThreadContext<Impl>::regStats(const std::string &name)
133{
134    if (FullSystem) {
135        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
136        thread->kernelStats->regStats(name + ".kern");
137    }
138}
139
140template <class Impl>
141Tick
142O3ThreadContext<Impl>::readLastActivate()
143{
144    return thread->lastActivate;
145}
146
147template <class Impl>
148Tick
149O3ThreadContext<Impl>::readLastSuspend()
150{
151    return thread->lastSuspend;
152}
153
154template <class Impl>
155void
156O3ThreadContext<Impl>::profileClear()
157{
158    thread->profileClear();
159}
160
161template <class Impl>
162void
163O3ThreadContext<Impl>::profileSample()
164{
165    thread->profileSample();
166}
167
168template <class Impl>
169void
170O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
171{
172    // Prevent squashing
173    thread->noSquashFromTC = true;
174    TheISA::copyRegs(tc, this);
175    thread->noSquashFromTC = false;
176
177    if (!FullSystem)
178        this->thread->funcExeInst = tc->readFuncExeInst();
179}
180
181template <class Impl>
182void
183O3ThreadContext<Impl>::clearArchRegs()
184{
185    cpu->isa[thread->threadId()]->clear();
186}
187
188template <class Impl>
189uint64_t
190O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
191{
192    return cpu->readArchIntReg(reg_idx, thread->threadId());
193}
194
195template <class Impl>
196TheISA::FloatReg
197O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
198{
199    return cpu->readArchFloatReg(reg_idx, thread->threadId());
200}
201
202template <class Impl>
203TheISA::FloatRegBits
204O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
205{
206    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
207}
208
209template <class Impl>
210TheISA::CCReg
211O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
212{
213    return cpu->readArchCCReg(reg_idx, thread->threadId());
214}
215
216template <class Impl>
217void
218O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
219{
220    cpu->setArchIntReg(reg_idx, val, thread->threadId());
221
222    conditionalSquash();
223}
224
225template <class Impl>
226void
227O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
228{
229    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
230
231    conditionalSquash();
232}
233
234template <class Impl>
235void
236O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
237{
238    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
239
240    conditionalSquash();
241}
242
243template <class Impl>
244void
245O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
246{
247    cpu->setArchCCReg(reg_idx, val, thread->threadId());
248
249    conditionalSquash();
250}
251
252template <class Impl>
253void
254O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
255{
256    cpu->pcState(val, thread->threadId());
257
258    conditionalSquash();
259}
260
261template <class Impl>
262void
263O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
264{
265    cpu->pcState(val, thread->threadId());
266
267    conditionalSquash();
268}
269
270template <class Impl>
271int
272O3ThreadContext<Impl>::flattenIntIndex(int reg)
273{
274    return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
275}
276
277template <class Impl>
278int
279O3ThreadContext<Impl>::flattenFloatIndex(int reg)
280{
281    return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
282}
283
284template <class Impl>
285int
286O3ThreadContext<Impl>::flattenCCIndex(int reg)
287{
288    return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
289}
290
291template <class Impl>
292void
293O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
294{
295    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
296
297    conditionalSquash();
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
303{
304    cpu->setMiscReg(misc_reg, val, thread->threadId());
305
306    conditionalSquash();
307}
308
309