thread_context_impl.hh revision 8733:64a7bf8fa56c 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include "arch/registers.hh"
45#include "config/the_isa.hh"
46#include "config/use_checker.hh"
47#include "cpu/o3/thread_context.hh"
48#include "cpu/quiesce_event.hh"
49#include "debug/O3CPU.hh"
50
51#if FULL_SYSTEM
52template <class Impl>
53FSTranslatingPortProxy*
54O3ThreadContext<Impl>::getVirtProxy()
55{
56    return thread->getVirtProxy();
57}
58
59template <class Impl>
60void
61O3ThreadContext<Impl>::dumpFuncProfile()
62{
63    thread->dumpFuncProfile();
64}
65#endif
66
67template <class Impl>
68void
69O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
70{
71    // some things should already be set up
72#if FULL_SYSTEM
73    assert(getSystemPtr() == old_context->getSystemPtr());
74#else
75    assert(getProcessPtr() == old_context->getProcessPtr());
76#endif
77
78    // copy over functional state
79    setStatus(old_context->status());
80    copyArchRegs(old_context);
81    setContextId(old_context->contextId());
82    setThreadId(old_context->threadId());
83
84#if !FULL_SYSTEM
85    thread->funcExeInst = old_context->readFuncExeInst();
86#else
87    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
88    if (other_quiesce) {
89        // Point the quiesce event's TC at this TC so that it wakes up
90        // the proper CPU.
91        other_quiesce->tc = this;
92    }
93    if (thread->quiesceEvent) {
94        thread->quiesceEvent->tc = this;
95    }
96
97    // Transfer kernel stats from one CPU to the other.
98    thread->kernelStats = old_context->getKernelStats();
99//    storeCondFailures = 0;
100    cpu->lockFlag = false;
101#endif
102
103    old_context->setStatus(ThreadContext::Halted);
104
105    thread->inSyscall = false;
106    thread->trapPending = false;
107}
108
109template <class Impl>
110void
111O3ThreadContext<Impl>::activate(int delay)
112{
113    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
114            threadId());
115
116    if (thread->status() == ThreadContext::Active)
117        return;
118
119#if FULL_SYSTEM
120    thread->lastActivate = curTick();
121#endif
122
123    thread->setStatus(ThreadContext::Active);
124
125    // status() == Suspended
126    cpu->activateContext(thread->threadId(), delay);
127}
128
129template <class Impl>
130void
131O3ThreadContext<Impl>::suspend(int delay)
132{
133    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
134            threadId());
135
136    if (thread->status() == ThreadContext::Suspended)
137        return;
138
139#if FULL_SYSTEM
140    thread->lastActivate = curTick();
141    thread->lastSuspend = curTick();
142#endif
143/*
144#if FULL_SYSTEM
145    // Don't change the status from active if there are pending interrupts
146    if (cpu->checkInterrupts()) {
147        assert(status() == ThreadContext::Active);
148        return;
149    }
150#endif
151*/
152    thread->setStatus(ThreadContext::Suspended);
153    cpu->suspendContext(thread->threadId());
154}
155
156template <class Impl>
157void
158O3ThreadContext<Impl>::halt(int delay)
159{
160    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
161            threadId());
162
163    if (thread->status() == ThreadContext::Halted)
164        return;
165
166    thread->setStatus(ThreadContext::Halted);
167    cpu->haltContext(thread->threadId());
168}
169
170template <class Impl>
171void
172O3ThreadContext<Impl>::regStats(const std::string &name)
173{
174#if FULL_SYSTEM
175    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
176    thread->kernelStats->regStats(name + ".kern");
177#endif
178}
179
180template <class Impl>
181void
182O3ThreadContext<Impl>::serialize(std::ostream &os)
183{
184#if FULL_SYSTEM
185    if (thread->kernelStats)
186        thread->kernelStats->serialize(os);
187#endif
188
189}
190
191template <class Impl>
192void
193O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
194{
195#if FULL_SYSTEM
196    if (thread->kernelStats)
197        thread->kernelStats->unserialize(cp, section);
198#endif
199
200}
201
202#if FULL_SYSTEM
203template <class Impl>
204Tick
205O3ThreadContext<Impl>::readLastActivate()
206{
207    return thread->lastActivate;
208}
209
210template <class Impl>
211Tick
212O3ThreadContext<Impl>::readLastSuspend()
213{
214    return thread->lastSuspend;
215}
216
217template <class Impl>
218void
219O3ThreadContext<Impl>::profileClear()
220{
221    thread->profileClear();
222}
223
224template <class Impl>
225void
226O3ThreadContext<Impl>::profileSample()
227{
228    thread->profileSample();
229}
230#endif
231
232template <class Impl>
233void
234O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
235{
236    // Prevent squashing
237    thread->inSyscall = true;
238    TheISA::copyRegs(tc, this);
239    thread->inSyscall = false;
240
241#if !FULL_SYSTEM
242    this->thread->funcExeInst = tc->readFuncExeInst();
243#endif
244}
245
246template <class Impl>
247void
248O3ThreadContext<Impl>::clearArchRegs()
249{
250    cpu->isa[thread->threadId()].clear();
251}
252
253template <class Impl>
254uint64_t
255O3ThreadContext<Impl>::readIntReg(int reg_idx)
256{
257    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
258    return cpu->readArchIntReg(reg_idx, thread->threadId());
259}
260
261template <class Impl>
262TheISA::FloatReg
263O3ThreadContext<Impl>::readFloatReg(int reg_idx)
264{
265    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
266    return cpu->readArchFloatReg(reg_idx, thread->threadId());
267}
268
269template <class Impl>
270TheISA::FloatRegBits
271O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
272{
273    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
274    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
275}
276
277template <class Impl>
278void
279O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
280{
281    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
282    cpu->setArchIntReg(reg_idx, val, thread->threadId());
283
284    // Squash if we're not already in a state update mode.
285    if (!thread->trapPending && !thread->inSyscall) {
286        cpu->squashFromTC(thread->threadId());
287    }
288}
289
290template <class Impl>
291void
292O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
293{
294    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
295    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
296
297    if (!thread->trapPending && !thread->inSyscall) {
298        cpu->squashFromTC(thread->threadId());
299    }
300}
301
302template <class Impl>
303void
304O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
305{
306    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
307    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
308
309    // Squash if we're not already in a state update mode.
310    if (!thread->trapPending && !thread->inSyscall) {
311        cpu->squashFromTC(thread->threadId());
312    }
313}
314
315template <class Impl>
316void
317O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
318{
319    cpu->pcState(val, thread->threadId());
320
321    // Squash if we're not already in a state update mode.
322    if (!thread->trapPending && !thread->inSyscall) {
323        cpu->squashFromTC(thread->threadId());
324    }
325}
326
327#if USE_CHECKER
328template <class Impl>
329void
330O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
331{
332    cpu->pcState(val, thread->threadId());
333
334    // Squash if we're not already in a state update mode.
335    if (!thread->trapPending && !thread->inSyscall) {
336        cpu->squashFromTC(thread->threadId());
337    }
338}
339#endif
340
341template <class Impl>
342int
343O3ThreadContext<Impl>::flattenIntIndex(int reg)
344{
345    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
346}
347
348template <class Impl>
349int
350O3ThreadContext<Impl>::flattenFloatIndex(int reg)
351{
352    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
353}
354
355template <class Impl>
356void
357O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
358{
359    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
360
361    // Squash if we're not already in a state update mode.
362    if (!thread->trapPending && !thread->inSyscall) {
363        cpu->squashFromTC(thread->threadId());
364    }
365}
366
367template <class Impl>
368void
369O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
370{
371    cpu->setMiscReg(misc_reg, val, thread->threadId());
372
373    // Squash if we're not already in a state update mode.
374    if (!thread->trapPending && !thread->inSyscall) {
375        cpu->squashFromTC(thread->threadId());
376    }
377}
378
379