thread_context_impl.hh revision 5082:82dd253231c8
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "arch/regfile.hh" 33#include "cpu/o3/thread_context.hh" 34#include "cpu/quiesce_event.hh" 35 36#if FULL_SYSTEM 37template <class Impl> 38VirtualPort * 39O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc) 40{ 41 if (!src_tc) 42 return thread->getVirtPort(); 43 44 VirtualPort *vp; 45 46 vp = new VirtualPort("tc-vport", src_tc); 47 thread->connectToMemFunc(vp); 48 return vp; 49} 50 51template <class Impl> 52void 53O3ThreadContext<Impl>::dumpFuncProfile() 54{ 55 thread->dumpFuncProfile(); 56} 57#endif 58 59template <class Impl> 60void 61O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 62{ 63 // some things should already be set up 64#if FULL_SYSTEM 65 assert(getSystemPtr() == old_context->getSystemPtr()); 66#else 67 assert(getProcessPtr() == old_context->getProcessPtr()); 68#endif 69 70 // copy over functional state 71 setStatus(old_context->status()); 72 copyArchRegs(old_context); 73 setCpuId(old_context->readCpuId()); 74 75#if !FULL_SYSTEM 76 thread->funcExeInst = old_context->readFuncExeInst(); 77#else 78 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 79 if (other_quiesce) { 80 // Point the quiesce event's TC at this TC so that it wakes up 81 // the proper CPU. 82 other_quiesce->tc = this; 83 } 84 if (thread->quiesceEvent) { 85 thread->quiesceEvent->tc = this; 86 } 87 88 // Transfer kernel stats from one CPU to the other. 89 thread->kernelStats = old_context->getKernelStats(); 90// storeCondFailures = 0; 91 cpu->lockFlag = false; 92#endif 93 94 old_context->setStatus(ThreadContext::Unallocated); 95 96 thread->inSyscall = false; 97 thread->trapPending = false; 98} 99 100#if FULL_SYSTEM 101template <class Impl> 102void 103O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) 104{ 105 if (vp != thread->getVirtPort()) { 106 vp->removeConn(); 107 delete vp; 108 } 109} 110#endif 111 112template <class Impl> 113void 114O3ThreadContext<Impl>::activate(int delay) 115{ 116 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 117 getThreadNum()); 118 119 if (thread->status() == ThreadContext::Active) 120 return; 121 122#if FULL_SYSTEM 123 thread->lastActivate = curTick; 124#endif 125 126 if (thread->status() == ThreadContext::Unallocated) { 127 cpu->activateWhenReady(thread->readTid()); 128 return; 129 } 130 131 thread->setStatus(ThreadContext::Active); 132 133 // status() == Suspended 134 cpu->activateContext(thread->readTid(), delay); 135} 136 137template <class Impl> 138void 139O3ThreadContext<Impl>::suspend() 140{ 141 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 142 getThreadNum()); 143 144 if (thread->status() == ThreadContext::Suspended) 145 return; 146 147#if FULL_SYSTEM 148 thread->lastActivate = curTick; 149 thread->lastSuspend = curTick; 150#endif 151/* 152#if FULL_SYSTEM 153 // Don't change the status from active if there are pending interrupts 154 if (cpu->check_interrupts()) { 155 assert(status() == ThreadContext::Active); 156 return; 157 } 158#endif 159*/ 160 thread->setStatus(ThreadContext::Suspended); 161 cpu->suspendContext(thread->readTid()); 162} 163 164template <class Impl> 165void 166O3ThreadContext<Impl>::deallocate(int delay) 167{ 168 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", 169 getThreadNum(), delay); 170 171 if (thread->status() == ThreadContext::Unallocated) 172 return; 173 174 thread->setStatus(ThreadContext::Unallocated); 175 cpu->deallocateContext(thread->readTid(), true, delay); 176} 177 178template <class Impl> 179void 180O3ThreadContext<Impl>::halt() 181{ 182 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 183 getThreadNum()); 184 185 if (thread->status() == ThreadContext::Halted) 186 return; 187 188 thread->setStatus(ThreadContext::Halted); 189 cpu->haltContext(thread->readTid()); 190} 191 192template <class Impl> 193void 194O3ThreadContext<Impl>::regStats(const std::string &name) 195{ 196#if FULL_SYSTEM 197 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 198 thread->kernelStats->regStats(name + ".kern"); 199#endif 200} 201 202template <class Impl> 203void 204O3ThreadContext<Impl>::serialize(std::ostream &os) 205{ 206#if FULL_SYSTEM 207 if (thread->kernelStats) 208 thread->kernelStats->serialize(os); 209#endif 210 211} 212 213template <class Impl> 214void 215O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 216{ 217#if FULL_SYSTEM 218 if (thread->kernelStats) 219 thread->kernelStats->unserialize(cp, section); 220#endif 221 222} 223 224#if FULL_SYSTEM 225template <class Impl> 226Tick 227O3ThreadContext<Impl>::readLastActivate() 228{ 229 return thread->lastActivate; 230} 231 232template <class Impl> 233Tick 234O3ThreadContext<Impl>::readLastSuspend() 235{ 236 return thread->lastSuspend; 237} 238 239template <class Impl> 240void 241O3ThreadContext<Impl>::profileClear() 242{ 243 thread->profileClear(); 244} 245 246template <class Impl> 247void 248O3ThreadContext<Impl>::profileSample() 249{ 250 thread->profileSample(); 251} 252#endif 253 254template <class Impl> 255TheISA::MachInst 256O3ThreadContext<Impl>:: getInst() 257{ 258 return thread->getInst(); 259} 260 261template <class Impl> 262void 263O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 264{ 265 // This function will mess things up unless the ROB is empty and 266 // there are no instructions in the pipeline. 267 unsigned tid = thread->readTid(); 268 PhysRegIndex renamed_reg; 269 270 // First loop through the integer registers. 271 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 272 renamed_reg = cpu->renameMap[tid].lookup(i); 273 274 DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 275 "now has data %lli.\n", 276 renamed_reg, cpu->readIntReg(renamed_reg), 277 tc->readIntReg(i)); 278 279 cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 280 } 281 282 // Then loop through the floating point registers. 283 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 284 renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 285 cpu->setFloatRegBits(renamed_reg, 286 tc->readFloatRegBits(i)); 287 } 288 289 // Copy the misc regs. 290 TheISA::copyMiscRegs(tc, this); 291 292 // Then finally set the PC and the next PC. 293 cpu->setPC(tc->readPC(), tid); 294 cpu->setNextPC(tc->readNextPC(), tid); 295#if !FULL_SYSTEM 296 this->thread->funcExeInst = tc->readFuncExeInst(); 297#endif 298} 299 300template <class Impl> 301void 302O3ThreadContext<Impl>::clearArchRegs() 303{} 304 305template <class Impl> 306uint64_t 307O3ThreadContext<Impl>::readIntReg(int reg_idx) 308{ 309 reg_idx = TheISA::flattenIntIndex(this, reg_idx); 310 return cpu->readArchIntReg(reg_idx, thread->readTid()); 311} 312 313template <class Impl> 314TheISA::FloatReg 315O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 316{ 317 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 318 switch(width) { 319 case 32: 320 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 321 case 64: 322 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); 323 default: 324 panic("Unsupported width!"); 325 return 0; 326 } 327} 328 329template <class Impl> 330TheISA::FloatReg 331O3ThreadContext<Impl>::readFloatReg(int reg_idx) 332{ 333 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 334 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 335} 336 337template <class Impl> 338TheISA::FloatRegBits 339O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 340{ 341 DPRINTF(Fault, "Reading floatint register through the TC!\n"); 342 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 343 return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 344} 345 346template <class Impl> 347TheISA::FloatRegBits 348O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 349{ 350 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 351 return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 352} 353 354template <class Impl> 355void 356O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 357{ 358 reg_idx = TheISA::flattenIntIndex(this, reg_idx); 359 cpu->setArchIntReg(reg_idx, val, thread->readTid()); 360 361 // Squash if we're not already in a state update mode. 362 if (!thread->trapPending && !thread->inSyscall) { 363 cpu->squashFromTC(thread->readTid()); 364 } 365} 366 367template <class Impl> 368void 369O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 370{ 371 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 372 switch(width) { 373 case 32: 374 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 375 break; 376 case 64: 377 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); 378 break; 379 } 380 381 // Squash if we're not already in a state update mode. 382 if (!thread->trapPending && !thread->inSyscall) { 383 cpu->squashFromTC(thread->readTid()); 384 } 385} 386 387template <class Impl> 388void 389O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 390{ 391 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 392 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 393 394 if (!thread->trapPending && !thread->inSyscall) { 395 cpu->squashFromTC(thread->readTid()); 396 } 397} 398 399template <class Impl> 400void 401O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 402 int width) 403{ 404 DPRINTF(Fault, "Setting floatint register through the TC!\n"); 405 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 406 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 407 408 // Squash if we're not already in a state update mode. 409 if (!thread->trapPending && !thread->inSyscall) { 410 cpu->squashFromTC(thread->readTid()); 411 } 412} 413 414template <class Impl> 415void 416O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 417{ 418 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 419 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 420 421 // Squash if we're not already in a state update mode. 422 if (!thread->trapPending && !thread->inSyscall) { 423 cpu->squashFromTC(thread->readTid()); 424 } 425} 426 427template <class Impl> 428void 429O3ThreadContext<Impl>::setPC(uint64_t val) 430{ 431 cpu->setPC(val, thread->readTid()); 432 433 // Squash if we're not already in a state update mode. 434 if (!thread->trapPending && !thread->inSyscall) { 435 cpu->squashFromTC(thread->readTid()); 436 } 437} 438 439template <class Impl> 440void 441O3ThreadContext<Impl>::setNextPC(uint64_t val) 442{ 443 cpu->setNextPC(val, thread->readTid()); 444 445 // Squash if we're not already in a state update mode. 446 if (!thread->trapPending && !thread->inSyscall) { 447 cpu->squashFromTC(thread->readTid()); 448 } 449} 450 451template <class Impl> 452void 453O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 454{ 455 cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); 456 457 // Squash if we're not already in a state update mode. 458 if (!thread->trapPending && !thread->inSyscall) { 459 cpu->squashFromTC(thread->readTid()); 460 } 461} 462 463template <class Impl> 464void 465O3ThreadContext<Impl>::setMiscReg(int misc_reg, 466 const MiscReg &val) 467{ 468 cpu->setMiscReg(misc_reg, val, thread->readTid()); 469 470 // Squash if we're not already in a state update mode. 471 if (!thread->trapPending && !thread->inSyscall) { 472 cpu->squashFromTC(thread->readTid()); 473 } 474} 475 476#if !FULL_SYSTEM 477 478template <class Impl> 479TheISA::IntReg 480O3ThreadContext<Impl>::getSyscallArg(int i) 481{ 482 return cpu->getSyscallArg(i, thread->readTid()); 483} 484 485template <class Impl> 486void 487O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 488{ 489 cpu->setSyscallArg(i, val, thread->readTid()); 490} 491 492template <class Impl> 493void 494O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 495{ 496 cpu->setSyscallReturn(return_value, thread->readTid()); 497} 498 499#endif // FULL_SYSTEM 500 501