thread_context_impl.hh revision 13611:c8b7847b4171
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408229Snate@binkert.org *
412800Ssaidi@eecs.umich.edu * Authors: Kevin Lim
422289SN/A *          Korey Sewell
432SN/A */
445569Snate@binkert.org
452167SN/A#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
462203SN/A#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
472203SN/A
482222SN/A#include "arch/generic/traits.hh"
492166SN/A#include "arch/kernel_stats.hh"
502203SN/A#include "arch/registers.hh"
512203SN/A#include "config/the_isa.hh"
522222SN/A#include "cpu/o3/thread_context.hh"
532166SN/A#include "cpu/quiesce_event.hh"
542147SN/A#include "debug/O3CPU.hh"
552147SN/A
562222SN/Atemplate <class Impl>
572147SN/AFSTranslatingPortProxy&
582147SN/AO3ThreadContext<Impl>::getVirtProxy()
592147SN/A{
602222SN/A    return thread->getVirtProxy();
612147SN/A}
622147SN/A
632147SN/Atemplate <class Impl>
642222SN/Avoid
652147SN/AO3ThreadContext<Impl>::dumpFuncProfile()
662147SN/A{
672147SN/A    thread->dumpFuncProfile();
682222SN/A}
692147SN/A
702147SN/Atemplate <class Impl>
712147SN/Avoid
722222SN/AO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
732147SN/A{
748405Sksewell@umich.edu    ::takeOverFrom(*this, *old_context);
752147SN/A    TheISA::Decoder *newDecoder = getDecoderPtr();
762222SN/A    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
772147SN/A    newDecoder->takeOverFrom(oldDecoder);
788405Sksewell@umich.edu
792147SN/A    thread->kernelStats = old_context->getKernelStats();
802222SN/A    thread->funcExeInst = old_context->readFuncExeInst();
812147SN/A
822289SN/A    thread->noSquashFromTC = false;
832289SN/A    thread->trapPending = false;
842289SN/A}
852289SN/A
862147SN/Atemplate <class Impl>
872147SN/Avoid
882222SN/AO3ThreadContext<Impl>::activate()
892147SN/A{
902147SN/A    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
912147SN/A            threadId());
922222SN/A
932147SN/A    if (thread->status() == ThreadContext::Active)
942147SN/A        return;
952147SN/A
962222SN/A    thread->lastActivate = curTick();
972147SN/A    thread->setStatus(ThreadContext::Active);
982147SN/A
992147SN/A    // status() == Suspended
1002222SN/A    cpu->activateContext(thread->threadId());
1012147SN/A}
1022147SN/A
1032147SN/Atemplate <class Impl>
1042222SN/Avoid
1052147SN/AO3ThreadContext<Impl>::suspend()
1062147SN/A{
1072147SN/A    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
1082222SN/A            threadId());
1092147SN/A
1102174SN/A    if (thread->status() == ThreadContext::Suspended)
1112174SN/A        return;
1125569Snate@binkert.org
1137678Sgblack@eecs.umich.edu    if (cpu->isDraining()) {
1142174SN/A        DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
1152680Sktlim@umich.edu        return;
1162222SN/A    }
1172174SN/A
1187720Sgblack@eecs.umich.edu    thread->lastActivate = curTick();
1197720Sgblack@eecs.umich.edu    thread->lastSuspend = curTick();
1202196SN/A
1217720Sgblack@eecs.umich.edu    thread->setStatus(ThreadContext::Suspended);
1227720Sgblack@eecs.umich.edu    cpu->suspendContext(thread->threadId());
1232196SN/A}
1242201SN/A
1252196SN/Atemplate <class Impl>
1265568Snate@binkert.orgvoid
1275568Snate@binkert.orgO3ThreadContext<Impl>::halt()
1282196SN/A{
1292196SN/A    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
1307720Sgblack@eecs.umich.edu
1317720Sgblack@eecs.umich.edu    if (thread->status() == ThreadContext::Halted)
1322174SN/A        return;
1332174SN/A
1345569Snate@binkert.org    thread->setStatus(ThreadContext::Halted);
1357678Sgblack@eecs.umich.edu    cpu->haltContext(thread->threadId());
1362201SN/A}
1372680Sktlim@umich.edu
1382201SN/Atemplate <class Impl>
1392201SN/Avoid
1402201SN/AO3ThreadContext<Impl>::regStats(const std::string &name)
1415569Snate@binkert.org{
1427678Sgblack@eecs.umich.edu    if (FullSystem) {
1432289SN/A        thread->kernelStats = new TheISA::Kernel::Statistics();
1442289SN/A        thread->kernelStats->regStats(name + ".kern");
1452289SN/A    }
1462289SN/A}
1472289SN/A
1482289SN/Atemplate <class Impl>
1495569Snate@binkert.orgTick
1506739Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastActivate()
1512289SN/A{
1525568Snate@binkert.org    return thread->lastActivate;
1532289SN/A}
1542289SN/A
1557678Sgblack@eecs.umich.edutemplate <class Impl>
1565568Snate@binkert.orgTick
1577678Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastSuspend()
1587678Sgblack@eecs.umich.edu{
1595569Snate@binkert.org    return thread->lastSuspend;
1602289SN/A}
1612289SN/A
1625568Snate@binkert.orgtemplate <class Impl>
1635568Snate@binkert.orgvoid
1642289SN/AO3ThreadContext<Impl>::profileClear()
1652289SN/A{
1662680Sktlim@umich.edu    thread->profileClear();
1672289SN/A}
1682289SN/A
1695569Snate@binkert.orgtemplate <class Impl>
1707678Sgblack@eecs.umich.eduvoid
1712289SN/AO3ThreadContext<Impl>::profileSample()
1722680Sktlim@umich.edu{
1735568Snate@binkert.org    thread->profileSample();
1745568Snate@binkert.org}
1755569Snate@binkert.org
1762289SN/Atemplate <class Impl>
1772289SN/Avoid
1782680Sktlim@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
1792289SN/A{
1802289SN/A    // Set vector renaming mode before copying registers
1814997Sgblack@eecs.umich.edu    cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
1824997Sgblack@eecs.umich.edu
1835569Snate@binkert.org    // Prevent squashing
1847678Sgblack@eecs.umich.edu    thread->noSquashFromTC = true;
1854997Sgblack@eecs.umich.edu    TheISA::copyRegs(tc, this);
1864997Sgblack@eecs.umich.edu    thread->noSquashFromTC = false;
1875184Sgblack@eecs.umich.edu
1885184Sgblack@eecs.umich.edu    if (!FullSystem)
1895569Snate@binkert.org        this->thread->funcExeInst = tc->readFuncExeInst();
1904997Sgblack@eecs.umich.edu}
1914997Sgblack@eecs.umich.edu
1924997Sgblack@eecs.umich.edutemplate <class Impl>
1935004Sgblack@eecs.umich.eduvoid
1944997Sgblack@eecs.umich.eduO3ThreadContext<Impl>::clearArchRegs()
1954997Sgblack@eecs.umich.edu{
1964997Sgblack@eecs.umich.edu    cpu->isa[thread->threadId()]->clear();
1975569Snate@binkert.org}
1987678Sgblack@eecs.umich.edu
1994997Sgblack@eecs.umich.edutemplate <class Impl>
2004997Sgblack@eecs.umich.eduRegVal
2015184Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
2025184Sgblack@eecs.umich.edu{
2035569Snate@binkert.org    return cpu->readArchIntReg(reg_idx, thread->threadId());
2044997Sgblack@eecs.umich.edu}
2055184Sgblack@eecs.umich.edu
2064997Sgblack@eecs.umich.edutemplate <class Impl>
2075569Snate@binkert.orgRegVal
2084997Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
2094997Sgblack@eecs.umich.edu{
2105004Sgblack@eecs.umich.edu    return cpu->readArchFloatReg(reg_idx, thread->threadId());
2114997Sgblack@eecs.umich.edu}
2124997Sgblack@eecs.umich.edu
2134997Sgblack@eecs.umich.edutemplate <class Impl>
2142174SN/Aconst TheISA::VecRegContainer&
2152174SN/AO3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
2162167SN/A{
2172167SN/A    return cpu->readArchVecReg(reg_id, thread->threadId());
218}
219
220template <class Impl>
221TheISA::VecRegContainer&
222O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
223{
224    return cpu->getWritableArchVecReg(reg_id, thread->threadId());
225}
226
227template <class Impl>
228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230                                           const ElemIndex& elemIndex) const
231{
232    return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
236const TheISA::VecPredRegContainer&
237O3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const
238{
239    return cpu->readArchVecPredReg(reg_id, thread->threadId());
240}
241
242template <class Impl>
243TheISA::VecPredRegContainer&
244O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
245{
246    return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
247}
248
249template <class Impl>
250TheISA::CCReg
251O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
252{
253    return cpu->readArchCCReg(reg_idx, thread->threadId());
254}
255
256template <class Impl>
257void
258O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
259{
260    cpu->setArchIntReg(reg_idx, val, thread->threadId());
261
262    conditionalSquash();
263}
264
265template <class Impl>
266void
267O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val)
268{
269    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
270
271    conditionalSquash();
272}
273
274template <class Impl>
275void
276O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
277{
278    cpu->setArchVecReg(reg_idx, val, thread->threadId());
279
280    conditionalSquash();
281}
282
283template <class Impl>
284void
285O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
286        const ElemIndex& elemIndex, const VecElem& val)
287{
288    cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
289    conditionalSquash();
290}
291
292template <class Impl>
293void
294O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
295                                         const VecPredRegContainer& val)
296{
297    cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
298
299    conditionalSquash();
300}
301
302template <class Impl>
303void
304O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
305{
306    cpu->setArchCCReg(reg_idx, val, thread->threadId());
307
308    conditionalSquash();
309}
310
311template <class Impl>
312void
313O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
314{
315    cpu->pcState(val, thread->threadId());
316
317    conditionalSquash();
318}
319
320template <class Impl>
321void
322O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
323{
324    cpu->pcState(val, thread->threadId());
325
326    conditionalSquash();
327}
328
329template <class Impl>
330RegId
331O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
332{
333    return cpu->isa[thread->threadId()]->flattenRegId(regId);
334}
335
336template <class Impl>
337void
338O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
339{
340    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
341
342    conditionalSquash();
343}
344
345#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
346template <class Impl>
347void
348O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
349{
350    cpu->setMiscReg(misc_reg, val, thread->threadId());
351
352    conditionalSquash();
353}
354
355