thread_context_impl.hh revision 9426
17139Sgblack@eecs.umich.edu/* 27139Sgblack@eecs.umich.edu * Copyright (c) 2010-2012 ARM Limited 37139Sgblack@eecs.umich.edu * All rights reserved 47139Sgblack@eecs.umich.edu * 57139Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67139Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77139Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87139Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97139Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107139Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117139Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127139Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137139Sgblack@eecs.umich.edu * 147139Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 157139Sgblack@eecs.umich.edu * All rights reserved. 167139Sgblack@eecs.umich.edu * 177139Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187139Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197139Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217139Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237139Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247139Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257139Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267139Sgblack@eecs.umich.edu * this software without specific prior written permission. 277139Sgblack@eecs.umich.edu * 287139Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297139Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317139Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327139Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337139Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347139Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357139Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367139Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377139Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387255Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397243Sgblack@eecs.umich.edu * 407243Sgblack@eecs.umich.edu * Authors: Kevin Lim 417255Sgblack@eecs.umich.edu * Korey Sewell 427255Sgblack@eecs.umich.edu */ 437243Sgblack@eecs.umich.edu 447243Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 457255Sgblack@eecs.umich.edu#include "arch/registers.hh" 467255Sgblack@eecs.umich.edu#include "config/the_isa.hh" 477255Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 487255Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 497255Sgblack@eecs.umich.edu#include "debug/O3CPU.hh" 507255Sgblack@eecs.umich.edu 517255Sgblack@eecs.umich.edutemplate <class Impl> 527255Sgblack@eecs.umich.eduFSTranslatingPortProxy& 537255Sgblack@eecs.umich.eduO3ThreadContext<Impl>::getVirtProxy() 547255Sgblack@eecs.umich.edu{ 557255Sgblack@eecs.umich.edu return thread->getVirtProxy(); 567256Sgblack@eecs.umich.edu} 577256Sgblack@eecs.umich.edu 587255Sgblack@eecs.umich.edutemplate <class Impl> 597256Sgblack@eecs.umich.eduvoid 607255Sgblack@eecs.umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 617256Sgblack@eecs.umich.edu{ 627255Sgblack@eecs.umich.edu thread->dumpFuncProfile(); 637255Sgblack@eecs.umich.edu} 647258Sgblack@eecs.umich.edu 657258Sgblack@eecs.umich.edutemplate <class Impl> 667255Sgblack@eecs.umich.eduvoid 677258Sgblack@eecs.umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 687255Sgblack@eecs.umich.edu{ 697258Sgblack@eecs.umich.edu // some things should already be set up 707255Sgblack@eecs.umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 717243Sgblack@eecs.umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 727255Sgblack@eecs.umich.edu 737243Sgblack@eecs.umich.edu // copy over functional state 747243Sgblack@eecs.umich.edu setStatus(old_context->status()); 757243Sgblack@eecs.umich.edu copyArchRegs(old_context); 767243Sgblack@eecs.umich.edu setContextId(old_context->contextId()); 777139Sgblack@eecs.umich.edu setThreadId(old_context->threadId()); 787188Sgblack@eecs.umich.edu 797188Sgblack@eecs.umich.edu if (FullSystem) { 807188Sgblack@eecs.umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 817188Sgblack@eecs.umich.edu if (other_quiesce) { 827188Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 837139Sgblack@eecs.umich.edu // the proper CPU. 847139Sgblack@eecs.umich.edu other_quiesce->tc = this; 857139Sgblack@eecs.umich.edu } 867139Sgblack@eecs.umich.edu if (thread->quiesceEvent) { 877188Sgblack@eecs.umich.edu thread->quiesceEvent->tc = this; 887188Sgblack@eecs.umich.edu } 897188Sgblack@eecs.umich.edu 907188Sgblack@eecs.umich.edu // Transfer kernel stats from one CPU to the other. 917188Sgblack@eecs.umich.edu thread->kernelStats = old_context->getKernelStats(); 927188Sgblack@eecs.umich.edu cpu->lockFlag = false; 937139Sgblack@eecs.umich.edu } else { 947146Sgblack@eecs.umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 957141Sgblack@eecs.umich.edu } 967139Sgblack@eecs.umich.edu 977139Sgblack@eecs.umich.edu old_context->setStatus(ThreadContext::Halted); 987139Sgblack@eecs.umich.edu 997146Sgblack@eecs.umich.edu thread->noSquashFromTC = false; 1007141Sgblack@eecs.umich.edu thread->trapPending = false; 1017139Sgblack@eecs.umich.edu} 1027146Sgblack@eecs.umich.edu 1037141Sgblack@eecs.umich.edutemplate <class Impl> 1047139Sgblack@eecs.umich.eduvoid 1057139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::activate(Cycles delay) 1067139Sgblack@eecs.umich.edu{ 1077139Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1087139Sgblack@eecs.umich.edu threadId()); 1097188Sgblack@eecs.umich.edu 1107188Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Active) 1117188Sgblack@eecs.umich.edu return; 1127188Sgblack@eecs.umich.edu 1137188Sgblack@eecs.umich.edu thread->lastActivate = curTick(); 1147188Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Active); 1157188Sgblack@eecs.umich.edu 1167188Sgblack@eecs.umich.edu // status() == Suspended 1177188Sgblack@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1187188Sgblack@eecs.umich.edu} 1197188Sgblack@eecs.umich.edu 1207188Sgblack@eecs.umich.edutemplate <class Impl> 1217188Sgblack@eecs.umich.eduvoid 1227188Sgblack@eecs.umich.eduO3ThreadContext<Impl>::suspend(Cycles delay) 1237188Sgblack@eecs.umich.edu{ 1247188Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1257188Sgblack@eecs.umich.edu threadId()); 1267188Sgblack@eecs.umich.edu 1277188Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Suspended) 1287188Sgblack@eecs.umich.edu return; 1297139Sgblack@eecs.umich.edu 1307139Sgblack@eecs.umich.edu thread->lastActivate = curTick(); 1317139Sgblack@eecs.umich.edu thread->lastSuspend = curTick(); 1327139Sgblack@eecs.umich.edu 1337139Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Suspended); 1347139Sgblack@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1357139Sgblack@eecs.umich.edu} 1367139Sgblack@eecs.umich.edu 1377139Sgblack@eecs.umich.edutemplate <class Impl> 1387139Sgblack@eecs.umich.eduvoid 1397139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::halt(Cycles delay) 1407139Sgblack@eecs.umich.edu{ 1417139Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1427139Sgblack@eecs.umich.edu threadId()); 1437139Sgblack@eecs.umich.edu 1447139Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Halted) 1457139Sgblack@eecs.umich.edu return; 1467139Sgblack@eecs.umich.edu 1477139Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Halted); 1487139Sgblack@eecs.umich.edu cpu->haltContext(thread->threadId()); 1497139Sgblack@eecs.umich.edu} 1507188Sgblack@eecs.umich.edu 1517188Sgblack@eecs.umich.edutemplate <class Impl> 1527188Sgblack@eecs.umich.eduvoid 1537188Sgblack@eecs.umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1547139Sgblack@eecs.umich.edu{ 1557188Sgblack@eecs.umich.edu if (FullSystem) { 1567139Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1577188Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1587139Sgblack@eecs.umich.edu } 1597139Sgblack@eecs.umich.edu} 1607139Sgblack@eecs.umich.edu 1617139Sgblack@eecs.umich.edutemplate <class Impl> 1627139Sgblack@eecs.umich.eduvoid 1637139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1647139Sgblack@eecs.umich.edu{ 1657139Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1667210Sgblack@eecs.umich.edu thread->kernelStats->serialize(os); 1677210Sgblack@eecs.umich.edu} 1687210Sgblack@eecs.umich.edu 1697210Sgblack@eecs.umich.edutemplate <class Impl> 1707210Sgblack@eecs.umich.eduvoid 1717210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1727210Sgblack@eecs.umich.edu{ 1737227Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1747227Sgblack@eecs.umich.edu thread->kernelStats->unserialize(cp, section); 1757227Sgblack@eecs.umich.edu} 1767227Sgblack@eecs.umich.edu 1777227Sgblack@eecs.umich.edutemplate <class Impl> 1787227Sgblack@eecs.umich.eduTick 1797227Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastActivate() 1807227Sgblack@eecs.umich.edu{ 1817210Sgblack@eecs.umich.edu return thread->lastActivate; 1827237Sgblack@eecs.umich.edu} 1837237Sgblack@eecs.umich.edu 1847237Sgblack@eecs.umich.edutemplate <class Impl> 1857237Sgblack@eecs.umich.eduTick 1867237Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastSuspend() 1877237Sgblack@eecs.umich.edu{ 1887237Sgblack@eecs.umich.edu return thread->lastSuspend; 1897210Sgblack@eecs.umich.edu} 1907227Sgblack@eecs.umich.edu 1917210Sgblack@eecs.umich.edutemplate <class Impl> 1927227Sgblack@eecs.umich.eduvoid 1937210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileClear() 1947210Sgblack@eecs.umich.edu{ 1957210Sgblack@eecs.umich.edu thread->profileClear(); 1967210Sgblack@eecs.umich.edu} 1977210Sgblack@eecs.umich.edu 1987240Sgblack@eecs.umich.edutemplate <class Impl> 1997235Sgblack@eecs.umich.eduvoid 2007235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileSample() 2017235Sgblack@eecs.umich.edu{ 2027235Sgblack@eecs.umich.edu thread->profileSample(); 2037235Sgblack@eecs.umich.edu} 2047235Sgblack@eecs.umich.edu 2057240Sgblack@eecs.umich.edutemplate <class Impl> 2067240Sgblack@eecs.umich.eduvoid 2077240Sgblack@eecs.umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2087240Sgblack@eecs.umich.edu{ 2097240Sgblack@eecs.umich.edu // Prevent squashing 2107240Sgblack@eecs.umich.edu thread->noSquashFromTC = true; 2117240Sgblack@eecs.umich.edu TheISA::copyRegs(tc, this); 2127240Sgblack@eecs.umich.edu thread->noSquashFromTC = false; 2137240Sgblack@eecs.umich.edu 2147240Sgblack@eecs.umich.edu if (!FullSystem) 2157210Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2167210Sgblack@eecs.umich.edu} 2177210Sgblack@eecs.umich.edu 2187210Sgblack@eecs.umich.edutemplate <class Impl> 2197210Sgblack@eecs.umich.eduvoid 2207227Sgblack@eecs.umich.eduO3ThreadContext<Impl>::clearArchRegs() 2217227Sgblack@eecs.umich.edu{ 2227227Sgblack@eecs.umich.edu cpu->isa[thread->threadId()]->clear(); 2237227Sgblack@eecs.umich.edu} 2247227Sgblack@eecs.umich.edu 2257227Sgblack@eecs.umich.edutemplate <class Impl> 2267210Sgblack@eecs.umich.eduuint64_t 2277235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 2287235Sgblack@eecs.umich.edu{ 2297235Sgblack@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2307235Sgblack@eecs.umich.edu} 2317235Sgblack@eecs.umich.edu 2327235Sgblack@eecs.umich.edutemplate <class Impl> 2337235Sgblack@eecs.umich.eduTheISA::FloatReg 2347235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 2357210Sgblack@eecs.umich.edu{ 2367235Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2377210Sgblack@eecs.umich.edu} 2387235Sgblack@eecs.umich.edu 2397210Sgblack@eecs.umich.edutemplate <class Impl> 2407210Sgblack@eecs.umich.eduTheISA::FloatRegBits 2417210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) 2427210Sgblack@eecs.umich.edu{ 2437210Sgblack@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2447211Sgblack@eecs.umich.edu} 2457211Sgblack@eecs.umich.edu 2467211Sgblack@eecs.umich.edutemplate <class Impl> 2477210Sgblack@eecs.umich.eduvoid 2487235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) 2497235Sgblack@eecs.umich.edu{ 2507235Sgblack@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2517235Sgblack@eecs.umich.edu 2527235Sgblack@eecs.umich.edu conditionalSquash(); 2537235Sgblack@eecs.umich.edu} 2547235Sgblack@eecs.umich.edu 2557235Sgblack@eecs.umich.edutemplate <class Impl> 2567210Sgblack@eecs.umich.eduvoid 2577235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val) 2587210Sgblack@eecs.umich.edu{ 2597235Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2607210Sgblack@eecs.umich.edu 2617210Sgblack@eecs.umich.edu conditionalSquash(); 2627211Sgblack@eecs.umich.edu} 2637211Sgblack@eecs.umich.edu 2647211Sgblack@eecs.umich.edutemplate <class Impl> 2657210Sgblack@eecs.umich.eduvoid 2667210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) 2677210Sgblack@eecs.umich.edu{ 2687210Sgblack@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 2697235Sgblack@eecs.umich.edu 2707235Sgblack@eecs.umich.edu conditionalSquash(); 2717235Sgblack@eecs.umich.edu} 2727235Sgblack@eecs.umich.edu 2737235Sgblack@eecs.umich.edutemplate <class Impl> 2747235Sgblack@eecs.umich.eduvoid 2757235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 2767235Sgblack@eecs.umich.edu{ 2777210Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 2787235Sgblack@eecs.umich.edu 2797210Sgblack@eecs.umich.edu conditionalSquash(); 2807235Sgblack@eecs.umich.edu} 2817210Sgblack@eecs.umich.edu 2827210Sgblack@eecs.umich.edutemplate <class Impl> 2837210Sgblack@eecs.umich.eduvoid 2847210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 2857210Sgblack@eecs.umich.edu{ 2867227Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 2877227Sgblack@eecs.umich.edu 2887227Sgblack@eecs.umich.edu conditionalSquash(); 2897227Sgblack@eecs.umich.edu} 2907227Sgblack@eecs.umich.edu 2917227Sgblack@eecs.umich.edutemplate <class Impl> 2927210Sgblack@eecs.umich.eduint 2937235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 2947235Sgblack@eecs.umich.edu{ 2957235Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()]->flattenIntIndex(reg); 2967235Sgblack@eecs.umich.edu} 2977235Sgblack@eecs.umich.edu 2987235Sgblack@eecs.umich.edutemplate <class Impl> 2997235Sgblack@eecs.umich.eduint 3007235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3017210Sgblack@eecs.umich.edu{ 3027235Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); 3037210Sgblack@eecs.umich.edu} 3047235Sgblack@eecs.umich.edu 3057210Sgblack@eecs.umich.edutemplate <class Impl> 3067210Sgblack@eecs.umich.eduvoid 3077210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3087210Sgblack@eecs.umich.edu{ 3097250Sgblack@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3107235Sgblack@eecs.umich.edu 3117235Sgblack@eecs.umich.edu conditionalSquash(); 3127235Sgblack@eecs.umich.edu} 3137235Sgblack@eecs.umich.edu 3147235Sgblack@eecs.umich.edutemplate <class Impl> 3157235Sgblack@eecs.umich.eduvoid 3167250Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 3177250Sgblack@eecs.umich.edu{ 3187250Sgblack@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3197250Sgblack@eecs.umich.edu 3207250Sgblack@eecs.umich.edu conditionalSquash(); 3217250Sgblack@eecs.umich.edu} 3227250Sgblack@eecs.umich.edu 3237250Sgblack@eecs.umich.edu