thread_context_impl.hh revision 9180
12817Sksewell@umich.edu/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37763SAli.Saidi@ARM.com * All rights reserved 47763SAli.Saidi@ARM.com * 57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137763SAli.Saidi@ARM.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu * Korey Sewell 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 448793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 456329Sgblack@eecs.umich.edu#include "arch/registers.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 472817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 482834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 498232Snate@binkert.org#include "debug/O3CPU.hh" 502817Sksewell@umich.edu 512817Sksewell@umich.edutemplate <class Impl> 528852Sandreas.hansson@arm.comFSTranslatingPortProxy& 538706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 542817Sksewell@umich.edu{ 558706Sandreas.hansson@arm.com return thread->getVirtProxy(); 562817Sksewell@umich.edu} 572817Sksewell@umich.edu 582817Sksewell@umich.edutemplate <class Impl> 592817Sksewell@umich.eduvoid 602817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 612817Sksewell@umich.edu{ 623126Sktlim@umich.edu thread->dumpFuncProfile(); 632817Sksewell@umich.edu} 642817Sksewell@umich.edu 652817Sksewell@umich.edutemplate <class Impl> 662817Sksewell@umich.eduvoid 672817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 682817Sksewell@umich.edu{ 692817Sksewell@umich.edu // some things should already be set up 702817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 712817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 722817Sksewell@umich.edu 732817Sksewell@umich.edu // copy over functional state 742817Sksewell@umich.edu setStatus(old_context->status()); 752817Sksewell@umich.edu copyArchRegs(old_context); 765714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 775715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 782817Sksewell@umich.edu 798793Sgblack@eecs.umich.edu if (FullSystem) { 808793Sgblack@eecs.umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 818793Sgblack@eecs.umich.edu if (other_quiesce) { 828793Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 838793Sgblack@eecs.umich.edu // the proper CPU. 848793Sgblack@eecs.umich.edu other_quiesce->tc = this; 858793Sgblack@eecs.umich.edu } 868793Sgblack@eecs.umich.edu if (thread->quiesceEvent) { 878793Sgblack@eecs.umich.edu thread->quiesceEvent->tc = this; 888793Sgblack@eecs.umich.edu } 898793Sgblack@eecs.umich.edu 908793Sgblack@eecs.umich.edu // Transfer kernel stats from one CPU to the other. 918793Sgblack@eecs.umich.edu thread->kernelStats = old_context->getKernelStats(); 928793Sgblack@eecs.umich.edu cpu->lockFlag = false; 938793Sgblack@eecs.umich.edu } else { 948793Sgblack@eecs.umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 952817Sksewell@umich.edu } 962817Sksewell@umich.edu 976029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 982817Sksewell@umich.edu 992817Sksewell@umich.edu thread->inSyscall = false; 1002817Sksewell@umich.edu thread->trapPending = false; 1012817Sksewell@umich.edu} 1022817Sksewell@umich.edu 1032817Sksewell@umich.edutemplate <class Impl> 1042817Sksewell@umich.eduvoid 1059180Sandreas.hansson@arm.comO3ThreadContext<Impl>::activate(Cycles delay) 1062817Sksewell@umich.edu{ 1072875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1085715Shsul@eecs.umich.edu threadId()); 1092817Sksewell@umich.edu 1102817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1112817Sksewell@umich.edu return; 1122817Sksewell@umich.edu 1137823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1142817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1152817Sksewell@umich.edu 1162817Sksewell@umich.edu // status() == Suspended 1175715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1182817Sksewell@umich.edu} 1192817Sksewell@umich.edu 1202817Sksewell@umich.edutemplate <class Impl> 1212817Sksewell@umich.eduvoid 1229180Sandreas.hansson@arm.comO3ThreadContext<Impl>::suspend(Cycles delay) 1232817Sksewell@umich.edu{ 1242875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1255715Shsul@eecs.umich.edu threadId()); 1262817Sksewell@umich.edu 1272817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1282817Sksewell@umich.edu return; 1292817Sksewell@umich.edu 1307823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1317823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1328793Sgblack@eecs.umich.edu 1332817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1345715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1352817Sksewell@umich.edu} 1362817Sksewell@umich.edu 1372817Sksewell@umich.edutemplate <class Impl> 1382817Sksewell@umich.eduvoid 1399180Sandreas.hansson@arm.comO3ThreadContext<Impl>::halt(Cycles delay) 1402817Sksewell@umich.edu{ 1412875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1425715Shsul@eecs.umich.edu threadId()); 1432817Sksewell@umich.edu 1442817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1452817Sksewell@umich.edu return; 1462817Sksewell@umich.edu 1472817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1485715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1492817Sksewell@umich.edu} 1502817Sksewell@umich.edu 1512817Sksewell@umich.edutemplate <class Impl> 1522817Sksewell@umich.eduvoid 1532817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1542817Sksewell@umich.edu{ 1558793Sgblack@eecs.umich.edu if (FullSystem) { 1568793Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1578793Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1588793Sgblack@eecs.umich.edu } 1592817Sksewell@umich.edu} 1602817Sksewell@umich.edu 1612817Sksewell@umich.edutemplate <class Impl> 1622817Sksewell@umich.eduvoid 1632817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1642817Sksewell@umich.edu{ 1658793Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1662817Sksewell@umich.edu thread->kernelStats->serialize(os); 1672817Sksewell@umich.edu} 1682817Sksewell@umich.edu 1692817Sksewell@umich.edutemplate <class Impl> 1702817Sksewell@umich.eduvoid 1712817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1722817Sksewell@umich.edu{ 1738793Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1742817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1752817Sksewell@umich.edu} 1762817Sksewell@umich.edu 1772817Sksewell@umich.edutemplate <class Impl> 1782817Sksewell@umich.eduTick 1792817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1802817Sksewell@umich.edu{ 1812817Sksewell@umich.edu return thread->lastActivate; 1822817Sksewell@umich.edu} 1832817Sksewell@umich.edu 1842817Sksewell@umich.edutemplate <class Impl> 1852817Sksewell@umich.eduTick 1862817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1872817Sksewell@umich.edu{ 1882817Sksewell@umich.edu return thread->lastSuspend; 1892817Sksewell@umich.edu} 1902817Sksewell@umich.edu 1912817Sksewell@umich.edutemplate <class Impl> 1922817Sksewell@umich.eduvoid 1932817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 1943126Sktlim@umich.edu{ 1953126Sktlim@umich.edu thread->profileClear(); 1963126Sktlim@umich.edu} 1972817Sksewell@umich.edu 1982817Sksewell@umich.edutemplate <class Impl> 1992817Sksewell@umich.eduvoid 2002817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2013126Sktlim@umich.edu{ 2023126Sktlim@umich.edu thread->profileSample(); 2033126Sktlim@umich.edu} 2042817Sksewell@umich.edu 2052817Sksewell@umich.edutemplate <class Impl> 2062817Sksewell@umich.eduvoid 2072817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2082817Sksewell@umich.edu{ 2098208SAli.Saidi@ARM.com // Prevent squashing 2108208SAli.Saidi@ARM.com thread->inSyscall = true; 2118208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 2128208SAli.Saidi@ARM.com thread->inSyscall = false; 2132817Sksewell@umich.edu 2148793Sgblack@eecs.umich.edu if (!FullSystem) 2158793Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2162817Sksewell@umich.edu} 2172817Sksewell@umich.edu 2182817Sksewell@umich.edutemplate <class Impl> 2192817Sksewell@umich.eduvoid 2202817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2217763SAli.Saidi@ARM.com{ 2227763SAli.Saidi@ARM.com cpu->isa[thread->threadId()].clear(); 2237763SAli.Saidi@ARM.com} 2242817Sksewell@umich.edu 2252817Sksewell@umich.edutemplate <class Impl> 2262817Sksewell@umich.eduuint64_t 2272817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2282817Sksewell@umich.edu{ 2296313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2305715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2312817Sksewell@umich.edu} 2322817Sksewell@umich.edu 2332817Sksewell@umich.edutemplate <class Impl> 2342986Sgblack@eecs.umich.eduTheISA::FloatReg 2352817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2362817Sksewell@umich.edu{ 2376313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2386314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2392817Sksewell@umich.edu} 2402817Sksewell@umich.edu 2412817Sksewell@umich.edutemplate <class Impl> 2422986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2432817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2442817Sksewell@umich.edu{ 2456313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2465715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2472817Sksewell@umich.edu} 2482817Sksewell@umich.edu 2492817Sksewell@umich.edutemplate <class Impl> 2502817Sksewell@umich.eduvoid 2512817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2522817Sksewell@umich.edu{ 2536313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2545715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2552817Sksewell@umich.edu 2562817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2572817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2585715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2592817Sksewell@umich.edu } 2602817Sksewell@umich.edu} 2612817Sksewell@umich.edu 2622817Sksewell@umich.edutemplate <class Impl> 2632817Sksewell@umich.eduvoid 2642817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 2652817Sksewell@umich.edu{ 2666313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2676314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2682817Sksewell@umich.edu 2692817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2705715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2712817Sksewell@umich.edu } 2722817Sksewell@umich.edu} 2732817Sksewell@umich.edu 2742817Sksewell@umich.edutemplate <class Impl> 2752817Sksewell@umich.eduvoid 2762817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 2772817Sksewell@umich.edu{ 2786313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2795715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 2802817Sksewell@umich.edu 2812817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2822817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2835715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2842817Sksewell@umich.edu } 2852817Sksewell@umich.edu} 2862817Sksewell@umich.edu 2872817Sksewell@umich.edutemplate <class Impl> 2882817Sksewell@umich.eduvoid 2897720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 2902817Sksewell@umich.edu{ 2917720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 2925258Sksewell@umich.edu 2935258Sksewell@umich.edu // Squash if we're not already in a state update mode. 2945258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2955715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2965258Sksewell@umich.edu } 2975258Sksewell@umich.edu} 2985258Sksewell@umich.edu 2998733Sgeoffrey.blake@arm.comtemplate <class Impl> 3008733Sgeoffrey.blake@arm.comvoid 3018733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 3028733Sgeoffrey.blake@arm.com{ 3038733Sgeoffrey.blake@arm.com cpu->pcState(val, thread->threadId()); 3048733Sgeoffrey.blake@arm.com 3058733Sgeoffrey.blake@arm.com // Squash if we're not already in a state update mode. 3068733Sgeoffrey.blake@arm.com if (!thread->trapPending && !thread->inSyscall) { 3078733Sgeoffrey.blake@arm.com cpu->squashFromTC(thread->threadId()); 3088733Sgeoffrey.blake@arm.com } 3098733Sgeoffrey.blake@arm.com} 3108733Sgeoffrey.blake@arm.com 3115258Sksewell@umich.edutemplate <class Impl> 3126313Sgblack@eecs.umich.eduint 3136313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3146313Sgblack@eecs.umich.edu{ 3156313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3166313Sgblack@eecs.umich.edu} 3176313Sgblack@eecs.umich.edu 3186313Sgblack@eecs.umich.edutemplate <class Impl> 3196313Sgblack@eecs.umich.eduint 3206313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3216313Sgblack@eecs.umich.edu{ 3226313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3236313Sgblack@eecs.umich.edu} 3246313Sgblack@eecs.umich.edu 3256313Sgblack@eecs.umich.edutemplate <class Impl> 3265258Sksewell@umich.eduvoid 3274172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3282817Sksewell@umich.edu{ 3295715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3302817Sksewell@umich.edu 3312817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3322817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3335715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3342817Sksewell@umich.edu } 3352817Sksewell@umich.edu} 3362817Sksewell@umich.edu 3372817Sksewell@umich.edutemplate <class Impl> 3383468Sgblack@eecs.umich.eduvoid 3398518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 3402817Sksewell@umich.edu{ 3415715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3422817Sksewell@umich.edu 3432817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3442817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3455715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3462817Sksewell@umich.edu } 3472817Sksewell@umich.edu} 3482817Sksewell@umich.edu 349