thread_context_impl.hh revision 8706
12817Sksewell@umich.edu/* 27763SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37763SAli.Saidi@ARM.com * All rights reserved 47763SAli.Saidi@ARM.com * 57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137763SAli.Saidi@ARM.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu * Korey Sewell 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 446329Sgblack@eecs.umich.edu#include "arch/registers.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 472834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 488232Snate@binkert.org#include "debug/O3CPU.hh" 492817Sksewell@umich.edu 502817Sksewell@umich.edu#if FULL_SYSTEM 512817Sksewell@umich.edutemplate <class Impl> 528706Sandreas.hansson@arm.comFSTranslatingPortProxy* 538706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 542817Sksewell@umich.edu{ 558706Sandreas.hansson@arm.com return thread->getVirtProxy(); 562817Sksewell@umich.edu} 572817Sksewell@umich.edu 582817Sksewell@umich.edutemplate <class Impl> 592817Sksewell@umich.eduvoid 602817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 612817Sksewell@umich.edu{ 623126Sktlim@umich.edu thread->dumpFuncProfile(); 632817Sksewell@umich.edu} 642817Sksewell@umich.edu#endif 652817Sksewell@umich.edu 662817Sksewell@umich.edutemplate <class Impl> 672817Sksewell@umich.eduvoid 682817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 692817Sksewell@umich.edu{ 702817Sksewell@umich.edu // some things should already be set up 717467Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 722817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 737467Stjones1@inf.ed.ac.uk#else 742817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 752817Sksewell@umich.edu#endif 762817Sksewell@umich.edu 772817Sksewell@umich.edu // copy over functional state 782817Sksewell@umich.edu setStatus(old_context->status()); 792817Sksewell@umich.edu copyArchRegs(old_context); 805714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 815715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 822817Sksewell@umich.edu 832817Sksewell@umich.edu#if !FULL_SYSTEM 842817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 852817Sksewell@umich.edu#else 862817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 872817Sksewell@umich.edu if (other_quiesce) { 882817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 892817Sksewell@umich.edu // the proper CPU. 902817Sksewell@umich.edu other_quiesce->tc = this; 912817Sksewell@umich.edu } 922817Sksewell@umich.edu if (thread->quiesceEvent) { 932817Sksewell@umich.edu thread->quiesceEvent->tc = this; 942817Sksewell@umich.edu } 952817Sksewell@umich.edu 962817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 972817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 982817Sksewell@umich.edu// storeCondFailures = 0; 992817Sksewell@umich.edu cpu->lockFlag = false; 1002817Sksewell@umich.edu#endif 1012817Sksewell@umich.edu 1026029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 1032817Sksewell@umich.edu 1042817Sksewell@umich.edu thread->inSyscall = false; 1052817Sksewell@umich.edu thread->trapPending = false; 1062817Sksewell@umich.edu} 1072817Sksewell@umich.edu 1082817Sksewell@umich.edutemplate <class Impl> 1092817Sksewell@umich.eduvoid 1102817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 1112817Sksewell@umich.edu{ 1122875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1135715Shsul@eecs.umich.edu threadId()); 1142817Sksewell@umich.edu 1152817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1162817Sksewell@umich.edu return; 1172817Sksewell@umich.edu 1182817Sksewell@umich.edu#if FULL_SYSTEM 1197823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1202817Sksewell@umich.edu#endif 1212817Sksewell@umich.edu 1222817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1232817Sksewell@umich.edu 1242817Sksewell@umich.edu // status() == Suspended 1255715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1262817Sksewell@umich.edu} 1272817Sksewell@umich.edu 1282817Sksewell@umich.edutemplate <class Impl> 1292817Sksewell@umich.eduvoid 1305250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1312817Sksewell@umich.edu{ 1322875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1335715Shsul@eecs.umich.edu threadId()); 1342817Sksewell@umich.edu 1352817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1362817Sksewell@umich.edu return; 1372817Sksewell@umich.edu 1382817Sksewell@umich.edu#if FULL_SYSTEM 1397823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1407823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1412817Sksewell@umich.edu#endif 1422817Sksewell@umich.edu/* 1432817Sksewell@umich.edu#if FULL_SYSTEM 1442817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1455704Snate@binkert.org if (cpu->checkInterrupts()) { 1462817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1472817Sksewell@umich.edu return; 1482817Sksewell@umich.edu } 1492817Sksewell@umich.edu#endif 1502817Sksewell@umich.edu*/ 1512817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1525715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1532817Sksewell@umich.edu} 1542817Sksewell@umich.edu 1552817Sksewell@umich.edutemplate <class Impl> 1562817Sksewell@umich.eduvoid 1575250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1582817Sksewell@umich.edu{ 1592875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1605715Shsul@eecs.umich.edu threadId()); 1612817Sksewell@umich.edu 1622817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1632817Sksewell@umich.edu return; 1642817Sksewell@umich.edu 1652817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1665715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1672817Sksewell@umich.edu} 1682817Sksewell@umich.edu 1692817Sksewell@umich.edutemplate <class Impl> 1702817Sksewell@umich.eduvoid 1712817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1722817Sksewell@umich.edu{ 1732817Sksewell@umich.edu#if FULL_SYSTEM 1743548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1752817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1762817Sksewell@umich.edu#endif 1772817Sksewell@umich.edu} 1782817Sksewell@umich.edu 1792817Sksewell@umich.edutemplate <class Impl> 1802817Sksewell@umich.eduvoid 1812817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1822817Sksewell@umich.edu{ 1832817Sksewell@umich.edu#if FULL_SYSTEM 1842817Sksewell@umich.edu if (thread->kernelStats) 1852817Sksewell@umich.edu thread->kernelStats->serialize(os); 1862817Sksewell@umich.edu#endif 1872817Sksewell@umich.edu 1882817Sksewell@umich.edu} 1892817Sksewell@umich.edu 1902817Sksewell@umich.edutemplate <class Impl> 1912817Sksewell@umich.eduvoid 1922817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1932817Sksewell@umich.edu{ 1942817Sksewell@umich.edu#if FULL_SYSTEM 1952817Sksewell@umich.edu if (thread->kernelStats) 1962817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1972817Sksewell@umich.edu#endif 1982817Sksewell@umich.edu 1992817Sksewell@umich.edu} 2002817Sksewell@umich.edu 2012817Sksewell@umich.edu#if FULL_SYSTEM 2022817Sksewell@umich.edutemplate <class Impl> 2032817Sksewell@umich.eduTick 2042817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2052817Sksewell@umich.edu{ 2062817Sksewell@umich.edu return thread->lastActivate; 2072817Sksewell@umich.edu} 2082817Sksewell@umich.edu 2092817Sksewell@umich.edutemplate <class Impl> 2102817Sksewell@umich.eduTick 2112817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2122817Sksewell@umich.edu{ 2132817Sksewell@umich.edu return thread->lastSuspend; 2142817Sksewell@umich.edu} 2152817Sksewell@umich.edu 2162817Sksewell@umich.edutemplate <class Impl> 2172817Sksewell@umich.eduvoid 2182817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2193126Sktlim@umich.edu{ 2203126Sktlim@umich.edu thread->profileClear(); 2213126Sktlim@umich.edu} 2222817Sksewell@umich.edu 2232817Sksewell@umich.edutemplate <class Impl> 2242817Sksewell@umich.eduvoid 2252817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2263126Sktlim@umich.edu{ 2273126Sktlim@umich.edu thread->profileSample(); 2283126Sktlim@umich.edu} 2292817Sksewell@umich.edu#endif 2302817Sksewell@umich.edu 2312817Sksewell@umich.edutemplate <class Impl> 2322817Sksewell@umich.eduvoid 2332817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2342817Sksewell@umich.edu{ 2358208SAli.Saidi@ARM.com // Prevent squashing 2368208SAli.Saidi@ARM.com thread->inSyscall = true; 2378208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 2388208SAli.Saidi@ARM.com thread->inSyscall = false; 2392817Sksewell@umich.edu 2402817Sksewell@umich.edu#if !FULL_SYSTEM 2412817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2422817Sksewell@umich.edu#endif 2432817Sksewell@umich.edu} 2442817Sksewell@umich.edu 2452817Sksewell@umich.edutemplate <class Impl> 2462817Sksewell@umich.eduvoid 2472817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2487763SAli.Saidi@ARM.com{ 2497763SAli.Saidi@ARM.com cpu->isa[thread->threadId()].clear(); 2507763SAli.Saidi@ARM.com} 2512817Sksewell@umich.edu 2522817Sksewell@umich.edutemplate <class Impl> 2532817Sksewell@umich.eduuint64_t 2542817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2552817Sksewell@umich.edu{ 2566313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2575715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2582817Sksewell@umich.edu} 2592817Sksewell@umich.edu 2602817Sksewell@umich.edutemplate <class Impl> 2612986Sgblack@eecs.umich.eduTheISA::FloatReg 2622817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2632817Sksewell@umich.edu{ 2646313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2656314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2662817Sksewell@umich.edu} 2672817Sksewell@umich.edu 2682817Sksewell@umich.edutemplate <class Impl> 2692986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2702817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2712817Sksewell@umich.edu{ 2726313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2735715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2742817Sksewell@umich.edu} 2752817Sksewell@umich.edu 2762817Sksewell@umich.edutemplate <class Impl> 2772817Sksewell@umich.eduvoid 2782817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2792817Sksewell@umich.edu{ 2806313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2815715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2822817Sksewell@umich.edu 2832817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2842817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2855715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2862817Sksewell@umich.edu } 2872817Sksewell@umich.edu} 2882817Sksewell@umich.edu 2892817Sksewell@umich.edutemplate <class Impl> 2902817Sksewell@umich.eduvoid 2912817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 2922817Sksewell@umich.edu{ 2936313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2946314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2952817Sksewell@umich.edu 2962817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2975715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2982817Sksewell@umich.edu } 2992817Sksewell@umich.edu} 3002817Sksewell@umich.edu 3012817Sksewell@umich.edutemplate <class Impl> 3022817Sksewell@umich.eduvoid 3032817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3042817Sksewell@umich.edu{ 3056313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3065715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3072817Sksewell@umich.edu 3082817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3092817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3105715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3112817Sksewell@umich.edu } 3122817Sksewell@umich.edu} 3132817Sksewell@umich.edu 3142817Sksewell@umich.edutemplate <class Impl> 3152817Sksewell@umich.eduvoid 3167720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3172817Sksewell@umich.edu{ 3187720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3195258Sksewell@umich.edu 3205258Sksewell@umich.edu // Squash if we're not already in a state update mode. 3215258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3225715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3235258Sksewell@umich.edu } 3245258Sksewell@umich.edu} 3255258Sksewell@umich.edu 3265258Sksewell@umich.edutemplate <class Impl> 3276313Sgblack@eecs.umich.eduint 3286313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3296313Sgblack@eecs.umich.edu{ 3306313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3316313Sgblack@eecs.umich.edu} 3326313Sgblack@eecs.umich.edu 3336313Sgblack@eecs.umich.edutemplate <class Impl> 3346313Sgblack@eecs.umich.eduint 3356313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3366313Sgblack@eecs.umich.edu{ 3376313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3386313Sgblack@eecs.umich.edu} 3396313Sgblack@eecs.umich.edu 3406313Sgblack@eecs.umich.edutemplate <class Impl> 3415258Sksewell@umich.eduvoid 3424172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3432817Sksewell@umich.edu{ 3445715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3452817Sksewell@umich.edu 3462817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3472817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3485715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3492817Sksewell@umich.edu } 3502817Sksewell@umich.edu} 3512817Sksewell@umich.edu 3522817Sksewell@umich.edutemplate <class Impl> 3533468Sgblack@eecs.umich.eduvoid 3548518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 3552817Sksewell@umich.edu{ 3565715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3572817Sksewell@umich.edu 3582817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3592817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3605715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3612817Sksewell@umich.edu } 3622817Sksewell@umich.edu} 3632817Sksewell@umich.edu 364