thread_context_impl.hh revision 7763
12817Sksewell@umich.edu/* 27763SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37763SAli.Saidi@ARM.com * All rights reserved 47763SAli.Saidi@ARM.com * 57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137763SAli.Saidi@ARM.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu * Korey Sewell 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 446329Sgblack@eecs.umich.edu#include "arch/registers.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 472834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 482817Sksewell@umich.edu 492817Sksewell@umich.edu#if FULL_SYSTEM 502817Sksewell@umich.edutemplate <class Impl> 512817Sksewell@umich.eduVirtualPort * 525499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 532817Sksewell@umich.edu{ 545499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 552817Sksewell@umich.edu} 562817Sksewell@umich.edu 572817Sksewell@umich.edutemplate <class Impl> 582817Sksewell@umich.eduvoid 592817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 602817Sksewell@umich.edu{ 613126Sktlim@umich.edu thread->dumpFuncProfile(); 622817Sksewell@umich.edu} 632817Sksewell@umich.edu#endif 642817Sksewell@umich.edu 652817Sksewell@umich.edutemplate <class Impl> 662817Sksewell@umich.eduvoid 672817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 682817Sksewell@umich.edu{ 692817Sksewell@umich.edu // some things should already be set up 707467Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 712817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 727467Stjones1@inf.ed.ac.uk#else 732817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 742817Sksewell@umich.edu#endif 752817Sksewell@umich.edu 762817Sksewell@umich.edu // copy over functional state 772817Sksewell@umich.edu setStatus(old_context->status()); 782817Sksewell@umich.edu copyArchRegs(old_context); 795714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 805715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 812817Sksewell@umich.edu 822817Sksewell@umich.edu#if !FULL_SYSTEM 832817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 842817Sksewell@umich.edu#else 852817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 862817Sksewell@umich.edu if (other_quiesce) { 872817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 882817Sksewell@umich.edu // the proper CPU. 892817Sksewell@umich.edu other_quiesce->tc = this; 902817Sksewell@umich.edu } 912817Sksewell@umich.edu if (thread->quiesceEvent) { 922817Sksewell@umich.edu thread->quiesceEvent->tc = this; 932817Sksewell@umich.edu } 942817Sksewell@umich.edu 952817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 962817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 972817Sksewell@umich.edu// storeCondFailures = 0; 982817Sksewell@umich.edu cpu->lockFlag = false; 992817Sksewell@umich.edu#endif 1002817Sksewell@umich.edu 1016029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 1022817Sksewell@umich.edu 1032817Sksewell@umich.edu thread->inSyscall = false; 1042817Sksewell@umich.edu thread->trapPending = false; 1052817Sksewell@umich.edu} 1062817Sksewell@umich.edu 1072817Sksewell@umich.edutemplate <class Impl> 1082817Sksewell@umich.eduvoid 1092817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 1102817Sksewell@umich.edu{ 1112875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1125715Shsul@eecs.umich.edu threadId()); 1132817Sksewell@umich.edu 1142817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1152817Sksewell@umich.edu return; 1162817Sksewell@umich.edu 1172817Sksewell@umich.edu#if FULL_SYSTEM 1182817Sksewell@umich.edu thread->lastActivate = curTick; 1192817Sksewell@umich.edu#endif 1202817Sksewell@umich.edu 1212817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1222817Sksewell@umich.edu 1232817Sksewell@umich.edu // status() == Suspended 1245715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1252817Sksewell@umich.edu} 1262817Sksewell@umich.edu 1272817Sksewell@umich.edutemplate <class Impl> 1282817Sksewell@umich.eduvoid 1295250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1302817Sksewell@umich.edu{ 1312875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1325715Shsul@eecs.umich.edu threadId()); 1332817Sksewell@umich.edu 1342817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1352817Sksewell@umich.edu return; 1362817Sksewell@umich.edu 1372817Sksewell@umich.edu#if FULL_SYSTEM 1382817Sksewell@umich.edu thread->lastActivate = curTick; 1392817Sksewell@umich.edu thread->lastSuspend = curTick; 1402817Sksewell@umich.edu#endif 1412817Sksewell@umich.edu/* 1422817Sksewell@umich.edu#if FULL_SYSTEM 1432817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1445704Snate@binkert.org if (cpu->checkInterrupts()) { 1452817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1462817Sksewell@umich.edu return; 1472817Sksewell@umich.edu } 1482817Sksewell@umich.edu#endif 1492817Sksewell@umich.edu*/ 1502817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1515715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1522817Sksewell@umich.edu} 1532817Sksewell@umich.edu 1542817Sksewell@umich.edutemplate <class Impl> 1552817Sksewell@umich.eduvoid 1565250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1572817Sksewell@umich.edu{ 1582875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1595715Shsul@eecs.umich.edu threadId()); 1602817Sksewell@umich.edu 1612817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1622817Sksewell@umich.edu return; 1632817Sksewell@umich.edu 1642817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1655715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1662817Sksewell@umich.edu} 1672817Sksewell@umich.edu 1682817Sksewell@umich.edutemplate <class Impl> 1692817Sksewell@umich.eduvoid 1702817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1712817Sksewell@umich.edu{ 1722817Sksewell@umich.edu#if FULL_SYSTEM 1733548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1742817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1752817Sksewell@umich.edu#endif 1762817Sksewell@umich.edu} 1772817Sksewell@umich.edu 1782817Sksewell@umich.edutemplate <class Impl> 1792817Sksewell@umich.eduvoid 1802817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1812817Sksewell@umich.edu{ 1822817Sksewell@umich.edu#if FULL_SYSTEM 1832817Sksewell@umich.edu if (thread->kernelStats) 1842817Sksewell@umich.edu thread->kernelStats->serialize(os); 1852817Sksewell@umich.edu#endif 1862817Sksewell@umich.edu 1872817Sksewell@umich.edu} 1882817Sksewell@umich.edu 1892817Sksewell@umich.edutemplate <class Impl> 1902817Sksewell@umich.eduvoid 1912817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1922817Sksewell@umich.edu{ 1932817Sksewell@umich.edu#if FULL_SYSTEM 1942817Sksewell@umich.edu if (thread->kernelStats) 1952817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1962817Sksewell@umich.edu#endif 1972817Sksewell@umich.edu 1982817Sksewell@umich.edu} 1992817Sksewell@umich.edu 2002817Sksewell@umich.edu#if FULL_SYSTEM 2012817Sksewell@umich.edutemplate <class Impl> 2022817Sksewell@umich.eduTick 2032817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2042817Sksewell@umich.edu{ 2052817Sksewell@umich.edu return thread->lastActivate; 2062817Sksewell@umich.edu} 2072817Sksewell@umich.edu 2082817Sksewell@umich.edutemplate <class Impl> 2092817Sksewell@umich.eduTick 2102817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2112817Sksewell@umich.edu{ 2122817Sksewell@umich.edu return thread->lastSuspend; 2132817Sksewell@umich.edu} 2142817Sksewell@umich.edu 2152817Sksewell@umich.edutemplate <class Impl> 2162817Sksewell@umich.eduvoid 2172817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2183126Sktlim@umich.edu{ 2193126Sktlim@umich.edu thread->profileClear(); 2203126Sktlim@umich.edu} 2212817Sksewell@umich.edu 2222817Sksewell@umich.edutemplate <class Impl> 2232817Sksewell@umich.eduvoid 2242817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2253126Sktlim@umich.edu{ 2263126Sktlim@umich.edu thread->profileSample(); 2273126Sktlim@umich.edu} 2282817Sksewell@umich.edu#endif 2292817Sksewell@umich.edu 2302817Sksewell@umich.edutemplate <class Impl> 2312817Sksewell@umich.eduvoid 2322817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2332817Sksewell@umich.edu{ 2342817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2352817Sksewell@umich.edu // there are no instructions in the pipeline. 2366221Snate@binkert.org ThreadID tid = thread->threadId(); 2372817Sksewell@umich.edu PhysRegIndex renamed_reg; 2382817Sksewell@umich.edu 2392817Sksewell@umich.edu // First loop through the integer registers. 2402817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2412817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2422817Sksewell@umich.edu 2432817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2442817Sksewell@umich.edu "now has data %lli.\n", 2452817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2462817Sksewell@umich.edu tc->readIntReg(i)); 2472817Sksewell@umich.edu 2482817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2492817Sksewell@umich.edu } 2502817Sksewell@umich.edu 2512817Sksewell@umich.edu // Then loop through the floating point registers. 2522817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2532817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2542817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2552817Sksewell@umich.edu tc->readFloatRegBits(i)); 2562817Sksewell@umich.edu } 2572817Sksewell@umich.edu 2582817Sksewell@umich.edu // Copy the misc regs. 2592986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2602817Sksewell@umich.edu 2615258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2625258Sksewell@umich.edu // next micropc. 2637720Sgblack@eecs.umich.edu cpu->pcState(tc->pcState(), tid); 2642817Sksewell@umich.edu#if !FULL_SYSTEM 2652817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2662817Sksewell@umich.edu#endif 2672817Sksewell@umich.edu} 2682817Sksewell@umich.edu 2692817Sksewell@umich.edutemplate <class Impl> 2702817Sksewell@umich.eduvoid 2712817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2727763SAli.Saidi@ARM.com{ 2737763SAli.Saidi@ARM.com cpu->isa[thread->threadId()].clear(); 2747763SAli.Saidi@ARM.com} 2752817Sksewell@umich.edu 2762817Sksewell@umich.edutemplate <class Impl> 2772817Sksewell@umich.eduuint64_t 2782817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2792817Sksewell@umich.edu{ 2806313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2815715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2822817Sksewell@umich.edu} 2832817Sksewell@umich.edu 2842817Sksewell@umich.edutemplate <class Impl> 2852986Sgblack@eecs.umich.eduTheISA::FloatReg 2862817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2872817Sksewell@umich.edu{ 2886313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2896314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2902817Sksewell@umich.edu} 2912817Sksewell@umich.edu 2922817Sksewell@umich.edutemplate <class Impl> 2932986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2942817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2952817Sksewell@umich.edu{ 2966313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2975715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2982817Sksewell@umich.edu} 2992817Sksewell@umich.edu 3002817Sksewell@umich.edutemplate <class Impl> 3012817Sksewell@umich.eduvoid 3022817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3032817Sksewell@umich.edu{ 3046313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 3055715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 3062817Sksewell@umich.edu 3072817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3082817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3095715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3102817Sksewell@umich.edu } 3112817Sksewell@umich.edu} 3122817Sksewell@umich.edu 3132817Sksewell@umich.edutemplate <class Impl> 3142817Sksewell@umich.eduvoid 3152817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3162817Sksewell@umich.edu{ 3176313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3186314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 3192817Sksewell@umich.edu 3202817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3215715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3222817Sksewell@umich.edu } 3232817Sksewell@umich.edu} 3242817Sksewell@umich.edu 3252817Sksewell@umich.edutemplate <class Impl> 3262817Sksewell@umich.eduvoid 3272817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3282817Sksewell@umich.edu{ 3296313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3305715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3312817Sksewell@umich.edu 3322817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3332817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3345715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3352817Sksewell@umich.edu } 3362817Sksewell@umich.edu} 3372817Sksewell@umich.edu 3382817Sksewell@umich.edutemplate <class Impl> 3392817Sksewell@umich.eduvoid 3407720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3412817Sksewell@umich.edu{ 3427720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3435258Sksewell@umich.edu 3445258Sksewell@umich.edu // Squash if we're not already in a state update mode. 3455258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3465715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3475258Sksewell@umich.edu } 3485258Sksewell@umich.edu} 3495258Sksewell@umich.edu 3505258Sksewell@umich.edutemplate <class Impl> 3516313Sgblack@eecs.umich.eduint 3526313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3536313Sgblack@eecs.umich.edu{ 3546313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3556313Sgblack@eecs.umich.edu} 3566313Sgblack@eecs.umich.edu 3576313Sgblack@eecs.umich.edutemplate <class Impl> 3586313Sgblack@eecs.umich.eduint 3596313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3606313Sgblack@eecs.umich.edu{ 3616313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3626313Sgblack@eecs.umich.edu} 3636313Sgblack@eecs.umich.edu 3646313Sgblack@eecs.umich.edutemplate <class Impl> 3655258Sksewell@umich.eduvoid 3664172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3672817Sksewell@umich.edu{ 3685715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3692817Sksewell@umich.edu 3702817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3712817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3725715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3732817Sksewell@umich.edu } 3742817Sksewell@umich.edu} 3752817Sksewell@umich.edu 3762817Sksewell@umich.edutemplate <class Impl> 3773468Sgblack@eecs.umich.eduvoid 3784172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 3792817Sksewell@umich.edu const MiscReg &val) 3802817Sksewell@umich.edu{ 3815715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3822817Sksewell@umich.edu 3832817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3842817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3855715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3862817Sksewell@umich.edu } 3872817Sksewell@umich.edu} 3882817Sksewell@umich.edu 389