thread_context_impl.hh revision 6658
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 326329Sgblack@eecs.umich.edu#include "arch/registers.hh" 336658Snate@binkert.org#include "config/the_isa.hh" 342817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 352834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 362817Sksewell@umich.edu 372817Sksewell@umich.edu#if FULL_SYSTEM 382817Sksewell@umich.edutemplate <class Impl> 392817Sksewell@umich.eduVirtualPort * 405499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 412817Sksewell@umich.edu{ 425499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 432817Sksewell@umich.edu} 442817Sksewell@umich.edu 452817Sksewell@umich.edutemplate <class Impl> 462817Sksewell@umich.eduvoid 472817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 482817Sksewell@umich.edu{ 493126Sktlim@umich.edu thread->dumpFuncProfile(); 502817Sksewell@umich.edu} 512817Sksewell@umich.edu#endif 522817Sksewell@umich.edu 532817Sksewell@umich.edutemplate <class Impl> 542817Sksewell@umich.eduvoid 552817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 562817Sksewell@umich.edu{ 572817Sksewell@umich.edu // some things should already be set up 582817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 595803Snate@binkert.org#if !FULL_SYSTEM 602817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 612817Sksewell@umich.edu#endif 622817Sksewell@umich.edu 632817Sksewell@umich.edu // copy over functional state 642817Sksewell@umich.edu setStatus(old_context->status()); 652817Sksewell@umich.edu copyArchRegs(old_context); 665714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 675715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 682817Sksewell@umich.edu 692817Sksewell@umich.edu#if !FULL_SYSTEM 702817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 712817Sksewell@umich.edu#else 722817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 732817Sksewell@umich.edu if (other_quiesce) { 742817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 752817Sksewell@umich.edu // the proper CPU. 762817Sksewell@umich.edu other_quiesce->tc = this; 772817Sksewell@umich.edu } 782817Sksewell@umich.edu if (thread->quiesceEvent) { 792817Sksewell@umich.edu thread->quiesceEvent->tc = this; 802817Sksewell@umich.edu } 812817Sksewell@umich.edu 822817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 832817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 842817Sksewell@umich.edu// storeCondFailures = 0; 852817Sksewell@umich.edu cpu->lockFlag = false; 862817Sksewell@umich.edu#endif 872817Sksewell@umich.edu 886029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 892817Sksewell@umich.edu 902817Sksewell@umich.edu thread->inSyscall = false; 912817Sksewell@umich.edu thread->trapPending = false; 922817Sksewell@umich.edu} 932817Sksewell@umich.edu 942817Sksewell@umich.edutemplate <class Impl> 952817Sksewell@umich.eduvoid 962817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 972817Sksewell@umich.edu{ 982875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 995715Shsul@eecs.umich.edu threadId()); 1002817Sksewell@umich.edu 1012817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1022817Sksewell@umich.edu return; 1032817Sksewell@umich.edu 1042817Sksewell@umich.edu#if FULL_SYSTEM 1052817Sksewell@umich.edu thread->lastActivate = curTick; 1062817Sksewell@umich.edu#endif 1072817Sksewell@umich.edu 1082817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1092817Sksewell@umich.edu 1102817Sksewell@umich.edu // status() == Suspended 1115715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1122817Sksewell@umich.edu} 1132817Sksewell@umich.edu 1142817Sksewell@umich.edutemplate <class Impl> 1152817Sksewell@umich.eduvoid 1165250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1172817Sksewell@umich.edu{ 1182875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1195715Shsul@eecs.umich.edu threadId()); 1202817Sksewell@umich.edu 1212817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1222817Sksewell@umich.edu return; 1232817Sksewell@umich.edu 1242817Sksewell@umich.edu#if FULL_SYSTEM 1252817Sksewell@umich.edu thread->lastActivate = curTick; 1262817Sksewell@umich.edu thread->lastSuspend = curTick; 1272817Sksewell@umich.edu#endif 1282817Sksewell@umich.edu/* 1292817Sksewell@umich.edu#if FULL_SYSTEM 1302817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1315704Snate@binkert.org if (cpu->checkInterrupts()) { 1322817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1332817Sksewell@umich.edu return; 1342817Sksewell@umich.edu } 1352817Sksewell@umich.edu#endif 1362817Sksewell@umich.edu*/ 1372817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1385715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1392817Sksewell@umich.edu} 1402817Sksewell@umich.edu 1412817Sksewell@umich.edutemplate <class Impl> 1422817Sksewell@umich.eduvoid 1435250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1442817Sksewell@umich.edu{ 1452875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1465715Shsul@eecs.umich.edu threadId()); 1472817Sksewell@umich.edu 1482817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1492817Sksewell@umich.edu return; 1502817Sksewell@umich.edu 1512817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1525715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1532817Sksewell@umich.edu} 1542817Sksewell@umich.edu 1552817Sksewell@umich.edutemplate <class Impl> 1562817Sksewell@umich.eduvoid 1572817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1582817Sksewell@umich.edu{ 1592817Sksewell@umich.edu#if FULL_SYSTEM 1603548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1612817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1622817Sksewell@umich.edu#endif 1632817Sksewell@umich.edu} 1642817Sksewell@umich.edu 1652817Sksewell@umich.edutemplate <class Impl> 1662817Sksewell@umich.eduvoid 1672817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1682817Sksewell@umich.edu{ 1692817Sksewell@umich.edu#if FULL_SYSTEM 1702817Sksewell@umich.edu if (thread->kernelStats) 1712817Sksewell@umich.edu thread->kernelStats->serialize(os); 1722817Sksewell@umich.edu#endif 1732817Sksewell@umich.edu 1742817Sksewell@umich.edu} 1752817Sksewell@umich.edu 1762817Sksewell@umich.edutemplate <class Impl> 1772817Sksewell@umich.eduvoid 1782817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1792817Sksewell@umich.edu{ 1802817Sksewell@umich.edu#if FULL_SYSTEM 1812817Sksewell@umich.edu if (thread->kernelStats) 1822817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1832817Sksewell@umich.edu#endif 1842817Sksewell@umich.edu 1852817Sksewell@umich.edu} 1862817Sksewell@umich.edu 1872817Sksewell@umich.edu#if FULL_SYSTEM 1882817Sksewell@umich.edutemplate <class Impl> 1892817Sksewell@umich.eduTick 1902817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1912817Sksewell@umich.edu{ 1922817Sksewell@umich.edu return thread->lastActivate; 1932817Sksewell@umich.edu} 1942817Sksewell@umich.edu 1952817Sksewell@umich.edutemplate <class Impl> 1962817Sksewell@umich.eduTick 1972817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1982817Sksewell@umich.edu{ 1992817Sksewell@umich.edu return thread->lastSuspend; 2002817Sksewell@umich.edu} 2012817Sksewell@umich.edu 2022817Sksewell@umich.edutemplate <class Impl> 2032817Sksewell@umich.eduvoid 2042817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2053126Sktlim@umich.edu{ 2063126Sktlim@umich.edu thread->profileClear(); 2073126Sktlim@umich.edu} 2082817Sksewell@umich.edu 2092817Sksewell@umich.edutemplate <class Impl> 2102817Sksewell@umich.eduvoid 2112817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2123126Sktlim@umich.edu{ 2133126Sktlim@umich.edu thread->profileSample(); 2143126Sktlim@umich.edu} 2152817Sksewell@umich.edu#endif 2162817Sksewell@umich.edu 2172817Sksewell@umich.edutemplate <class Impl> 2182817Sksewell@umich.eduTheISA::MachInst 2192817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2202817Sksewell@umich.edu{ 2212817Sksewell@umich.edu return thread->getInst(); 2222817Sksewell@umich.edu} 2232817Sksewell@umich.edu 2242817Sksewell@umich.edutemplate <class Impl> 2252817Sksewell@umich.eduvoid 2262817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2272817Sksewell@umich.edu{ 2282817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2292817Sksewell@umich.edu // there are no instructions in the pipeline. 2306221Snate@binkert.org ThreadID tid = thread->threadId(); 2312817Sksewell@umich.edu PhysRegIndex renamed_reg; 2322817Sksewell@umich.edu 2332817Sksewell@umich.edu // First loop through the integer registers. 2342817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2352817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2362817Sksewell@umich.edu 2372817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2382817Sksewell@umich.edu "now has data %lli.\n", 2392817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2402817Sksewell@umich.edu tc->readIntReg(i)); 2412817Sksewell@umich.edu 2422817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2432817Sksewell@umich.edu } 2442817Sksewell@umich.edu 2452817Sksewell@umich.edu // Then loop through the floating point registers. 2462817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2472817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2482817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2492817Sksewell@umich.edu tc->readFloatRegBits(i)); 2502817Sksewell@umich.edu } 2512817Sksewell@umich.edu 2522817Sksewell@umich.edu // Copy the misc regs. 2532986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2542817Sksewell@umich.edu 2555258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2565258Sksewell@umich.edu // next micropc. 2572817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2582817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2595258Sksewell@umich.edu cpu->setNextNPC(tc->readNextNPC(), tid); 2605258Sksewell@umich.edu cpu->setMicroPC(tc->readMicroPC(), tid); 2615258Sksewell@umich.edu cpu->setNextMicroPC(tc->readNextMicroPC(), tid); 2622817Sksewell@umich.edu#if !FULL_SYSTEM 2632817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2642817Sksewell@umich.edu#endif 2652817Sksewell@umich.edu} 2662817Sksewell@umich.edu 2672817Sksewell@umich.edutemplate <class Impl> 2682817Sksewell@umich.eduvoid 2692817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2702817Sksewell@umich.edu{} 2712817Sksewell@umich.edu 2722817Sksewell@umich.edutemplate <class Impl> 2732817Sksewell@umich.eduuint64_t 2742817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2752817Sksewell@umich.edu{ 2766313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2775715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2782817Sksewell@umich.edu} 2792817Sksewell@umich.edu 2802817Sksewell@umich.edutemplate <class Impl> 2812986Sgblack@eecs.umich.eduTheISA::FloatReg 2822817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2832817Sksewell@umich.edu{ 2846313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2856314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2862817Sksewell@umich.edu} 2872817Sksewell@umich.edu 2882817Sksewell@umich.edutemplate <class Impl> 2892986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2902817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2912817Sksewell@umich.edu{ 2926313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2935715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2942817Sksewell@umich.edu} 2952817Sksewell@umich.edu 2962817Sksewell@umich.edutemplate <class Impl> 2972817Sksewell@umich.eduvoid 2982817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2992817Sksewell@umich.edu{ 3006313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 3015715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 3022817Sksewell@umich.edu 3032817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3042817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3055715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3062817Sksewell@umich.edu } 3072817Sksewell@umich.edu} 3082817Sksewell@umich.edu 3092817Sksewell@umich.edutemplate <class Impl> 3102817Sksewell@umich.eduvoid 3112817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3122817Sksewell@umich.edu{ 3136313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3146314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 3152817Sksewell@umich.edu 3162817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3175715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3182817Sksewell@umich.edu } 3192817Sksewell@umich.edu} 3202817Sksewell@umich.edu 3212817Sksewell@umich.edutemplate <class Impl> 3222817Sksewell@umich.eduvoid 3232817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3242817Sksewell@umich.edu{ 3256313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3265715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3272817Sksewell@umich.edu 3282817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3292817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3305715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3312817Sksewell@umich.edu } 3322817Sksewell@umich.edu} 3332817Sksewell@umich.edu 3342817Sksewell@umich.edutemplate <class Impl> 3352817Sksewell@umich.eduvoid 3362817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 3372817Sksewell@umich.edu{ 3385715Shsul@eecs.umich.edu cpu->setPC(val, thread->threadId()); 3392817Sksewell@umich.edu 3402817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3412817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3425715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3432817Sksewell@umich.edu } 3442817Sksewell@umich.edu} 3452817Sksewell@umich.edu 3462817Sksewell@umich.edutemplate <class Impl> 3472817Sksewell@umich.eduvoid 3482817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 3492817Sksewell@umich.edu{ 3505715Shsul@eecs.umich.edu cpu->setNextPC(val, thread->threadId()); 3512817Sksewell@umich.edu 3522817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3532817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3545715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3552817Sksewell@umich.edu } 3562817Sksewell@umich.edu} 3572817Sksewell@umich.edu 3582817Sksewell@umich.edutemplate <class Impl> 3593468Sgblack@eecs.umich.eduvoid 3605258Sksewell@umich.eduO3ThreadContext<Impl>::setMicroPC(uint64_t val) 3615258Sksewell@umich.edu{ 3625715Shsul@eecs.umich.edu cpu->setMicroPC(val, thread->threadId()); 3635258Sksewell@umich.edu 3645258Sksewell@umich.edu // Squash if we're not already in a state update mode. 3655258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3665715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3675258Sksewell@umich.edu } 3685258Sksewell@umich.edu} 3695258Sksewell@umich.edu 3705258Sksewell@umich.edutemplate <class Impl> 3715258Sksewell@umich.eduvoid 3725258Sksewell@umich.eduO3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 3735258Sksewell@umich.edu{ 3745715Shsul@eecs.umich.edu cpu->setNextMicroPC(val, thread->threadId()); 3755258Sksewell@umich.edu 3765258Sksewell@umich.edu // Squash if we're not already in a state update mode. 3775258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3785715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3795258Sksewell@umich.edu } 3805258Sksewell@umich.edu} 3815258Sksewell@umich.edu 3825258Sksewell@umich.edutemplate <class Impl> 3836313Sgblack@eecs.umich.eduint 3846313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3856313Sgblack@eecs.umich.edu{ 3866313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3876313Sgblack@eecs.umich.edu} 3886313Sgblack@eecs.umich.edu 3896313Sgblack@eecs.umich.edutemplate <class Impl> 3906313Sgblack@eecs.umich.eduint 3916313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3926313Sgblack@eecs.umich.edu{ 3936313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3946313Sgblack@eecs.umich.edu} 3956313Sgblack@eecs.umich.edu 3966313Sgblack@eecs.umich.edutemplate <class Impl> 3975258Sksewell@umich.eduvoid 3984172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3992817Sksewell@umich.edu{ 4005715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 4012817Sksewell@umich.edu 4022817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4032817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4045715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4052817Sksewell@umich.edu } 4062817Sksewell@umich.edu} 4072817Sksewell@umich.edu 4082817Sksewell@umich.edutemplate <class Impl> 4093468Sgblack@eecs.umich.eduvoid 4104172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 4112817Sksewell@umich.edu const MiscReg &val) 4122817Sksewell@umich.edu{ 4135715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 4142817Sksewell@umich.edu 4152817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4162817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4175715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4182817Sksewell@umich.edu } 4192817Sksewell@umich.edu} 4202817Sksewell@umich.edu 421