thread_context_impl.hh revision 6221
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 323776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 332817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 342834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 352817Sksewell@umich.edu 362817Sksewell@umich.edu#if FULL_SYSTEM 372817Sksewell@umich.edutemplate <class Impl> 382817Sksewell@umich.eduVirtualPort * 395499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 402817Sksewell@umich.edu{ 415499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 422817Sksewell@umich.edu} 432817Sksewell@umich.edu 442817Sksewell@umich.edutemplate <class Impl> 452817Sksewell@umich.eduvoid 462817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 472817Sksewell@umich.edu{ 483126Sktlim@umich.edu thread->dumpFuncProfile(); 492817Sksewell@umich.edu} 502817Sksewell@umich.edu#endif 512817Sksewell@umich.edu 522817Sksewell@umich.edutemplate <class Impl> 532817Sksewell@umich.eduvoid 542817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 552817Sksewell@umich.edu{ 562817Sksewell@umich.edu // some things should already be set up 572817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 585803Snate@binkert.org#if !FULL_SYSTEM 592817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 602817Sksewell@umich.edu#endif 612817Sksewell@umich.edu 622817Sksewell@umich.edu // copy over functional state 632817Sksewell@umich.edu setStatus(old_context->status()); 642817Sksewell@umich.edu copyArchRegs(old_context); 655714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 665715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 672817Sksewell@umich.edu 682817Sksewell@umich.edu#if !FULL_SYSTEM 692817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 702817Sksewell@umich.edu#else 712817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 722817Sksewell@umich.edu if (other_quiesce) { 732817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 742817Sksewell@umich.edu // the proper CPU. 752817Sksewell@umich.edu other_quiesce->tc = this; 762817Sksewell@umich.edu } 772817Sksewell@umich.edu if (thread->quiesceEvent) { 782817Sksewell@umich.edu thread->quiesceEvent->tc = this; 792817Sksewell@umich.edu } 802817Sksewell@umich.edu 812817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 822817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 832817Sksewell@umich.edu// storeCondFailures = 0; 842817Sksewell@umich.edu cpu->lockFlag = false; 852817Sksewell@umich.edu#endif 862817Sksewell@umich.edu 876029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 882817Sksewell@umich.edu 892817Sksewell@umich.edu thread->inSyscall = false; 902817Sksewell@umich.edu thread->trapPending = false; 912817Sksewell@umich.edu} 922817Sksewell@umich.edu 932817Sksewell@umich.edutemplate <class Impl> 942817Sksewell@umich.eduvoid 952817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 962817Sksewell@umich.edu{ 972875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 985715Shsul@eecs.umich.edu threadId()); 992817Sksewell@umich.edu 1002817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1012817Sksewell@umich.edu return; 1022817Sksewell@umich.edu 1032817Sksewell@umich.edu#if FULL_SYSTEM 1042817Sksewell@umich.edu thread->lastActivate = curTick; 1052817Sksewell@umich.edu#endif 1062817Sksewell@umich.edu 1072817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1082817Sksewell@umich.edu 1092817Sksewell@umich.edu // status() == Suspended 1105715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1112817Sksewell@umich.edu} 1122817Sksewell@umich.edu 1132817Sksewell@umich.edutemplate <class Impl> 1142817Sksewell@umich.eduvoid 1155250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1162817Sksewell@umich.edu{ 1172875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1185715Shsul@eecs.umich.edu threadId()); 1192817Sksewell@umich.edu 1202817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1212817Sksewell@umich.edu return; 1222817Sksewell@umich.edu 1232817Sksewell@umich.edu#if FULL_SYSTEM 1242817Sksewell@umich.edu thread->lastActivate = curTick; 1252817Sksewell@umich.edu thread->lastSuspend = curTick; 1262817Sksewell@umich.edu#endif 1272817Sksewell@umich.edu/* 1282817Sksewell@umich.edu#if FULL_SYSTEM 1292817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1305704Snate@binkert.org if (cpu->checkInterrupts()) { 1312817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1322817Sksewell@umich.edu return; 1332817Sksewell@umich.edu } 1342817Sksewell@umich.edu#endif 1352817Sksewell@umich.edu*/ 1362817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1375715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1382817Sksewell@umich.edu} 1392817Sksewell@umich.edu 1402817Sksewell@umich.edutemplate <class Impl> 1412817Sksewell@umich.eduvoid 1425250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1432817Sksewell@umich.edu{ 1442875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1455715Shsul@eecs.umich.edu threadId()); 1462817Sksewell@umich.edu 1472817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1482817Sksewell@umich.edu return; 1492817Sksewell@umich.edu 1502817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1515715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1522817Sksewell@umich.edu} 1532817Sksewell@umich.edu 1542817Sksewell@umich.edutemplate <class Impl> 1552817Sksewell@umich.eduvoid 1562817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1572817Sksewell@umich.edu{ 1582817Sksewell@umich.edu#if FULL_SYSTEM 1593548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1602817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1612817Sksewell@umich.edu#endif 1622817Sksewell@umich.edu} 1632817Sksewell@umich.edu 1642817Sksewell@umich.edutemplate <class Impl> 1652817Sksewell@umich.eduvoid 1662817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1672817Sksewell@umich.edu{ 1682817Sksewell@umich.edu#if FULL_SYSTEM 1692817Sksewell@umich.edu if (thread->kernelStats) 1702817Sksewell@umich.edu thread->kernelStats->serialize(os); 1712817Sksewell@umich.edu#endif 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu} 1742817Sksewell@umich.edu 1752817Sksewell@umich.edutemplate <class Impl> 1762817Sksewell@umich.eduvoid 1772817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1782817Sksewell@umich.edu{ 1792817Sksewell@umich.edu#if FULL_SYSTEM 1802817Sksewell@umich.edu if (thread->kernelStats) 1812817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1822817Sksewell@umich.edu#endif 1832817Sksewell@umich.edu 1842817Sksewell@umich.edu} 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu#if FULL_SYSTEM 1872817Sksewell@umich.edutemplate <class Impl> 1882817Sksewell@umich.eduTick 1892817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1902817Sksewell@umich.edu{ 1912817Sksewell@umich.edu return thread->lastActivate; 1922817Sksewell@umich.edu} 1932817Sksewell@umich.edu 1942817Sksewell@umich.edutemplate <class Impl> 1952817Sksewell@umich.eduTick 1962817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1972817Sksewell@umich.edu{ 1982817Sksewell@umich.edu return thread->lastSuspend; 1992817Sksewell@umich.edu} 2002817Sksewell@umich.edu 2012817Sksewell@umich.edutemplate <class Impl> 2022817Sksewell@umich.eduvoid 2032817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2043126Sktlim@umich.edu{ 2053126Sktlim@umich.edu thread->profileClear(); 2063126Sktlim@umich.edu} 2072817Sksewell@umich.edu 2082817Sksewell@umich.edutemplate <class Impl> 2092817Sksewell@umich.eduvoid 2102817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2113126Sktlim@umich.edu{ 2123126Sktlim@umich.edu thread->profileSample(); 2133126Sktlim@umich.edu} 2142817Sksewell@umich.edu#endif 2152817Sksewell@umich.edu 2162817Sksewell@umich.edutemplate <class Impl> 2172817Sksewell@umich.eduTheISA::MachInst 2182817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2192817Sksewell@umich.edu{ 2202817Sksewell@umich.edu return thread->getInst(); 2212817Sksewell@umich.edu} 2222817Sksewell@umich.edu 2232817Sksewell@umich.edutemplate <class Impl> 2242817Sksewell@umich.eduvoid 2252817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2262817Sksewell@umich.edu{ 2272817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2282817Sksewell@umich.edu // there are no instructions in the pipeline. 2296221Snate@binkert.org ThreadID tid = thread->threadId(); 2302817Sksewell@umich.edu PhysRegIndex renamed_reg; 2312817Sksewell@umich.edu 2322817Sksewell@umich.edu // First loop through the integer registers. 2332817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2342817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2352817Sksewell@umich.edu 2362817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2372817Sksewell@umich.edu "now has data %lli.\n", 2382817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2392817Sksewell@umich.edu tc->readIntReg(i)); 2402817Sksewell@umich.edu 2412817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2422817Sksewell@umich.edu } 2432817Sksewell@umich.edu 2442817Sksewell@umich.edu // Then loop through the floating point registers. 2452817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2462817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2472817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2482817Sksewell@umich.edu tc->readFloatRegBits(i)); 2492817Sksewell@umich.edu } 2502817Sksewell@umich.edu 2512817Sksewell@umich.edu // Copy the misc regs. 2522986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2532817Sksewell@umich.edu 2545258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2555258Sksewell@umich.edu // next micropc. 2562817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2572817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2585258Sksewell@umich.edu cpu->setNextNPC(tc->readNextNPC(), tid); 2595258Sksewell@umich.edu cpu->setMicroPC(tc->readMicroPC(), tid); 2605258Sksewell@umich.edu cpu->setNextMicroPC(tc->readNextMicroPC(), tid); 2612817Sksewell@umich.edu#if !FULL_SYSTEM 2622817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2632817Sksewell@umich.edu#endif 2642817Sksewell@umich.edu} 2652817Sksewell@umich.edu 2662817Sksewell@umich.edutemplate <class Impl> 2672817Sksewell@umich.eduvoid 2682817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2692817Sksewell@umich.edu{} 2702817Sksewell@umich.edu 2712817Sksewell@umich.edutemplate <class Impl> 2722817Sksewell@umich.eduuint64_t 2732817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2742817Sksewell@umich.edu{ 2753776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 2765715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2772817Sksewell@umich.edu} 2782817Sksewell@umich.edu 2792817Sksewell@umich.edutemplate <class Impl> 2802986Sgblack@eecs.umich.eduTheISA::FloatReg 2812817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 2822817Sksewell@umich.edu{ 2835258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 2842817Sksewell@umich.edu switch(width) { 2852817Sksewell@umich.edu case 32: 2865715Shsul@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); 2872817Sksewell@umich.edu case 64: 2885715Shsul@eecs.umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); 2892817Sksewell@umich.edu default: 2902817Sksewell@umich.edu panic("Unsupported width!"); 2912817Sksewell@umich.edu return 0; 2922817Sksewell@umich.edu } 2932817Sksewell@umich.edu} 2942817Sksewell@umich.edu 2952817Sksewell@umich.edutemplate <class Impl> 2962986Sgblack@eecs.umich.eduTheISA::FloatReg 2972817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2982817Sksewell@umich.edu{ 2995258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3005715Shsul@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); 3012817Sksewell@umich.edu} 3022817Sksewell@umich.edu 3032817Sksewell@umich.edutemplate <class Impl> 3042986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3052817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3062817Sksewell@umich.edu{ 3072817Sksewell@umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3085258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3095715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 3102817Sksewell@umich.edu} 3112817Sksewell@umich.edu 3122817Sksewell@umich.edutemplate <class Impl> 3132986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3142817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3152817Sksewell@umich.edu{ 3165258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3175715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 3182817Sksewell@umich.edu} 3192817Sksewell@umich.edu 3202817Sksewell@umich.edutemplate <class Impl> 3212817Sksewell@umich.eduvoid 3222817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3232817Sksewell@umich.edu{ 3243776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 3255715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 3262817Sksewell@umich.edu 3272817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3282817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3295715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3302817Sksewell@umich.edu } 3312817Sksewell@umich.edu} 3322817Sksewell@umich.edu 3332817Sksewell@umich.edutemplate <class Impl> 3342817Sksewell@umich.eduvoid 3352817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3362817Sksewell@umich.edu{ 3375258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3382817Sksewell@umich.edu switch(width) { 3392817Sksewell@umich.edu case 32: 3405715Shsul@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); 3412817Sksewell@umich.edu break; 3422817Sksewell@umich.edu case 64: 3435715Shsul@eecs.umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); 3442817Sksewell@umich.edu break; 3452817Sksewell@umich.edu } 3462817Sksewell@umich.edu 3472817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3482817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3495715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3502817Sksewell@umich.edu } 3512817Sksewell@umich.edu} 3522817Sksewell@umich.edu 3532817Sksewell@umich.edutemplate <class Impl> 3542817Sksewell@umich.eduvoid 3552817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3562817Sksewell@umich.edu{ 3575258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3585715Shsul@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); 3592817Sksewell@umich.edu 3602817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3615715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3622817Sksewell@umich.edu } 3632817Sksewell@umich.edu} 3642817Sksewell@umich.edu 3652817Sksewell@umich.edutemplate <class Impl> 3662817Sksewell@umich.eduvoid 3672817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3682817Sksewell@umich.edu int width) 3692817Sksewell@umich.edu{ 3702817Sksewell@umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3715258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3725715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3732817Sksewell@umich.edu 3742817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3752817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3765715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3772817Sksewell@umich.edu } 3782817Sksewell@umich.edu} 3792817Sksewell@umich.edu 3802817Sksewell@umich.edutemplate <class Impl> 3812817Sksewell@umich.eduvoid 3822817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3832817Sksewell@umich.edu{ 3845258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3855715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3862817Sksewell@umich.edu 3872817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3882817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3895715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3902817Sksewell@umich.edu } 3912817Sksewell@umich.edu} 3922817Sksewell@umich.edu 3932817Sksewell@umich.edutemplate <class Impl> 3942817Sksewell@umich.eduvoid 3952817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 3962817Sksewell@umich.edu{ 3975715Shsul@eecs.umich.edu cpu->setPC(val, thread->threadId()); 3982817Sksewell@umich.edu 3992817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4002817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4015715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4022817Sksewell@umich.edu } 4032817Sksewell@umich.edu} 4042817Sksewell@umich.edu 4052817Sksewell@umich.edutemplate <class Impl> 4062817Sksewell@umich.eduvoid 4072817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4082817Sksewell@umich.edu{ 4095715Shsul@eecs.umich.edu cpu->setNextPC(val, thread->threadId()); 4102817Sksewell@umich.edu 4112817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4122817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4135715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4142817Sksewell@umich.edu } 4152817Sksewell@umich.edu} 4162817Sksewell@umich.edu 4172817Sksewell@umich.edutemplate <class Impl> 4183468Sgblack@eecs.umich.eduvoid 4195258Sksewell@umich.eduO3ThreadContext<Impl>::setMicroPC(uint64_t val) 4205258Sksewell@umich.edu{ 4215715Shsul@eecs.umich.edu cpu->setMicroPC(val, thread->threadId()); 4225258Sksewell@umich.edu 4235258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4245258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4255715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4265258Sksewell@umich.edu } 4275258Sksewell@umich.edu} 4285258Sksewell@umich.edu 4295258Sksewell@umich.edutemplate <class Impl> 4305258Sksewell@umich.eduvoid 4315258Sksewell@umich.eduO3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 4325258Sksewell@umich.edu{ 4335715Shsul@eecs.umich.edu cpu->setNextMicroPC(val, thread->threadId()); 4345258Sksewell@umich.edu 4355258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4365258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4375715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4385258Sksewell@umich.edu } 4395258Sksewell@umich.edu} 4405258Sksewell@umich.edu 4415258Sksewell@umich.edutemplate <class Impl> 4425258Sksewell@umich.eduvoid 4434172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4442817Sksewell@umich.edu{ 4455715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 4462817Sksewell@umich.edu 4472817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4482817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4495715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4502817Sksewell@umich.edu } 4512817Sksewell@umich.edu} 4522817Sksewell@umich.edu 4532817Sksewell@umich.edutemplate <class Impl> 4543468Sgblack@eecs.umich.eduvoid 4554172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 4562817Sksewell@umich.edu const MiscReg &val) 4572817Sksewell@umich.edu{ 4585715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 4592817Sksewell@umich.edu 4602817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4612817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4625715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4632817Sksewell@umich.edu } 4642817Sksewell@umich.edu} 4652817Sksewell@umich.edu 466