thread_context_impl.hh revision 5715
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 323776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 332817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 342834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 352817Sksewell@umich.edu 362817Sksewell@umich.edu#if FULL_SYSTEM 372817Sksewell@umich.edutemplate <class Impl> 382817Sksewell@umich.eduVirtualPort * 395499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 402817Sksewell@umich.edu{ 415499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 422817Sksewell@umich.edu} 432817Sksewell@umich.edu 442817Sksewell@umich.edutemplate <class Impl> 452817Sksewell@umich.eduvoid 462817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 472817Sksewell@umich.edu{ 483126Sktlim@umich.edu thread->dumpFuncProfile(); 492817Sksewell@umich.edu} 502817Sksewell@umich.edu#endif 512817Sksewell@umich.edu 522817Sksewell@umich.edutemplate <class Impl> 532817Sksewell@umich.eduvoid 542817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 552817Sksewell@umich.edu{ 562817Sksewell@umich.edu // some things should already be set up 572817Sksewell@umich.edu#if FULL_SYSTEM 582817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 592817Sksewell@umich.edu#else 602817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 612817Sksewell@umich.edu#endif 622817Sksewell@umich.edu 632817Sksewell@umich.edu // copy over functional state 642817Sksewell@umich.edu setStatus(old_context->status()); 652817Sksewell@umich.edu copyArchRegs(old_context); 665714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 675715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 682817Sksewell@umich.edu 692817Sksewell@umich.edu#if !FULL_SYSTEM 702817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 712817Sksewell@umich.edu#else 722817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 732817Sksewell@umich.edu if (other_quiesce) { 742817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 752817Sksewell@umich.edu // the proper CPU. 762817Sksewell@umich.edu other_quiesce->tc = this; 772817Sksewell@umich.edu } 782817Sksewell@umich.edu if (thread->quiesceEvent) { 792817Sksewell@umich.edu thread->quiesceEvent->tc = this; 802817Sksewell@umich.edu } 812817Sksewell@umich.edu 822817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 832817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 842817Sksewell@umich.edu// storeCondFailures = 0; 852817Sksewell@umich.edu cpu->lockFlag = false; 862817Sksewell@umich.edu#endif 872817Sksewell@umich.edu 882817Sksewell@umich.edu old_context->setStatus(ThreadContext::Unallocated); 892817Sksewell@umich.edu 902817Sksewell@umich.edu thread->inSyscall = false; 912817Sksewell@umich.edu thread->trapPending = false; 922817Sksewell@umich.edu} 932817Sksewell@umich.edu 942817Sksewell@umich.edutemplate <class Impl> 952817Sksewell@umich.eduvoid 962817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 972817Sksewell@umich.edu{ 982875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 995715Shsul@eecs.umich.edu threadId()); 1002817Sksewell@umich.edu 1012817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1022817Sksewell@umich.edu return; 1032817Sksewell@umich.edu 1042817Sksewell@umich.edu#if FULL_SYSTEM 1052817Sksewell@umich.edu thread->lastActivate = curTick; 1062817Sksewell@umich.edu#endif 1072817Sksewell@umich.edu 1082817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) { 1095715Shsul@eecs.umich.edu cpu->activateWhenReady(thread->threadId()); 1102817Sksewell@umich.edu return; 1112817Sksewell@umich.edu } 1122817Sksewell@umich.edu 1132817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1142817Sksewell@umich.edu 1152817Sksewell@umich.edu // status() == Suspended 1165715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1172817Sksewell@umich.edu} 1182817Sksewell@umich.edu 1192817Sksewell@umich.edutemplate <class Impl> 1202817Sksewell@umich.eduvoid 1215250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1222817Sksewell@umich.edu{ 1232875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1245715Shsul@eecs.umich.edu threadId()); 1252817Sksewell@umich.edu 1262817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1272817Sksewell@umich.edu return; 1282817Sksewell@umich.edu 1292817Sksewell@umich.edu#if FULL_SYSTEM 1302817Sksewell@umich.edu thread->lastActivate = curTick; 1312817Sksewell@umich.edu thread->lastSuspend = curTick; 1322817Sksewell@umich.edu#endif 1332817Sksewell@umich.edu/* 1342817Sksewell@umich.edu#if FULL_SYSTEM 1352817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1365704Snate@binkert.org if (cpu->checkInterrupts()) { 1372817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1382817Sksewell@umich.edu return; 1392817Sksewell@umich.edu } 1402817Sksewell@umich.edu#endif 1412817Sksewell@umich.edu*/ 1422817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1435715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1442817Sksewell@umich.edu} 1452817Sksewell@umich.edu 1462817Sksewell@umich.edutemplate <class Impl> 1472817Sksewell@umich.eduvoid 1482875Sksewell@umich.eduO3ThreadContext<Impl>::deallocate(int delay) 1492817Sksewell@umich.edu{ 1503221Sktlim@umich.edu DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", 1515715Shsul@eecs.umich.edu threadId(), delay); 1522817Sksewell@umich.edu 1532817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) 1542817Sksewell@umich.edu return; 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu thread->setStatus(ThreadContext::Unallocated); 1575715Shsul@eecs.umich.edu cpu->deallocateContext(thread->threadId(), true, delay); 1582817Sksewell@umich.edu} 1592817Sksewell@umich.edu 1602817Sksewell@umich.edutemplate <class Impl> 1612817Sksewell@umich.eduvoid 1625250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1632817Sksewell@umich.edu{ 1642875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1655715Shsul@eecs.umich.edu threadId()); 1662817Sksewell@umich.edu 1672817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1682817Sksewell@umich.edu return; 1692817Sksewell@umich.edu 1702817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1715715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1722817Sksewell@umich.edu} 1732817Sksewell@umich.edu 1742817Sksewell@umich.edutemplate <class Impl> 1752817Sksewell@umich.eduvoid 1762817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1772817Sksewell@umich.edu{ 1782817Sksewell@umich.edu#if FULL_SYSTEM 1793548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1802817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1812817Sksewell@umich.edu#endif 1822817Sksewell@umich.edu} 1832817Sksewell@umich.edu 1842817Sksewell@umich.edutemplate <class Impl> 1852817Sksewell@umich.eduvoid 1862817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1872817Sksewell@umich.edu{ 1882817Sksewell@umich.edu#if FULL_SYSTEM 1892817Sksewell@umich.edu if (thread->kernelStats) 1902817Sksewell@umich.edu thread->kernelStats->serialize(os); 1912817Sksewell@umich.edu#endif 1922817Sksewell@umich.edu 1932817Sksewell@umich.edu} 1942817Sksewell@umich.edu 1952817Sksewell@umich.edutemplate <class Impl> 1962817Sksewell@umich.eduvoid 1972817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1982817Sksewell@umich.edu{ 1992817Sksewell@umich.edu#if FULL_SYSTEM 2002817Sksewell@umich.edu if (thread->kernelStats) 2012817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 2022817Sksewell@umich.edu#endif 2032817Sksewell@umich.edu 2042817Sksewell@umich.edu} 2052817Sksewell@umich.edu 2062817Sksewell@umich.edu#if FULL_SYSTEM 2072817Sksewell@umich.edutemplate <class Impl> 2082817Sksewell@umich.eduTick 2092817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2102817Sksewell@umich.edu{ 2112817Sksewell@umich.edu return thread->lastActivate; 2122817Sksewell@umich.edu} 2132817Sksewell@umich.edu 2142817Sksewell@umich.edutemplate <class Impl> 2152817Sksewell@umich.eduTick 2162817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2172817Sksewell@umich.edu{ 2182817Sksewell@umich.edu return thread->lastSuspend; 2192817Sksewell@umich.edu} 2202817Sksewell@umich.edu 2212817Sksewell@umich.edutemplate <class Impl> 2222817Sksewell@umich.eduvoid 2232817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2243126Sktlim@umich.edu{ 2253126Sktlim@umich.edu thread->profileClear(); 2263126Sktlim@umich.edu} 2272817Sksewell@umich.edu 2282817Sksewell@umich.edutemplate <class Impl> 2292817Sksewell@umich.eduvoid 2302817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2313126Sktlim@umich.edu{ 2323126Sktlim@umich.edu thread->profileSample(); 2333126Sktlim@umich.edu} 2342817Sksewell@umich.edu#endif 2352817Sksewell@umich.edu 2362817Sksewell@umich.edutemplate <class Impl> 2372817Sksewell@umich.eduTheISA::MachInst 2382817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2392817Sksewell@umich.edu{ 2402817Sksewell@umich.edu return thread->getInst(); 2412817Sksewell@umich.edu} 2422817Sksewell@umich.edu 2432817Sksewell@umich.edutemplate <class Impl> 2442817Sksewell@umich.eduvoid 2452817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2462817Sksewell@umich.edu{ 2472817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2482817Sksewell@umich.edu // there are no instructions in the pipeline. 2495715Shsul@eecs.umich.edu unsigned tid = thread->threadId(); 2502817Sksewell@umich.edu PhysRegIndex renamed_reg; 2512817Sksewell@umich.edu 2522817Sksewell@umich.edu // First loop through the integer registers. 2532817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2542817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2552817Sksewell@umich.edu 2562817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2572817Sksewell@umich.edu "now has data %lli.\n", 2582817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2592817Sksewell@umich.edu tc->readIntReg(i)); 2602817Sksewell@umich.edu 2612817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2622817Sksewell@umich.edu } 2632817Sksewell@umich.edu 2642817Sksewell@umich.edu // Then loop through the floating point registers. 2652817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2662817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2672817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2682817Sksewell@umich.edu tc->readFloatRegBits(i)); 2692817Sksewell@umich.edu } 2702817Sksewell@umich.edu 2712817Sksewell@umich.edu // Copy the misc regs. 2722986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2732817Sksewell@umich.edu 2745258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2755258Sksewell@umich.edu // next micropc. 2762817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2772817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2785258Sksewell@umich.edu cpu->setNextNPC(tc->readNextNPC(), tid); 2795258Sksewell@umich.edu cpu->setMicroPC(tc->readMicroPC(), tid); 2805258Sksewell@umich.edu cpu->setNextMicroPC(tc->readNextMicroPC(), tid); 2812817Sksewell@umich.edu#if !FULL_SYSTEM 2822817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2832817Sksewell@umich.edu#endif 2842817Sksewell@umich.edu} 2852817Sksewell@umich.edu 2862817Sksewell@umich.edutemplate <class Impl> 2872817Sksewell@umich.eduvoid 2882817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2892817Sksewell@umich.edu{} 2902817Sksewell@umich.edu 2912817Sksewell@umich.edutemplate <class Impl> 2922817Sksewell@umich.eduuint64_t 2932817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2942817Sksewell@umich.edu{ 2953776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 2965715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2972817Sksewell@umich.edu} 2982817Sksewell@umich.edu 2992817Sksewell@umich.edutemplate <class Impl> 3002986Sgblack@eecs.umich.eduTheISA::FloatReg 3012817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 3022817Sksewell@umich.edu{ 3035258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3042817Sksewell@umich.edu switch(width) { 3052817Sksewell@umich.edu case 32: 3065715Shsul@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); 3072817Sksewell@umich.edu case 64: 3085715Shsul@eecs.umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); 3092817Sksewell@umich.edu default: 3102817Sksewell@umich.edu panic("Unsupported width!"); 3112817Sksewell@umich.edu return 0; 3122817Sksewell@umich.edu } 3132817Sksewell@umich.edu} 3142817Sksewell@umich.edu 3152817Sksewell@umich.edutemplate <class Impl> 3162986Sgblack@eecs.umich.eduTheISA::FloatReg 3172817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 3182817Sksewell@umich.edu{ 3195258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3205715Shsul@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); 3212817Sksewell@umich.edu} 3222817Sksewell@umich.edu 3232817Sksewell@umich.edutemplate <class Impl> 3242986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3252817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3262817Sksewell@umich.edu{ 3272817Sksewell@umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3285258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3295715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 3302817Sksewell@umich.edu} 3312817Sksewell@umich.edu 3322817Sksewell@umich.edutemplate <class Impl> 3332986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3342817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3352817Sksewell@umich.edu{ 3365258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3375715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 3382817Sksewell@umich.edu} 3392817Sksewell@umich.edu 3402817Sksewell@umich.edutemplate <class Impl> 3412817Sksewell@umich.eduvoid 3422817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3432817Sksewell@umich.edu{ 3443776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 3455715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 3462817Sksewell@umich.edu 3472817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3482817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3495715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3502817Sksewell@umich.edu } 3512817Sksewell@umich.edu} 3522817Sksewell@umich.edu 3532817Sksewell@umich.edutemplate <class Impl> 3542817Sksewell@umich.eduvoid 3552817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3562817Sksewell@umich.edu{ 3575258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3582817Sksewell@umich.edu switch(width) { 3592817Sksewell@umich.edu case 32: 3605715Shsul@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); 3612817Sksewell@umich.edu break; 3622817Sksewell@umich.edu case 64: 3635715Shsul@eecs.umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); 3642817Sksewell@umich.edu break; 3652817Sksewell@umich.edu } 3662817Sksewell@umich.edu 3672817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3682817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3695715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3702817Sksewell@umich.edu } 3712817Sksewell@umich.edu} 3722817Sksewell@umich.edu 3732817Sksewell@umich.edutemplate <class Impl> 3742817Sksewell@umich.eduvoid 3752817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3762817Sksewell@umich.edu{ 3775258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3785715Shsul@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); 3792817Sksewell@umich.edu 3802817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3815715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3822817Sksewell@umich.edu } 3832817Sksewell@umich.edu} 3842817Sksewell@umich.edu 3852817Sksewell@umich.edutemplate <class Impl> 3862817Sksewell@umich.eduvoid 3872817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3882817Sksewell@umich.edu int width) 3892817Sksewell@umich.edu{ 3902817Sksewell@umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3915258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3925715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3932817Sksewell@umich.edu 3942817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3952817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3965715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3972817Sksewell@umich.edu } 3982817Sksewell@umich.edu} 3992817Sksewell@umich.edu 4002817Sksewell@umich.edutemplate <class Impl> 4012817Sksewell@umich.eduvoid 4022817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4032817Sksewell@umich.edu{ 4045258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 4055715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 4062817Sksewell@umich.edu 4072817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4082817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4095715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4102817Sksewell@umich.edu } 4112817Sksewell@umich.edu} 4122817Sksewell@umich.edu 4132817Sksewell@umich.edutemplate <class Impl> 4142817Sksewell@umich.eduvoid 4152817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 4162817Sksewell@umich.edu{ 4175715Shsul@eecs.umich.edu cpu->setPC(val, thread->threadId()); 4182817Sksewell@umich.edu 4192817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4202817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4215715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4222817Sksewell@umich.edu } 4232817Sksewell@umich.edu} 4242817Sksewell@umich.edu 4252817Sksewell@umich.edutemplate <class Impl> 4262817Sksewell@umich.eduvoid 4272817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4282817Sksewell@umich.edu{ 4295715Shsul@eecs.umich.edu cpu->setNextPC(val, thread->threadId()); 4302817Sksewell@umich.edu 4312817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4322817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4335715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4342817Sksewell@umich.edu } 4352817Sksewell@umich.edu} 4362817Sksewell@umich.edu 4372817Sksewell@umich.edutemplate <class Impl> 4383468Sgblack@eecs.umich.eduvoid 4395258Sksewell@umich.eduO3ThreadContext<Impl>::setMicroPC(uint64_t val) 4405258Sksewell@umich.edu{ 4415715Shsul@eecs.umich.edu cpu->setMicroPC(val, thread->threadId()); 4425258Sksewell@umich.edu 4435258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4445258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4455715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4465258Sksewell@umich.edu } 4475258Sksewell@umich.edu} 4485258Sksewell@umich.edu 4495258Sksewell@umich.edutemplate <class Impl> 4505258Sksewell@umich.eduvoid 4515258Sksewell@umich.eduO3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 4525258Sksewell@umich.edu{ 4535715Shsul@eecs.umich.edu cpu->setNextMicroPC(val, thread->threadId()); 4545258Sksewell@umich.edu 4555258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4565258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4575715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4585258Sksewell@umich.edu } 4595258Sksewell@umich.edu} 4605258Sksewell@umich.edu 4615258Sksewell@umich.edutemplate <class Impl> 4625258Sksewell@umich.eduvoid 4634172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4642817Sksewell@umich.edu{ 4655715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 4662817Sksewell@umich.edu 4672817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4682817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4695715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4702817Sksewell@umich.edu } 4712817Sksewell@umich.edu} 4722817Sksewell@umich.edu 4732817Sksewell@umich.edutemplate <class Impl> 4743468Sgblack@eecs.umich.eduvoid 4754172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 4762817Sksewell@umich.edu const MiscReg &val) 4772817Sksewell@umich.edu{ 4785715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 4792817Sksewell@umich.edu 4802817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4812817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4825715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 4832817Sksewell@umich.edu } 4842817Sksewell@umich.edu} 4852817Sksewell@umich.edu 4862817Sksewell@umich.edu#if !FULL_SYSTEM 4872817Sksewell@umich.edu 4882817Sksewell@umich.edutemplate <class Impl> 4892817Sksewell@umich.eduTheISA::IntReg 4902817Sksewell@umich.eduO3ThreadContext<Impl>::getSyscallArg(int i) 4912817Sksewell@umich.edu{ 4925715Shsul@eecs.umich.edu return cpu->getSyscallArg(i, thread->threadId()); 4932817Sksewell@umich.edu} 4942817Sksewell@umich.edu 4952817Sksewell@umich.edutemplate <class Impl> 4962817Sksewell@umich.eduvoid 4972817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 4982817Sksewell@umich.edu{ 4995715Shsul@eecs.umich.edu cpu->setSyscallArg(i, val, thread->threadId()); 5002817Sksewell@umich.edu} 5012817Sksewell@umich.edu 5022817Sksewell@umich.edutemplate <class Impl> 5032817Sksewell@umich.eduvoid 5042817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 5052817Sksewell@umich.edu{ 5065715Shsul@eecs.umich.edu cpu->setSyscallReturn(return_value, thread->threadId()); 5072817Sksewell@umich.edu} 5082817Sksewell@umich.edu 5092817Sksewell@umich.edu#endif // FULL_SYSTEM 5102817Sksewell@umich.edu 511