thread_context_impl.hh revision 4217
17139Sgblack@eecs.umich.edu/* 27139Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 37139Sgblack@eecs.umich.edu * All rights reserved. 47139Sgblack@eecs.umich.edu * 57139Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67139Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77139Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97139Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117139Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127139Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137139Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147139Sgblack@eecs.umich.edu * this software without specific prior written permission. 157139Sgblack@eecs.umich.edu * 167139Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177139Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187139Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197139Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207139Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217139Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227139Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237139Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247139Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257139Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267139Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277139Sgblack@eecs.umich.edu * 287139Sgblack@eecs.umich.edu * Authors: Kevin Lim 297139Sgblack@eecs.umich.edu * Korey Sewell 307139Sgblack@eecs.umich.edu */ 317139Sgblack@eecs.umich.edu 327139Sgblack@eecs.umich.edu#include "arch/regfile.hh" 337139Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 347139Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 357139Sgblack@eecs.umich.edu 367139Sgblack@eecs.umich.edu#if FULL_SYSTEM 377139Sgblack@eecs.umich.edutemplate <class Impl> 387139Sgblack@eecs.umich.eduVirtualPort * 397139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc) 407139Sgblack@eecs.umich.edu{ 417139Sgblack@eecs.umich.edu if (!src_tc) 427139Sgblack@eecs.umich.edu return thread->getVirtPort(); 437146Sgblack@eecs.umich.edu 447141Sgblack@eecs.umich.edu VirtualPort *vp; 457139Sgblack@eecs.umich.edu 467146Sgblack@eecs.umich.edu vp = new VirtualPort("tc-vport", src_tc); 477141Sgblack@eecs.umich.edu thread->connectToMemFunc(vp); 487139Sgblack@eecs.umich.edu return vp; 497139Sgblack@eecs.umich.edu} 507139Sgblack@eecs.umich.edu 517146Sgblack@eecs.umich.edutemplate <class Impl> 527141Sgblack@eecs.umich.eduvoid 537139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 547146Sgblack@eecs.umich.edu{ 557141Sgblack@eecs.umich.edu thread->dumpFuncProfile(); 567139Sgblack@eecs.umich.edu} 577139Sgblack@eecs.umich.edu#endif 587139Sgblack@eecs.umich.edu 597139Sgblack@eecs.umich.edutemplate <class Impl> 607139Sgblack@eecs.umich.eduvoid 617141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 627139Sgblack@eecs.umich.edu{ 637139Sgblack@eecs.umich.edu // some things should already be set up 647141Sgblack@eecs.umich.edu#if FULL_SYSTEM 657141Sgblack@eecs.umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 667141Sgblack@eecs.umich.edu#else 677139Sgblack@eecs.umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 687139Sgblack@eecs.umich.edu#endif 697139Sgblack@eecs.umich.edu 707139Sgblack@eecs.umich.edu // copy over functional state 717139Sgblack@eecs.umich.edu setStatus(old_context->status()); 727139Sgblack@eecs.umich.edu copyArchRegs(old_context); 737139Sgblack@eecs.umich.edu setCpuId(old_context->readCpuId()); 747139Sgblack@eecs.umich.edu 757139Sgblack@eecs.umich.edu#if !FULL_SYSTEM 767139Sgblack@eecs.umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 777139Sgblack@eecs.umich.edu#else 787139Sgblack@eecs.umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 797139Sgblack@eecs.umich.edu if (other_quiesce) { 807139Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 817139Sgblack@eecs.umich.edu // the proper CPU. 827139Sgblack@eecs.umich.edu other_quiesce->tc = this; 837139Sgblack@eecs.umich.edu } 847139Sgblack@eecs.umich.edu if (thread->quiesceEvent) { 857139Sgblack@eecs.umich.edu thread->quiesceEvent->tc = this; 867139Sgblack@eecs.umich.edu } 877139Sgblack@eecs.umich.edu 887141Sgblack@eecs.umich.edu // Transfer kernel stats from one CPU to the other. 897141Sgblack@eecs.umich.edu thread->kernelStats = old_context->getKernelStats(); 907141Sgblack@eecs.umich.edu// storeCondFailures = 0; 917141Sgblack@eecs.umich.edu cpu->lockFlag = false; 927139Sgblack@eecs.umich.edu#endif 937141Sgblack@eecs.umich.edu 947139Sgblack@eecs.umich.edu old_context->setStatus(ThreadContext::Unallocated); 957141Sgblack@eecs.umich.edu 967139Sgblack@eecs.umich.edu thread->inSyscall = false; 977139Sgblack@eecs.umich.edu thread->trapPending = false; 987139Sgblack@eecs.umich.edu} 997139Sgblack@eecs.umich.edu 1007139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1017139Sgblack@eecs.umich.edutemplate <class Impl> 1027139Sgblack@eecs.umich.eduvoid 1037139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) 1047139Sgblack@eecs.umich.edu{ 1057139Sgblack@eecs.umich.edu if (vp != thread->getVirtPort()) { 1067139Sgblack@eecs.umich.edu vp->removeConn(); 1077146Sgblack@eecs.umich.edu delete vp; 1087141Sgblack@eecs.umich.edu } 1097139Sgblack@eecs.umich.edu} 1107146Sgblack@eecs.umich.edu#endif 1117141Sgblack@eecs.umich.edu 1127139Sgblack@eecs.umich.edutemplate <class Impl> 1137139Sgblack@eecs.umich.eduvoid 1147139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::activate(int delay) 1157139Sgblack@eecs.umich.edu{ 1167141Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1177139Sgblack@eecs.umich.edu getThreadNum()); 1187185Sgblack@eecs.umich.edu 1197185Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Active) 1207185Sgblack@eecs.umich.edu return; 1217185Sgblack@eecs.umich.edu 1227185Sgblack@eecs.umich.edu#if FULL_SYSTEM 1237185Sgblack@eecs.umich.edu thread->lastActivate = curTick; 1247185Sgblack@eecs.umich.edu#endif 1257185Sgblack@eecs.umich.edu 1267185Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Unallocated) { 1277185Sgblack@eecs.umich.edu cpu->activateWhenReady(thread->readTid()); 1287185Sgblack@eecs.umich.edu return; 1297185Sgblack@eecs.umich.edu } 1307185Sgblack@eecs.umich.edu 1317185Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Active); 1327185Sgblack@eecs.umich.edu 1337185Sgblack@eecs.umich.edu // status() == Suspended 1347185Sgblack@eecs.umich.edu cpu->activateContext(thread->readTid(), delay); 1357185Sgblack@eecs.umich.edu} 1367185Sgblack@eecs.umich.edu 1377185Sgblack@eecs.umich.edutemplate <class Impl> 1387185Sgblack@eecs.umich.eduvoid 1397185Sgblack@eecs.umich.eduO3ThreadContext<Impl>::suspend() 1407185Sgblack@eecs.umich.edu{ 1417185Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1427139Sgblack@eecs.umich.edu getThreadNum()); 1437139Sgblack@eecs.umich.edu 1447139Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Suspended) 1457139Sgblack@eecs.umich.edu return; 1467139Sgblack@eecs.umich.edu 1477139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1487139Sgblack@eecs.umich.edu thread->lastActivate = curTick; 1497139Sgblack@eecs.umich.edu thread->lastSuspend = curTick; 1507139Sgblack@eecs.umich.edu#endif 1517139Sgblack@eecs.umich.edu/* 1527139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1537139Sgblack@eecs.umich.edu // Don't change the status from active if there are pending interrupts 1547139Sgblack@eecs.umich.edu if (cpu->check_interrupts()) { 1557139Sgblack@eecs.umich.edu assert(status() == ThreadContext::Active); 1567185Sgblack@eecs.umich.edu return; 1577139Sgblack@eecs.umich.edu } 1587185Sgblack@eecs.umich.edu#endif 1597139Sgblack@eecs.umich.edu*/ 1607139Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Suspended); 1617139Sgblack@eecs.umich.edu cpu->suspendContext(thread->readTid()); 1627141Sgblack@eecs.umich.edu} 1637141Sgblack@eecs.umich.edu 1647141Sgblack@eecs.umich.edutemplate <class Impl> 1657141Sgblack@eecs.umich.eduvoid 1667139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::deallocate(int delay) 1677141Sgblack@eecs.umich.edu{ 1687139Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", 1697141Sgblack@eecs.umich.edu getThreadNum(), delay); 1707139Sgblack@eecs.umich.edu 1717139Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Unallocated) 1727139Sgblack@eecs.umich.edu return; 1737139Sgblack@eecs.umich.edu 1747139Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Unallocated); 1757139Sgblack@eecs.umich.edu cpu->deallocateContext(thread->readTid(), true, delay); 1767139Sgblack@eecs.umich.edu} 1777141Sgblack@eecs.umich.edu 1787141Sgblack@eecs.umich.edutemplate <class Impl> 1797141Sgblack@eecs.umich.eduvoid 1807141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::halt() 1817141Sgblack@eecs.umich.edu{ 1827141Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1837141Sgblack@eecs.umich.edu getThreadNum()); 1847141Sgblack@eecs.umich.edu 1857141Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Halted) 1867141Sgblack@eecs.umich.edu return; 1877141Sgblack@eecs.umich.edu 1887141Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Halted); 1897141Sgblack@eecs.umich.edu cpu->haltContext(thread->readTid()); 1907183Sgblack@eecs.umich.edu} 1917141Sgblack@eecs.umich.edu 1927183Sgblack@eecs.umich.edutemplate <class Impl> 1937141Sgblack@eecs.umich.eduvoid 1947183Sgblack@eecs.umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1957141Sgblack@eecs.umich.edu{ 1967141Sgblack@eecs.umich.edu#if FULL_SYSTEM 1977141Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1987183Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1997141Sgblack@eecs.umich.edu#endif 2007183Sgblack@eecs.umich.edu} 2017141Sgblack@eecs.umich.edu 2027183Sgblack@eecs.umich.edutemplate <class Impl> 2037141Sgblack@eecs.umich.eduvoid 2047183Sgblack@eecs.umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 2057141Sgblack@eecs.umich.edu{ 2067141Sgblack@eecs.umich.edu#if FULL_SYSTEM 2077183Sgblack@eecs.umich.edu if (thread->kernelStats) 2087141Sgblack@eecs.umich.edu thread->kernelStats->serialize(os); 2097146Sgblack@eecs.umich.edu#endif 2107141Sgblack@eecs.umich.edu 2117183Sgblack@eecs.umich.edu} 2127141Sgblack@eecs.umich.edu 2137183Sgblack@eecs.umich.edutemplate <class Impl> 2147141Sgblack@eecs.umich.eduvoid 2157141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 2167141Sgblack@eecs.umich.edu{ 2177141Sgblack@eecs.umich.edu#if FULL_SYSTEM 2187141Sgblack@eecs.umich.edu if (thread->kernelStats) 2197141Sgblack@eecs.umich.edu thread->kernelStats->unserialize(cp, section); 2207141Sgblack@eecs.umich.edu#endif 2217141Sgblack@eecs.umich.edu 2227141Sgblack@eecs.umich.edu} 2237141Sgblack@eecs.umich.edu 2247141Sgblack@eecs.umich.edu#if FULL_SYSTEM 2257141Sgblack@eecs.umich.edutemplate <class Impl> 2267183Sgblack@eecs.umich.eduTick 2277141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastActivate() 2287183Sgblack@eecs.umich.edu{ 2297141Sgblack@eecs.umich.edu return thread->lastActivate; 2307183Sgblack@eecs.umich.edu} 2317141Sgblack@eecs.umich.edu 2327183Sgblack@eecs.umich.edutemplate <class Impl> 2337141Sgblack@eecs.umich.eduTick 2347183Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastSuspend() 2357141Sgblack@eecs.umich.edu{ 2367183Sgblack@eecs.umich.edu return thread->lastSuspend; 2377141Sgblack@eecs.umich.edu} 2387183Sgblack@eecs.umich.edu 2397141Sgblack@eecs.umich.edutemplate <class Impl> 2407183Sgblack@eecs.umich.eduvoid 2417141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileClear() 2427183Sgblack@eecs.umich.edu{ 2437141Sgblack@eecs.umich.edu thread->profileClear(); 2447183Sgblack@eecs.umich.edu} 2457141Sgblack@eecs.umich.edu 2467183Sgblack@eecs.umich.edutemplate <class Impl> 2477141Sgblack@eecs.umich.eduvoid 2487183Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileSample() 2497141Sgblack@eecs.umich.edu{ 2507183Sgblack@eecs.umich.edu thread->profileSample(); 2517141Sgblack@eecs.umich.edu} 2527183Sgblack@eecs.umich.edu#endif 2537141Sgblack@eecs.umich.edu 2547183Sgblack@eecs.umich.edutemplate <class Impl> 2557141Sgblack@eecs.umich.eduTheISA::MachInst 2567183Sgblack@eecs.umich.eduO3ThreadContext<Impl>:: getInst() 2577141Sgblack@eecs.umich.edu{ 2587141Sgblack@eecs.umich.edu return thread->getInst(); 2597141Sgblack@eecs.umich.edu} 2607141Sgblack@eecs.umich.edu 2617141Sgblack@eecs.umich.edutemplate <class Impl> 2627141Sgblack@eecs.umich.eduvoid 2637141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2647141Sgblack@eecs.umich.edu{ 2657141Sgblack@eecs.umich.edu // This function will mess things up unless the ROB is empty and 2667141Sgblack@eecs.umich.edu // there are no instructions in the pipeline. 2677141Sgblack@eecs.umich.edu unsigned tid = thread->readTid(); 2687141Sgblack@eecs.umich.edu PhysRegIndex renamed_reg; 2697141Sgblack@eecs.umich.edu 2707141Sgblack@eecs.umich.edu // First loop through the integer registers. 2717146Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2727141Sgblack@eecs.umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2737183Sgblack@eecs.umich.edu 2747141Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2757146Sgblack@eecs.umich.edu "now has data %lli.\n", 2767141Sgblack@eecs.umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2777154Sgblack@eecs.umich.edu tc->readIntReg(i)); 2787154Sgblack@eecs.umich.edu 2797154Sgblack@eecs.umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2807154Sgblack@eecs.umich.edu } 2817154Sgblack@eecs.umich.edu 2827154Sgblack@eecs.umich.edu // Then loop through the floating point registers. 2837154Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2847154Sgblack@eecs.umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2857154Sgblack@eecs.umich.edu cpu->setFloatRegBits(renamed_reg, 2867141Sgblack@eecs.umich.edu tc->readFloatRegBits(i)); 2877141Sgblack@eecs.umich.edu } 2887141Sgblack@eecs.umich.edu 2897141Sgblack@eecs.umich.edu // Copy the misc regs. 2907141Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2917141Sgblack@eecs.umich.edu 2927141Sgblack@eecs.umich.edu // Then finally set the PC and the next PC. 2937141Sgblack@eecs.umich.edu cpu->setPC(tc->readPC(), tid); 2947141Sgblack@eecs.umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2957141Sgblack@eecs.umich.edu#if !FULL_SYSTEM 2967185Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2977141Sgblack@eecs.umich.edu#endif 2987141Sgblack@eecs.umich.edu} 2997141Sgblack@eecs.umich.edu 3007141Sgblack@eecs.umich.edutemplate <class Impl> 3017141Sgblack@eecs.umich.eduvoid 3027141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::clearArchRegs() 3037141Sgblack@eecs.umich.edu{} 3047141Sgblack@eecs.umich.edu 3057141Sgblack@eecs.umich.edutemplate <class Impl> 3067146Sgblack@eecs.umich.eduuint64_t 3077141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 3087141Sgblack@eecs.umich.edu{ 3097141Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 3107141Sgblack@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->readTid()); 3117141Sgblack@eecs.umich.edu} 3127141Sgblack@eecs.umich.edu 3137141Sgblack@eecs.umich.edutemplate <class Impl> 3147141Sgblack@eecs.umich.eduTheISA::FloatReg 3157141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 3167141Sgblack@eecs.umich.edu{ 3177146Sgblack@eecs.umich.edu switch(width) { 3187141Sgblack@eecs.umich.edu case 32: 3197141Sgblack@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3207146Sgblack@eecs.umich.edu case 64: 3217141Sgblack@eecs.umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); 3227141Sgblack@eecs.umich.edu default: 3237141Sgblack@eecs.umich.edu panic("Unsupported width!"); 3247154Sgblack@eecs.umich.edu return 0; 3257154Sgblack@eecs.umich.edu } 3267154Sgblack@eecs.umich.edu} 3277154Sgblack@eecs.umich.edu 3287141Sgblack@eecs.umich.edutemplate <class Impl> 3297141Sgblack@eecs.umich.eduTheISA::FloatReg 3307141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 3317141Sgblack@eecs.umich.edu{ 3327141Sgblack@eecs.umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3337141Sgblack@eecs.umich.edu} 3347141Sgblack@eecs.umich.edu 3357141Sgblack@eecs.umich.edutemplate <class Impl> 3367141Sgblack@eecs.umich.eduTheISA::FloatRegBits 3377141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3387141Sgblack@eecs.umich.edu{ 3397141Sgblack@eecs.umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3407154Sgblack@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3417154Sgblack@eecs.umich.edu} 3427154Sgblack@eecs.umich.edu 3437154Sgblack@eecs.umich.edutemplate <class Impl> 3447141Sgblack@eecs.umich.eduTheISA::FloatRegBits 3457141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3467141Sgblack@eecs.umich.edu{ 3477141Sgblack@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3487141Sgblack@eecs.umich.edu} 3497141Sgblack@eecs.umich.edu 3507141Sgblack@eecs.umich.edutemplate <class Impl> 3517141Sgblack@eecs.umich.eduvoid 3527141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3537141Sgblack@eecs.umich.edu{ 3547141Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 3557141Sgblack@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->readTid()); 3567141Sgblack@eecs.umich.edu 3577154Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3587154Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3597154Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 3607154Sgblack@eecs.umich.edu } 3617141Sgblack@eecs.umich.edu} 3627141Sgblack@eecs.umich.edu 3637141Sgblack@eecs.umich.edutemplate <class Impl> 3647141Sgblack@eecs.umich.eduvoid 3657141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3667141Sgblack@eecs.umich.edu{ 3677141Sgblack@eecs.umich.edu switch(width) { 3687141Sgblack@eecs.umich.edu case 32: 3697141Sgblack@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3707141Sgblack@eecs.umich.edu break; 3717141Sgblack@eecs.umich.edu case 64: 3727141Sgblack@eecs.umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); 3737141Sgblack@eecs.umich.edu break; 3747154Sgblack@eecs.umich.edu } 3757154Sgblack@eecs.umich.edu 3767154Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3777154Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3787141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 3797141Sgblack@eecs.umich.edu } 3807141Sgblack@eecs.umich.edu} 3817141Sgblack@eecs.umich.edu 3827141Sgblack@eecs.umich.edutemplate <class Impl> 3837141Sgblack@eecs.umich.eduvoid 3847141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3857141Sgblack@eecs.umich.edu{ 3867141Sgblack@eecs.umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3877141Sgblack@eecs.umich.edu 3887141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3897141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 3907141Sgblack@eecs.umich.edu } 3917141Sgblack@eecs.umich.edu} 3927141Sgblack@eecs.umich.edu 3937141Sgblack@eecs.umich.edutemplate <class Impl> 3947141Sgblack@eecs.umich.eduvoid 3957141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3967141Sgblack@eecs.umich.edu int width) 3977141Sgblack@eecs.umich.edu{ 3987141Sgblack@eecs.umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3997141Sgblack@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 4007141Sgblack@eecs.umich.edu 4017141Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4027141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4037141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4047141Sgblack@eecs.umich.edu } 4057141Sgblack@eecs.umich.edu} 4067141Sgblack@eecs.umich.edu 4077141Sgblack@eecs.umich.edutemplate <class Impl> 4087141Sgblack@eecs.umich.eduvoid 4097141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4107141Sgblack@eecs.umich.edu{ 4117141Sgblack@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 4127141Sgblack@eecs.umich.edu 4137146Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4147183Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4157141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4167146Sgblack@eecs.umich.edu } 4177183Sgblack@eecs.umich.edu} 4187141Sgblack@eecs.umich.edu 4197141Sgblack@eecs.umich.edutemplate <class Impl> 4207141Sgblack@eecs.umich.eduvoid 4217141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 4227141Sgblack@eecs.umich.edu{ 4237141Sgblack@eecs.umich.edu cpu->setPC(val, thread->readTid()); 4247141Sgblack@eecs.umich.edu 4257141Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4267141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4277141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4287141Sgblack@eecs.umich.edu } 4297183Sgblack@eecs.umich.edu} 4307141Sgblack@eecs.umich.edu 4317141Sgblack@eecs.umich.edutemplate <class Impl> 4327141Sgblack@eecs.umich.eduvoid 4337141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4347141Sgblack@eecs.umich.edu{ 4357141Sgblack@eecs.umich.edu cpu->setNextPC(val, thread->readTid()); 4367141Sgblack@eecs.umich.edu 4377141Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4387141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4397141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4407141Sgblack@eecs.umich.edu } 4417141Sgblack@eecs.umich.edu} 4427141Sgblack@eecs.umich.edu 4437141Sgblack@eecs.umich.edutemplate <class Impl> 4447141Sgblack@eecs.umich.eduvoid 4457141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4467141Sgblack@eecs.umich.edu{ 4477141Sgblack@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); 4487141Sgblack@eecs.umich.edu 4497141Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4507141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4517141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4527141Sgblack@eecs.umich.edu } 4537141Sgblack@eecs.umich.edu} 4547141Sgblack@eecs.umich.edu 4557141Sgblack@eecs.umich.edutemplate <class Impl> 4567141Sgblack@eecs.umich.eduvoid 4577141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 4587141Sgblack@eecs.umich.edu const MiscReg &val) 4597141Sgblack@eecs.umich.edu{ 4607141Sgblack@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->readTid()); 4617141Sgblack@eecs.umich.edu 4627141Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 4637141Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 4647141Sgblack@eecs.umich.edu cpu->squashFromTC(thread->readTid()); 4657141Sgblack@eecs.umich.edu } 4667141Sgblack@eecs.umich.edu} 4677141Sgblack@eecs.umich.edu 4687141Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4697141Sgblack@eecs.umich.edu 4707141Sgblack@eecs.umich.edutemplate <class Impl> 4717141Sgblack@eecs.umich.eduTheISA::IntReg 4727141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::getSyscallArg(int i) 4737141Sgblack@eecs.umich.edu{ 4747141Sgblack@eecs.umich.edu return cpu->getSyscallArg(i, thread->readTid()); 4757141Sgblack@eecs.umich.edu} 4767141Sgblack@eecs.umich.edu 4777141Sgblack@eecs.umich.edutemplate <class Impl> 4787141Sgblack@eecs.umich.eduvoid 4797141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 4807141Sgblack@eecs.umich.edu{ 4817141Sgblack@eecs.umich.edu cpu->setSyscallArg(i, val, thread->readTid()); 4827141Sgblack@eecs.umich.edu} 4837141Sgblack@eecs.umich.edu 4847141Sgblack@eecs.umich.edutemplate <class Impl> 4857141Sgblack@eecs.umich.eduvoid 4867141Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 4877141Sgblack@eecs.umich.edu{ 4887141Sgblack@eecs.umich.edu cpu->setSyscallReturn(return_value, thread->readTid()); 4897141Sgblack@eecs.umich.edu} 4907141Sgblack@eecs.umich.edu 4917141Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 4927141Sgblack@eecs.umich.edu 4937141Sgblack@eecs.umich.edu