thread_context_impl.hh revision 2817
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 322817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 332817Sksewell@umich.edu 342817Sksewell@umich.eduusing namespace TheISA; 352817Sksewell@umich.edu 362817Sksewell@umich.edu#if FULL_SYSTEM 372817Sksewell@umich.edutemplate <class Impl> 382817Sksewell@umich.eduVirtualPort * 392817Sksewell@umich.eduO3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc) 402817Sksewell@umich.edu{ 412817Sksewell@umich.edu if (!src_tc) 422817Sksewell@umich.edu return thread->getVirtPort(); 432817Sksewell@umich.edu 442817Sksewell@umich.edu VirtualPort *vp; 452817Sksewell@umich.edu Port *mem_port; 462817Sksewell@umich.edu 472817Sksewell@umich.edu vp = new VirtualPort("tc-vport", src_tc); 482817Sksewell@umich.edu mem_port = cpu->system->physmem->getPort("functional"); 492817Sksewell@umich.edu mem_port->setPeer(vp); 502817Sksewell@umich.edu vp->setPeer(mem_port); 512817Sksewell@umich.edu return vp; 522817Sksewell@umich.edu} 532817Sksewell@umich.edu 542817Sksewell@umich.edutemplate <class Impl> 552817Sksewell@umich.eduvoid 562817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 572817Sksewell@umich.edu{ 582817Sksewell@umich.edu // Currently not supported 592817Sksewell@umich.edu} 602817Sksewell@umich.edu#endif 612817Sksewell@umich.edu 622817Sksewell@umich.edutemplate <class Impl> 632817Sksewell@umich.eduvoid 642817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 652817Sksewell@umich.edu{ 662817Sksewell@umich.edu // some things should already be set up 672817Sksewell@umich.edu#if FULL_SYSTEM 682817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 692817Sksewell@umich.edu#else 702817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 712817Sksewell@umich.edu#endif 722817Sksewell@umich.edu 732817Sksewell@umich.edu // copy over functional state 742817Sksewell@umich.edu setStatus(old_context->status()); 752817Sksewell@umich.edu copyArchRegs(old_context); 762817Sksewell@umich.edu setCpuId(old_context->readCpuId()); 772817Sksewell@umich.edu 782817Sksewell@umich.edu#if !FULL_SYSTEM 792817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 802817Sksewell@umich.edu#else 812817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 822817Sksewell@umich.edu if (other_quiesce) { 832817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 842817Sksewell@umich.edu // the proper CPU. 852817Sksewell@umich.edu other_quiesce->tc = this; 862817Sksewell@umich.edu } 872817Sksewell@umich.edu if (thread->quiesceEvent) { 882817Sksewell@umich.edu thread->quiesceEvent->tc = this; 892817Sksewell@umich.edu } 902817Sksewell@umich.edu 912817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 922817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 932817Sksewell@umich.edu// storeCondFailures = 0; 942817Sksewell@umich.edu cpu->lockFlag = false; 952817Sksewell@umich.edu#endif 962817Sksewell@umich.edu 972817Sksewell@umich.edu old_context->setStatus(ThreadContext::Unallocated); 982817Sksewell@umich.edu 992817Sksewell@umich.edu thread->inSyscall = false; 1002817Sksewell@umich.edu thread->trapPending = false; 1012817Sksewell@umich.edu} 1022817Sksewell@umich.edu 1032817Sksewell@umich.edu#if FULL_SYSTEM 1042817Sksewell@umich.edutemplate <class Impl> 1052817Sksewell@umich.eduvoid 1062817Sksewell@umich.eduO3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) 1072817Sksewell@umich.edu{ 1082817Sksewell@umich.edu delete vp->getPeer(); 1092817Sksewell@umich.edu delete vp; 1102817Sksewell@umich.edu} 1112817Sksewell@umich.edu#endif 1122817Sksewell@umich.edu 1132817Sksewell@umich.edutemplate <class Impl> 1142817Sksewell@umich.eduvoid 1152817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 1162817Sksewell@umich.edu{ 1172817Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on AlphaTC\n"); 1182817Sksewell@umich.edu 1192817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1202817Sksewell@umich.edu return; 1212817Sksewell@umich.edu 1222817Sksewell@umich.edu#if FULL_SYSTEM 1232817Sksewell@umich.edu thread->lastActivate = curTick; 1242817Sksewell@umich.edu#endif 1252817Sksewell@umich.edu 1262817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) { 1272817Sksewell@umich.edu cpu->activateWhenReady(thread->readTid()); 1282817Sksewell@umich.edu return; 1292817Sksewell@umich.edu } 1302817Sksewell@umich.edu 1312817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1322817Sksewell@umich.edu 1332817Sksewell@umich.edu // status() == Suspended 1342817Sksewell@umich.edu cpu->activateContext(thread->readTid(), delay); 1352817Sksewell@umich.edu} 1362817Sksewell@umich.edu 1372817Sksewell@umich.edutemplate <class Impl> 1382817Sksewell@umich.eduvoid 1392817Sksewell@umich.eduO3ThreadContext<Impl>::suspend() 1402817Sksewell@umich.edu{ 1412817Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on AlphaTC\n"); 1422817Sksewell@umich.edu 1432817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1442817Sksewell@umich.edu return; 1452817Sksewell@umich.edu 1462817Sksewell@umich.edu#if FULL_SYSTEM 1472817Sksewell@umich.edu thread->lastActivate = curTick; 1482817Sksewell@umich.edu thread->lastSuspend = curTick; 1492817Sksewell@umich.edu#endif 1502817Sksewell@umich.edu/* 1512817Sksewell@umich.edu#if FULL_SYSTEM 1522817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1532817Sksewell@umich.edu if (cpu->check_interrupts()) { 1542817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1552817Sksewell@umich.edu return; 1562817Sksewell@umich.edu } 1572817Sksewell@umich.edu#endif 1582817Sksewell@umich.edu*/ 1592817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1602817Sksewell@umich.edu cpu->suspendContext(thread->readTid()); 1612817Sksewell@umich.edu} 1622817Sksewell@umich.edu 1632817Sksewell@umich.edutemplate <class Impl> 1642817Sksewell@umich.eduvoid 1652817Sksewell@umich.eduO3ThreadContext<Impl>::deallocate() 1662817Sksewell@umich.edu{ 1672817Sksewell@umich.edu DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n"); 1682817Sksewell@umich.edu 1692817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) 1702817Sksewell@umich.edu return; 1712817Sksewell@umich.edu 1722817Sksewell@umich.edu thread->setStatus(ThreadContext::Unallocated); 1732817Sksewell@umich.edu cpu->deallocateContext(thread->readTid()); 1742817Sksewell@umich.edu} 1752817Sksewell@umich.edu 1762817Sksewell@umich.edutemplate <class Impl> 1772817Sksewell@umich.eduvoid 1782817Sksewell@umich.eduO3ThreadContext<Impl>::halt() 1792817Sksewell@umich.edu{ 1802817Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on AlphaTC\n"); 1812817Sksewell@umich.edu 1822817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1832817Sksewell@umich.edu return; 1842817Sksewell@umich.edu 1852817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1862817Sksewell@umich.edu cpu->haltContext(thread->readTid()); 1872817Sksewell@umich.edu} 1882817Sksewell@umich.edu 1892817Sksewell@umich.edutemplate <class Impl> 1902817Sksewell@umich.eduvoid 1912817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1922817Sksewell@umich.edu{ 1932817Sksewell@umich.edu#if FULL_SYSTEM 1942817Sksewell@umich.edu thread->kernelStats = new Kernel::Statistics(cpu->system); 1952817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1962817Sksewell@umich.edu#endif 1972817Sksewell@umich.edu} 1982817Sksewell@umich.edu 1992817Sksewell@umich.edutemplate <class Impl> 2002817Sksewell@umich.eduvoid 2012817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 2022817Sksewell@umich.edu{ 2032817Sksewell@umich.edu#if FULL_SYSTEM 2042817Sksewell@umich.edu if (thread->kernelStats) 2052817Sksewell@umich.edu thread->kernelStats->serialize(os); 2062817Sksewell@umich.edu#endif 2072817Sksewell@umich.edu 2082817Sksewell@umich.edu} 2092817Sksewell@umich.edu 2102817Sksewell@umich.edutemplate <class Impl> 2112817Sksewell@umich.eduvoid 2122817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 2132817Sksewell@umich.edu{ 2142817Sksewell@umich.edu#if FULL_SYSTEM 2152817Sksewell@umich.edu if (thread->kernelStats) 2162817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 2172817Sksewell@umich.edu#endif 2182817Sksewell@umich.edu 2192817Sksewell@umich.edu} 2202817Sksewell@umich.edu 2212817Sksewell@umich.edu#if FULL_SYSTEM 2222817Sksewell@umich.edutemplate <class Impl> 2232817Sksewell@umich.eduTick 2242817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2252817Sksewell@umich.edu{ 2262817Sksewell@umich.edu return thread->lastActivate; 2272817Sksewell@umich.edu} 2282817Sksewell@umich.edu 2292817Sksewell@umich.edutemplate <class Impl> 2302817Sksewell@umich.eduTick 2312817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2322817Sksewell@umich.edu{ 2332817Sksewell@umich.edu return thread->lastSuspend; 2342817Sksewell@umich.edu} 2352817Sksewell@umich.edu 2362817Sksewell@umich.edutemplate <class Impl> 2372817Sksewell@umich.eduvoid 2382817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2392817Sksewell@umich.edu{} 2402817Sksewell@umich.edu 2412817Sksewell@umich.edutemplate <class Impl> 2422817Sksewell@umich.eduvoid 2432817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2442817Sksewell@umich.edu{} 2452817Sksewell@umich.edu#endif 2462817Sksewell@umich.edu 2472817Sksewell@umich.edutemplate <class Impl> 2482817Sksewell@umich.eduTheISA::MachInst 2492817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2502817Sksewell@umich.edu{ 2512817Sksewell@umich.edu return thread->getInst(); 2522817Sksewell@umich.edu} 2532817Sksewell@umich.edu 2542817Sksewell@umich.edutemplate <class Impl> 2552817Sksewell@umich.eduvoid 2562817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2572817Sksewell@umich.edu{ 2582817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2592817Sksewell@umich.edu // there are no instructions in the pipeline. 2602817Sksewell@umich.edu unsigned tid = thread->readTid(); 2612817Sksewell@umich.edu PhysRegIndex renamed_reg; 2622817Sksewell@umich.edu 2632817Sksewell@umich.edu // First loop through the integer registers. 2642817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2652817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2662817Sksewell@umich.edu 2672817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2682817Sksewell@umich.edu "now has data %lli.\n", 2692817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2702817Sksewell@umich.edu tc->readIntReg(i)); 2712817Sksewell@umich.edu 2722817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2732817Sksewell@umich.edu } 2742817Sksewell@umich.edu 2752817Sksewell@umich.edu // Then loop through the floating point registers. 2762817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2772817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2782817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2792817Sksewell@umich.edu tc->readFloatRegBits(i)); 2802817Sksewell@umich.edu } 2812817Sksewell@umich.edu 2822817Sksewell@umich.edu // Copy the misc regs. 2832817Sksewell@umich.edu copyMiscRegs(tc, this); 2842817Sksewell@umich.edu 2852817Sksewell@umich.edu // Then finally set the PC and the next PC. 2862817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2872817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2882817Sksewell@umich.edu#if !FULL_SYSTEM 2892817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2902817Sksewell@umich.edu#endif 2912817Sksewell@umich.edu} 2922817Sksewell@umich.edu 2932817Sksewell@umich.edutemplate <class Impl> 2942817Sksewell@umich.eduvoid 2952817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2962817Sksewell@umich.edu{} 2972817Sksewell@umich.edu 2982817Sksewell@umich.edutemplate <class Impl> 2992817Sksewell@umich.eduuint64_t 3002817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 3012817Sksewell@umich.edu{ 3022817Sksewell@umich.edu return cpu->readArchIntReg(reg_idx, thread->readTid()); 3032817Sksewell@umich.edu} 3042817Sksewell@umich.edu 3052817Sksewell@umich.edutemplate <class Impl> 3062817Sksewell@umich.eduFloatReg 3072817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 3082817Sksewell@umich.edu{ 3092817Sksewell@umich.edu switch(width) { 3102817Sksewell@umich.edu case 32: 3112817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3122817Sksewell@umich.edu case 64: 3132817Sksewell@umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); 3142817Sksewell@umich.edu default: 3152817Sksewell@umich.edu panic("Unsupported width!"); 3162817Sksewell@umich.edu return 0; 3172817Sksewell@umich.edu } 3182817Sksewell@umich.edu} 3192817Sksewell@umich.edu 3202817Sksewell@umich.edutemplate <class Impl> 3212817Sksewell@umich.eduFloatReg 3222817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 3232817Sksewell@umich.edu{ 3242817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3252817Sksewell@umich.edu} 3262817Sksewell@umich.edu 3272817Sksewell@umich.edutemplate <class Impl> 3282817Sksewell@umich.eduFloatRegBits 3292817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3302817Sksewell@umich.edu{ 3312817Sksewell@umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3322817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3332817Sksewell@umich.edu} 3342817Sksewell@umich.edu 3352817Sksewell@umich.edutemplate <class Impl> 3362817Sksewell@umich.eduFloatRegBits 3372817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3382817Sksewell@umich.edu{ 3392817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3402817Sksewell@umich.edu} 3412817Sksewell@umich.edu 3422817Sksewell@umich.edutemplate <class Impl> 3432817Sksewell@umich.eduvoid 3442817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3452817Sksewell@umich.edu{ 3462817Sksewell@umich.edu cpu->setArchIntReg(reg_idx, val, thread->readTid()); 3472817Sksewell@umich.edu 3482817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3492817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3502817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3512817Sksewell@umich.edu } 3522817Sksewell@umich.edu} 3532817Sksewell@umich.edu 3542817Sksewell@umich.edutemplate <class Impl> 3552817Sksewell@umich.eduvoid 3562817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3572817Sksewell@umich.edu{ 3582817Sksewell@umich.edu switch(width) { 3592817Sksewell@umich.edu case 32: 3602817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3612817Sksewell@umich.edu break; 3622817Sksewell@umich.edu case 64: 3632817Sksewell@umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); 3642817Sksewell@umich.edu break; 3652817Sksewell@umich.edu } 3662817Sksewell@umich.edu 3672817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3682817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3692817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3702817Sksewell@umich.edu } 3712817Sksewell@umich.edu} 3722817Sksewell@umich.edu 3732817Sksewell@umich.edutemplate <class Impl> 3742817Sksewell@umich.eduvoid 3752817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3762817Sksewell@umich.edu{ 3772817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3782817Sksewell@umich.edu 3792817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3802817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3812817Sksewell@umich.edu } 3822817Sksewell@umich.edu} 3832817Sksewell@umich.edu 3842817Sksewell@umich.edutemplate <class Impl> 3852817Sksewell@umich.eduvoid 3862817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3872817Sksewell@umich.edu int width) 3882817Sksewell@umich.edu{ 3892817Sksewell@umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3902817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 3912817Sksewell@umich.edu 3922817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3932817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3942817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3952817Sksewell@umich.edu } 3962817Sksewell@umich.edu} 3972817Sksewell@umich.edu 3982817Sksewell@umich.edutemplate <class Impl> 3992817Sksewell@umich.eduvoid 4002817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4012817Sksewell@umich.edu{ 4022817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 4032817Sksewell@umich.edu 4042817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4052817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4062817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4072817Sksewell@umich.edu } 4082817Sksewell@umich.edu} 4092817Sksewell@umich.edu 4102817Sksewell@umich.edutemplate <class Impl> 4112817Sksewell@umich.eduvoid 4122817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 4132817Sksewell@umich.edu{ 4142817Sksewell@umich.edu cpu->setPC(val, thread->readTid()); 4152817Sksewell@umich.edu 4162817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4172817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4182817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4192817Sksewell@umich.edu } 4202817Sksewell@umich.edu} 4212817Sksewell@umich.edu 4222817Sksewell@umich.edutemplate <class Impl> 4232817Sksewell@umich.eduvoid 4242817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4252817Sksewell@umich.edu{ 4262817Sksewell@umich.edu cpu->setNextPC(val, thread->readTid()); 4272817Sksewell@umich.edu 4282817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4292817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4302817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4312817Sksewell@umich.edu } 4322817Sksewell@umich.edu} 4332817Sksewell@umich.edu 4342817Sksewell@umich.edutemplate <class Impl> 4352817Sksewell@umich.eduFault 4362817Sksewell@umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 4372817Sksewell@umich.edu{ 4382817Sksewell@umich.edu Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); 4392817Sksewell@umich.edu 4402817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4412817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4422817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4432817Sksewell@umich.edu } 4442817Sksewell@umich.edu 4452817Sksewell@umich.edu return ret_fault; 4462817Sksewell@umich.edu} 4472817Sksewell@umich.edu 4482817Sksewell@umich.edutemplate <class Impl> 4492817Sksewell@umich.eduFault 4502817Sksewell@umich.eduO3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg, 4512817Sksewell@umich.edu const MiscReg &val) 4522817Sksewell@umich.edu{ 4532817Sksewell@umich.edu Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, 4542817Sksewell@umich.edu thread->readTid()); 4552817Sksewell@umich.edu 4562817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4572817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4582817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4592817Sksewell@umich.edu } 4602817Sksewell@umich.edu 4612817Sksewell@umich.edu return ret_fault; 4622817Sksewell@umich.edu} 4632817Sksewell@umich.edu 4642817Sksewell@umich.edu#if !FULL_SYSTEM 4652817Sksewell@umich.edu 4662817Sksewell@umich.edutemplate <class Impl> 4672817Sksewell@umich.eduTheISA::IntReg 4682817Sksewell@umich.eduO3ThreadContext<Impl>::getSyscallArg(int i) 4692817Sksewell@umich.edu{ 4702817Sksewell@umich.edu return cpu->getSyscallArg(i, thread->readTid()); 4712817Sksewell@umich.edu} 4722817Sksewell@umich.edu 4732817Sksewell@umich.edutemplate <class Impl> 4742817Sksewell@umich.eduvoid 4752817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 4762817Sksewell@umich.edu{ 4772817Sksewell@umich.edu cpu->setSyscallArg(i, val, thread->readTid()); 4782817Sksewell@umich.edu} 4792817Sksewell@umich.edu 4802817Sksewell@umich.edutemplate <class Impl> 4812817Sksewell@umich.eduvoid 4822817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 4832817Sksewell@umich.edu{ 4842817Sksewell@umich.edu cpu->setSyscallReturn(return_value, thread->readTid()); 4852817Sksewell@umich.edu} 4862817Sksewell@umich.edu 4872817Sksewell@umich.edu#endif // FULL_SYSTEM 4882817Sksewell@umich.edu 489