thread_context_impl.hh revision 13641
12817Sksewell@umich.edu/* 212279Snikos.nikoleris@arm.com * Copyright (c) 2010-2012, 2016-2017 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47763SAli.Saidi@ARM.com * All rights reserved 57763SAli.Saidi@ARM.com * 67763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147763SAli.Saidi@ARM.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu * Korey Sewell 432817Sksewell@umich.edu */ 442817Sksewell@umich.edu 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 479944Smatt.horsnell@ARM.com 4813601Sgiacomo.travaglini@arm.com#include "arch/generic/traits.hh" 498793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 522817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 532834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 548232Snate@binkert.org#include "debug/O3CPU.hh" 552817Sksewell@umich.edu 562817Sksewell@umich.edutemplate <class Impl> 578852Sandreas.hansson@arm.comFSTranslatingPortProxy& 588706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 592817Sksewell@umich.edu{ 608706Sandreas.hansson@arm.com return thread->getVirtProxy(); 612817Sksewell@umich.edu} 622817Sksewell@umich.edu 632817Sksewell@umich.edutemplate <class Impl> 642817Sksewell@umich.eduvoid 652817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 662817Sksewell@umich.edu{ 673126Sktlim@umich.edu thread->dumpFuncProfile(); 682817Sksewell@umich.edu} 692817Sksewell@umich.edu 702817Sksewell@umich.edutemplate <class Impl> 712817Sksewell@umich.eduvoid 722817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 732817Sksewell@umich.edu{ 749441SAndreas.Sandberg@ARM.com ::takeOverFrom(*this, *old_context); 759478Snilay@cs.wisc.edu TheISA::Decoder *newDecoder = getDecoderPtr(); 769478Snilay@cs.wisc.edu TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 779478Snilay@cs.wisc.edu newDecoder->takeOverFrom(oldDecoder); 782817Sksewell@umich.edu 799441SAndreas.Sandberg@ARM.com thread->kernelStats = old_context->getKernelStats(); 809441SAndreas.Sandberg@ARM.com thread->funcExeInst = old_context->readFuncExeInst(); 812817Sksewell@umich.edu 829382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 832817Sksewell@umich.edu thread->trapPending = false; 842817Sksewell@umich.edu} 852817Sksewell@umich.edu 862817Sksewell@umich.edutemplate <class Impl> 872817Sksewell@umich.eduvoid 8810407Smitch.hayenga@arm.comO3ThreadContext<Impl>::activate() 892817Sksewell@umich.edu{ 902875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 915715Shsul@eecs.umich.edu threadId()); 922817Sksewell@umich.edu 932817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 942817Sksewell@umich.edu return; 952817Sksewell@umich.edu 967823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 972817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 982817Sksewell@umich.edu 992817Sksewell@umich.edu // status() == Suspended 10010407Smitch.hayenga@arm.com cpu->activateContext(thread->threadId()); 1012817Sksewell@umich.edu} 1022817Sksewell@umich.edu 1032817Sksewell@umich.edutemplate <class Impl> 1042817Sksewell@umich.eduvoid 10510407Smitch.hayenga@arm.comO3ThreadContext<Impl>::suspend() 1062817Sksewell@umich.edu{ 1072875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1085715Shsul@eecs.umich.edu threadId()); 1092817Sksewell@umich.edu 1102817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1112817Sksewell@umich.edu return; 1122817Sksewell@umich.edu 11312279Snikos.nikoleris@arm.com if (cpu->isDraining()) { 11412279Snikos.nikoleris@arm.com DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n"); 11512279Snikos.nikoleris@arm.com return; 11612279Snikos.nikoleris@arm.com } 11712279Snikos.nikoleris@arm.com 1187823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1197823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1208793Sgblack@eecs.umich.edu 1212817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1225715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1232817Sksewell@umich.edu} 1242817Sksewell@umich.edu 1252817Sksewell@umich.edutemplate <class Impl> 1262817Sksewell@umich.eduvoid 12710407Smitch.hayenga@arm.comO3ThreadContext<Impl>::halt() 1282817Sksewell@umich.edu{ 12910407Smitch.hayenga@arm.com DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId()); 1302817Sksewell@umich.edu 13113641Sqtt2@cornell.edu if (thread->status() == ThreadContext::Halting || 13213641Sqtt2@cornell.edu thread->status() == ThreadContext::Halted) 1332817Sksewell@umich.edu return; 1342817Sksewell@umich.edu 13513641Sqtt2@cornell.edu // the thread is not going to halt/terminate immediately in this cycle. 13613641Sqtt2@cornell.edu // The thread will be removed after an exit trap is processed 13713641Sqtt2@cornell.edu // (e.g., after trapLatency cycles). Until then, the thread's status 13813641Sqtt2@cornell.edu // will be Halting. 13913641Sqtt2@cornell.edu thread->setStatus(ThreadContext::Halting); 14013641Sqtt2@cornell.edu 14113641Sqtt2@cornell.edu // add this thread to the exiting list to mark that it is trying to exit. 14213641Sqtt2@cornell.edu cpu->addThreadToExitingList(thread->threadId()); 1432817Sksewell@umich.edu} 1442817Sksewell@umich.edu 1452817Sksewell@umich.edutemplate <class Impl> 1462817Sksewell@umich.eduvoid 1472817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1482817Sksewell@umich.edu{ 1498793Sgblack@eecs.umich.edu if (FullSystem) { 15012181Sgabeblack@google.com thread->kernelStats = new TheISA::Kernel::Statistics(); 1518793Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1528793Sgblack@eecs.umich.edu } 1532817Sksewell@umich.edu} 1542817Sksewell@umich.edu 1552817Sksewell@umich.edutemplate <class Impl> 1562817Sksewell@umich.eduTick 1572817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1582817Sksewell@umich.edu{ 1592817Sksewell@umich.edu return thread->lastActivate; 1602817Sksewell@umich.edu} 1612817Sksewell@umich.edu 1622817Sksewell@umich.edutemplate <class Impl> 1632817Sksewell@umich.eduTick 1642817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1652817Sksewell@umich.edu{ 1662817Sksewell@umich.edu return thread->lastSuspend; 1672817Sksewell@umich.edu} 1682817Sksewell@umich.edu 1692817Sksewell@umich.edutemplate <class Impl> 1702817Sksewell@umich.eduvoid 1712817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 1723126Sktlim@umich.edu{ 1733126Sktlim@umich.edu thread->profileClear(); 1743126Sktlim@umich.edu} 1752817Sksewell@umich.edu 1762817Sksewell@umich.edutemplate <class Impl> 1772817Sksewell@umich.eduvoid 1782817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 1793126Sktlim@umich.edu{ 1803126Sktlim@umich.edu thread->profileSample(); 1813126Sktlim@umich.edu} 1822817Sksewell@umich.edu 1832817Sksewell@umich.edutemplate <class Impl> 1842817Sksewell@umich.eduvoid 1852817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 1862817Sksewell@umich.edu{ 18713601Sgiacomo.travaglini@arm.com // Set vector renaming mode before copying registers 18813601Sgiacomo.travaglini@arm.com cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState())); 18913601Sgiacomo.travaglini@arm.com 1908208SAli.Saidi@ARM.com // Prevent squashing 1919382SAli.Saidi@ARM.com thread->noSquashFromTC = true; 1928208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 1939382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 1942817Sksewell@umich.edu 1958793Sgblack@eecs.umich.edu if (!FullSystem) 1968793Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 1972817Sksewell@umich.edu} 1982817Sksewell@umich.edu 1992817Sksewell@umich.edutemplate <class Impl> 2002817Sksewell@umich.eduvoid 2012817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2027763SAli.Saidi@ARM.com{ 2039384SAndreas.Sandberg@arm.com cpu->isa[thread->threadId()]->clear(); 2047763SAli.Saidi@ARM.com} 2052817Sksewell@umich.edu 2062817Sksewell@umich.edutemplate <class Impl> 20713557Sgabeblack@google.comRegVal 2089426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 2092817Sksewell@umich.edu{ 2105715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2112817Sksewell@umich.edu} 2122817Sksewell@umich.edu 2132817Sksewell@umich.edutemplate <class Impl> 21413557Sgabeblack@google.comRegVal 21513611Sgabeblack@google.comO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 2162817Sksewell@umich.edu{ 21713611Sgabeblack@google.com return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2182817Sksewell@umich.edu} 2192817Sksewell@umich.edu 2202817Sksewell@umich.edutemplate <class Impl> 22112109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecRegContainer& 22212109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecRegFlat(int reg_id) const 22312109SRekai.GonzalezAlberquilla@arm.com{ 22412109SRekai.GonzalezAlberquilla@arm.com return cpu->readArchVecReg(reg_id, thread->threadId()); 22512109SRekai.GonzalezAlberquilla@arm.com} 22612109SRekai.GonzalezAlberquilla@arm.com 22712109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 22812109SRekai.GonzalezAlberquilla@arm.comTheISA::VecRegContainer& 22912109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id) 23012109SRekai.GonzalezAlberquilla@arm.com{ 23112109SRekai.GonzalezAlberquilla@arm.com return cpu->getWritableArchVecReg(reg_id, thread->threadId()); 23212109SRekai.GonzalezAlberquilla@arm.com} 23312109SRekai.GonzalezAlberquilla@arm.com 23412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 23512109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecElem& 23612109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx, 23712109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 23812109SRekai.GonzalezAlberquilla@arm.com{ 23912109SRekai.GonzalezAlberquilla@arm.com return cpu->readArchVecElem(idx, elemIndex, thread->threadId()); 24012109SRekai.GonzalezAlberquilla@arm.com} 24112109SRekai.GonzalezAlberquilla@arm.com 24212109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 24313610Sgiacomo.gabrielli@arm.comconst TheISA::VecPredRegContainer& 24413610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const 24513610Sgiacomo.gabrielli@arm.com{ 24613610Sgiacomo.gabrielli@arm.com return cpu->readArchVecPredReg(reg_id, thread->threadId()); 24713610Sgiacomo.gabrielli@arm.com} 24813610Sgiacomo.gabrielli@arm.com 24913610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 25013610Sgiacomo.gabrielli@arm.comTheISA::VecPredRegContainer& 25113610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id) 25213610Sgiacomo.gabrielli@arm.com{ 25313610Sgiacomo.gabrielli@arm.com return cpu->getWritableArchVecPredReg(reg_id, thread->threadId()); 25413610Sgiacomo.gabrielli@arm.com} 25513610Sgiacomo.gabrielli@arm.com 25613610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 25713622Sgabeblack@google.comRegVal 2589920Syasuko.eckert@amd.comO3ThreadContext<Impl>::readCCRegFlat(int reg_idx) 2599920Syasuko.eckert@amd.com{ 2609920Syasuko.eckert@amd.com return cpu->readArchCCReg(reg_idx, thread->threadId()); 2619920Syasuko.eckert@amd.com} 2629920Syasuko.eckert@amd.com 2639920Syasuko.eckert@amd.comtemplate <class Impl> 2642817Sksewell@umich.eduvoid 26513557Sgabeblack@google.comO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) 2662817Sksewell@umich.edu{ 2675715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2682817Sksewell@umich.edu 2699382SAli.Saidi@ARM.com conditionalSquash(); 2702817Sksewell@umich.edu} 2712817Sksewell@umich.edu 2722817Sksewell@umich.edutemplate <class Impl> 2732817Sksewell@umich.eduvoid 27413611Sgabeblack@google.comO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val) 2752817Sksewell@umich.edu{ 27613611Sgabeblack@google.com cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2772817Sksewell@umich.edu 2789382SAli.Saidi@ARM.com conditionalSquash(); 2792817Sksewell@umich.edu} 2802817Sksewell@umich.edu 2812817Sksewell@umich.edutemplate <class Impl> 2822817Sksewell@umich.eduvoid 28312109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val) 28412109SRekai.GonzalezAlberquilla@arm.com{ 28512109SRekai.GonzalezAlberquilla@arm.com cpu->setArchVecReg(reg_idx, val, thread->threadId()); 28612109SRekai.GonzalezAlberquilla@arm.com 28712109SRekai.GonzalezAlberquilla@arm.com conditionalSquash(); 28812109SRekai.GonzalezAlberquilla@arm.com} 28912109SRekai.GonzalezAlberquilla@arm.com 29012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 29112109SRekai.GonzalezAlberquilla@arm.comvoid 29212109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx, 29312109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex, const VecElem& val) 29412109SRekai.GonzalezAlberquilla@arm.com{ 29512109SRekai.GonzalezAlberquilla@arm.com cpu->setArchVecElem(idx, elemIndex, val, thread->threadId()); 29612109SRekai.GonzalezAlberquilla@arm.com conditionalSquash(); 29712109SRekai.GonzalezAlberquilla@arm.com} 29812109SRekai.GonzalezAlberquilla@arm.com 29912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 30012109SRekai.GonzalezAlberquilla@arm.comvoid 30113610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx, 30213610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 30313610Sgiacomo.gabrielli@arm.com{ 30413610Sgiacomo.gabrielli@arm.com cpu->setArchVecPredReg(reg_idx, val, thread->threadId()); 30513610Sgiacomo.gabrielli@arm.com 30613610Sgiacomo.gabrielli@arm.com conditionalSquash(); 30713610Sgiacomo.gabrielli@arm.com} 30813610Sgiacomo.gabrielli@arm.com 30913610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 31013610Sgiacomo.gabrielli@arm.comvoid 31113622Sgabeblack@google.comO3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val) 3129920Syasuko.eckert@amd.com{ 3139920Syasuko.eckert@amd.com cpu->setArchCCReg(reg_idx, val, thread->threadId()); 3149920Syasuko.eckert@amd.com 3159920Syasuko.eckert@amd.com conditionalSquash(); 3169920Syasuko.eckert@amd.com} 3179920Syasuko.eckert@amd.com 3189920Syasuko.eckert@amd.comtemplate <class Impl> 3199920Syasuko.eckert@amd.comvoid 3207720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3212817Sksewell@umich.edu{ 3227720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3235258Sksewell@umich.edu 3249382SAli.Saidi@ARM.com conditionalSquash(); 3255258Sksewell@umich.edu} 3265258Sksewell@umich.edu 3278733Sgeoffrey.blake@arm.comtemplate <class Impl> 3288733Sgeoffrey.blake@arm.comvoid 3298733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 3308733Sgeoffrey.blake@arm.com{ 3318733Sgeoffrey.blake@arm.com cpu->pcState(val, thread->threadId()); 3328733Sgeoffrey.blake@arm.com 3339382SAli.Saidi@ARM.com conditionalSquash(); 3348733Sgeoffrey.blake@arm.com} 3358733Sgeoffrey.blake@arm.com 3365258Sksewell@umich.edutemplate <class Impl> 33712106SRekai.GonzalezAlberquilla@arm.comRegId 33812106SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::flattenRegId(const RegId& regId) const 3396313Sgblack@eecs.umich.edu{ 34012106SRekai.GonzalezAlberquilla@arm.com return cpu->isa[thread->threadId()]->flattenRegId(regId); 34110033SAli.Saidi@ARM.com} 34210033SAli.Saidi@ARM.com 34310033SAli.Saidi@ARM.comtemplate <class Impl> 3445258Sksewell@umich.eduvoid 34513582Sgabeblack@google.comO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val) 3462817Sksewell@umich.edu{ 3475715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3482817Sksewell@umich.edu 3499382SAli.Saidi@ARM.com conditionalSquash(); 3502817Sksewell@umich.edu} 3512817Sksewell@umich.edu 3529944Smatt.horsnell@ARM.com#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 3532817Sksewell@umich.edutemplate <class Impl> 3543468Sgblack@eecs.umich.eduvoid 35513582Sgabeblack@google.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val) 3562817Sksewell@umich.edu{ 3575715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3582817Sksewell@umich.edu 3599382SAli.Saidi@ARM.com conditionalSquash(); 3602817Sksewell@umich.edu} 3612817Sksewell@umich.edu 362