thread_context_impl.hh revision 13622
12817Sksewell@umich.edu/* 212279Snikos.nikoleris@arm.com * Copyright (c) 2010-2012, 2016-2017 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47763SAli.Saidi@ARM.com * All rights reserved 57763SAli.Saidi@ARM.com * 67763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147763SAli.Saidi@ARM.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu * Korey Sewell 432817Sksewell@umich.edu */ 442817Sksewell@umich.edu 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 479944Smatt.horsnell@ARM.com 4813601Sgiacomo.travaglini@arm.com#include "arch/generic/traits.hh" 498793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 522817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 532834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 548232Snate@binkert.org#include "debug/O3CPU.hh" 552817Sksewell@umich.edu 562817Sksewell@umich.edutemplate <class Impl> 578852Sandreas.hansson@arm.comFSTranslatingPortProxy& 588706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 592817Sksewell@umich.edu{ 608706Sandreas.hansson@arm.com return thread->getVirtProxy(); 612817Sksewell@umich.edu} 622817Sksewell@umich.edu 632817Sksewell@umich.edutemplate <class Impl> 642817Sksewell@umich.eduvoid 652817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 662817Sksewell@umich.edu{ 673126Sktlim@umich.edu thread->dumpFuncProfile(); 682817Sksewell@umich.edu} 692817Sksewell@umich.edu 702817Sksewell@umich.edutemplate <class Impl> 712817Sksewell@umich.eduvoid 722817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 732817Sksewell@umich.edu{ 749441SAndreas.Sandberg@ARM.com ::takeOverFrom(*this, *old_context); 759478Snilay@cs.wisc.edu TheISA::Decoder *newDecoder = getDecoderPtr(); 769478Snilay@cs.wisc.edu TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 779478Snilay@cs.wisc.edu newDecoder->takeOverFrom(oldDecoder); 782817Sksewell@umich.edu 799441SAndreas.Sandberg@ARM.com thread->kernelStats = old_context->getKernelStats(); 809441SAndreas.Sandberg@ARM.com thread->funcExeInst = old_context->readFuncExeInst(); 812817Sksewell@umich.edu 829382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 832817Sksewell@umich.edu thread->trapPending = false; 842817Sksewell@umich.edu} 852817Sksewell@umich.edu 862817Sksewell@umich.edutemplate <class Impl> 872817Sksewell@umich.eduvoid 8810407Smitch.hayenga@arm.comO3ThreadContext<Impl>::activate() 892817Sksewell@umich.edu{ 902875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 915715Shsul@eecs.umich.edu threadId()); 922817Sksewell@umich.edu 932817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 942817Sksewell@umich.edu return; 952817Sksewell@umich.edu 967823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 972817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 982817Sksewell@umich.edu 992817Sksewell@umich.edu // status() == Suspended 10010407Smitch.hayenga@arm.com cpu->activateContext(thread->threadId()); 1012817Sksewell@umich.edu} 1022817Sksewell@umich.edu 1032817Sksewell@umich.edutemplate <class Impl> 1042817Sksewell@umich.eduvoid 10510407Smitch.hayenga@arm.comO3ThreadContext<Impl>::suspend() 1062817Sksewell@umich.edu{ 1072875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1085715Shsul@eecs.umich.edu threadId()); 1092817Sksewell@umich.edu 1102817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1112817Sksewell@umich.edu return; 1122817Sksewell@umich.edu 11312279Snikos.nikoleris@arm.com if (cpu->isDraining()) { 11412279Snikos.nikoleris@arm.com DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n"); 11512279Snikos.nikoleris@arm.com return; 11612279Snikos.nikoleris@arm.com } 11712279Snikos.nikoleris@arm.com 1187823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1197823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1208793Sgblack@eecs.umich.edu 1212817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1225715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1232817Sksewell@umich.edu} 1242817Sksewell@umich.edu 1252817Sksewell@umich.edutemplate <class Impl> 1262817Sksewell@umich.eduvoid 12710407Smitch.hayenga@arm.comO3ThreadContext<Impl>::halt() 1282817Sksewell@umich.edu{ 12910407Smitch.hayenga@arm.com DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId()); 1302817Sksewell@umich.edu 1312817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1322817Sksewell@umich.edu return; 1332817Sksewell@umich.edu 1342817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1355715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1362817Sksewell@umich.edu} 1372817Sksewell@umich.edu 1382817Sksewell@umich.edutemplate <class Impl> 1392817Sksewell@umich.eduvoid 1402817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1412817Sksewell@umich.edu{ 1428793Sgblack@eecs.umich.edu if (FullSystem) { 14312181Sgabeblack@google.com thread->kernelStats = new TheISA::Kernel::Statistics(); 1448793Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1458793Sgblack@eecs.umich.edu } 1462817Sksewell@umich.edu} 1472817Sksewell@umich.edu 1482817Sksewell@umich.edutemplate <class Impl> 1492817Sksewell@umich.eduTick 1502817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1512817Sksewell@umich.edu{ 1522817Sksewell@umich.edu return thread->lastActivate; 1532817Sksewell@umich.edu} 1542817Sksewell@umich.edu 1552817Sksewell@umich.edutemplate <class Impl> 1562817Sksewell@umich.eduTick 1572817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1582817Sksewell@umich.edu{ 1592817Sksewell@umich.edu return thread->lastSuspend; 1602817Sksewell@umich.edu} 1612817Sksewell@umich.edu 1622817Sksewell@umich.edutemplate <class Impl> 1632817Sksewell@umich.eduvoid 1642817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 1653126Sktlim@umich.edu{ 1663126Sktlim@umich.edu thread->profileClear(); 1673126Sktlim@umich.edu} 1682817Sksewell@umich.edu 1692817Sksewell@umich.edutemplate <class Impl> 1702817Sksewell@umich.eduvoid 1712817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 1723126Sktlim@umich.edu{ 1733126Sktlim@umich.edu thread->profileSample(); 1743126Sktlim@umich.edu} 1752817Sksewell@umich.edu 1762817Sksewell@umich.edutemplate <class Impl> 1772817Sksewell@umich.eduvoid 1782817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 1792817Sksewell@umich.edu{ 18013601Sgiacomo.travaglini@arm.com // Set vector renaming mode before copying registers 18113601Sgiacomo.travaglini@arm.com cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState())); 18213601Sgiacomo.travaglini@arm.com 1838208SAli.Saidi@ARM.com // Prevent squashing 1849382SAli.Saidi@ARM.com thread->noSquashFromTC = true; 1858208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 1869382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 1872817Sksewell@umich.edu 1888793Sgblack@eecs.umich.edu if (!FullSystem) 1898793Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 1902817Sksewell@umich.edu} 1912817Sksewell@umich.edu 1922817Sksewell@umich.edutemplate <class Impl> 1932817Sksewell@umich.eduvoid 1942817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 1957763SAli.Saidi@ARM.com{ 1969384SAndreas.Sandberg@arm.com cpu->isa[thread->threadId()]->clear(); 1977763SAli.Saidi@ARM.com} 1982817Sksewell@umich.edu 1992817Sksewell@umich.edutemplate <class Impl> 20013557Sgabeblack@google.comRegVal 2019426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 2022817Sksewell@umich.edu{ 2035715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2042817Sksewell@umich.edu} 2052817Sksewell@umich.edu 2062817Sksewell@umich.edutemplate <class Impl> 20713557Sgabeblack@google.comRegVal 20813611Sgabeblack@google.comO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 2092817Sksewell@umich.edu{ 21013611Sgabeblack@google.com return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2112817Sksewell@umich.edu} 2122817Sksewell@umich.edu 2132817Sksewell@umich.edutemplate <class Impl> 21412109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecRegContainer& 21512109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecRegFlat(int reg_id) const 21612109SRekai.GonzalezAlberquilla@arm.com{ 21712109SRekai.GonzalezAlberquilla@arm.com return cpu->readArchVecReg(reg_id, thread->threadId()); 21812109SRekai.GonzalezAlberquilla@arm.com} 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 22112109SRekai.GonzalezAlberquilla@arm.comTheISA::VecRegContainer& 22212109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id) 22312109SRekai.GonzalezAlberquilla@arm.com{ 22412109SRekai.GonzalezAlberquilla@arm.com return cpu->getWritableArchVecReg(reg_id, thread->threadId()); 22512109SRekai.GonzalezAlberquilla@arm.com} 22612109SRekai.GonzalezAlberquilla@arm.com 22712109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 22812109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecElem& 22912109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx, 23012109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 23112109SRekai.GonzalezAlberquilla@arm.com{ 23212109SRekai.GonzalezAlberquilla@arm.com return cpu->readArchVecElem(idx, elemIndex, thread->threadId()); 23312109SRekai.GonzalezAlberquilla@arm.com} 23412109SRekai.GonzalezAlberquilla@arm.com 23512109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 23613610Sgiacomo.gabrielli@arm.comconst TheISA::VecPredRegContainer& 23713610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const 23813610Sgiacomo.gabrielli@arm.com{ 23913610Sgiacomo.gabrielli@arm.com return cpu->readArchVecPredReg(reg_id, thread->threadId()); 24013610Sgiacomo.gabrielli@arm.com} 24113610Sgiacomo.gabrielli@arm.com 24213610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 24313610Sgiacomo.gabrielli@arm.comTheISA::VecPredRegContainer& 24413610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id) 24513610Sgiacomo.gabrielli@arm.com{ 24613610Sgiacomo.gabrielli@arm.com return cpu->getWritableArchVecPredReg(reg_id, thread->threadId()); 24713610Sgiacomo.gabrielli@arm.com} 24813610Sgiacomo.gabrielli@arm.com 24913610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 25013622Sgabeblack@google.comRegVal 2519920Syasuko.eckert@amd.comO3ThreadContext<Impl>::readCCRegFlat(int reg_idx) 2529920Syasuko.eckert@amd.com{ 2539920Syasuko.eckert@amd.com return cpu->readArchCCReg(reg_idx, thread->threadId()); 2549920Syasuko.eckert@amd.com} 2559920Syasuko.eckert@amd.com 2569920Syasuko.eckert@amd.comtemplate <class Impl> 2572817Sksewell@umich.eduvoid 25813557Sgabeblack@google.comO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) 2592817Sksewell@umich.edu{ 2605715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2612817Sksewell@umich.edu 2629382SAli.Saidi@ARM.com conditionalSquash(); 2632817Sksewell@umich.edu} 2642817Sksewell@umich.edu 2652817Sksewell@umich.edutemplate <class Impl> 2662817Sksewell@umich.eduvoid 26713611Sgabeblack@google.comO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val) 2682817Sksewell@umich.edu{ 26913611Sgabeblack@google.com cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2702817Sksewell@umich.edu 2719382SAli.Saidi@ARM.com conditionalSquash(); 2722817Sksewell@umich.edu} 2732817Sksewell@umich.edu 2742817Sksewell@umich.edutemplate <class Impl> 2752817Sksewell@umich.eduvoid 27612109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val) 27712109SRekai.GonzalezAlberquilla@arm.com{ 27812109SRekai.GonzalezAlberquilla@arm.com cpu->setArchVecReg(reg_idx, val, thread->threadId()); 27912109SRekai.GonzalezAlberquilla@arm.com 28012109SRekai.GonzalezAlberquilla@arm.com conditionalSquash(); 28112109SRekai.GonzalezAlberquilla@arm.com} 28212109SRekai.GonzalezAlberquilla@arm.com 28312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 28412109SRekai.GonzalezAlberquilla@arm.comvoid 28512109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx, 28612109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex, const VecElem& val) 28712109SRekai.GonzalezAlberquilla@arm.com{ 28812109SRekai.GonzalezAlberquilla@arm.com cpu->setArchVecElem(idx, elemIndex, val, thread->threadId()); 28912109SRekai.GonzalezAlberquilla@arm.com conditionalSquash(); 29012109SRekai.GonzalezAlberquilla@arm.com} 29112109SRekai.GonzalezAlberquilla@arm.com 29212109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 29312109SRekai.GonzalezAlberquilla@arm.comvoid 29413610Sgiacomo.gabrielli@arm.comO3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx, 29513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 29613610Sgiacomo.gabrielli@arm.com{ 29713610Sgiacomo.gabrielli@arm.com cpu->setArchVecPredReg(reg_idx, val, thread->threadId()); 29813610Sgiacomo.gabrielli@arm.com 29913610Sgiacomo.gabrielli@arm.com conditionalSquash(); 30013610Sgiacomo.gabrielli@arm.com} 30113610Sgiacomo.gabrielli@arm.com 30213610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 30313610Sgiacomo.gabrielli@arm.comvoid 30413622Sgabeblack@google.comO3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val) 3059920Syasuko.eckert@amd.com{ 3069920Syasuko.eckert@amd.com cpu->setArchCCReg(reg_idx, val, thread->threadId()); 3079920Syasuko.eckert@amd.com 3089920Syasuko.eckert@amd.com conditionalSquash(); 3099920Syasuko.eckert@amd.com} 3109920Syasuko.eckert@amd.com 3119920Syasuko.eckert@amd.comtemplate <class Impl> 3129920Syasuko.eckert@amd.comvoid 3137720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3142817Sksewell@umich.edu{ 3157720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3165258Sksewell@umich.edu 3179382SAli.Saidi@ARM.com conditionalSquash(); 3185258Sksewell@umich.edu} 3195258Sksewell@umich.edu 3208733Sgeoffrey.blake@arm.comtemplate <class Impl> 3218733Sgeoffrey.blake@arm.comvoid 3228733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 3238733Sgeoffrey.blake@arm.com{ 3248733Sgeoffrey.blake@arm.com cpu->pcState(val, thread->threadId()); 3258733Sgeoffrey.blake@arm.com 3269382SAli.Saidi@ARM.com conditionalSquash(); 3278733Sgeoffrey.blake@arm.com} 3288733Sgeoffrey.blake@arm.com 3295258Sksewell@umich.edutemplate <class Impl> 33012106SRekai.GonzalezAlberquilla@arm.comRegId 33112106SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::flattenRegId(const RegId& regId) const 3326313Sgblack@eecs.umich.edu{ 33312106SRekai.GonzalezAlberquilla@arm.com return cpu->isa[thread->threadId()]->flattenRegId(regId); 33410033SAli.Saidi@ARM.com} 33510033SAli.Saidi@ARM.com 33610033SAli.Saidi@ARM.comtemplate <class Impl> 3375258Sksewell@umich.eduvoid 33813582Sgabeblack@google.comO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val) 3392817Sksewell@umich.edu{ 3405715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3412817Sksewell@umich.edu 3429382SAli.Saidi@ARM.com conditionalSquash(); 3432817Sksewell@umich.edu} 3442817Sksewell@umich.edu 3459944Smatt.horsnell@ARM.com#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 3462817Sksewell@umich.edutemplate <class Impl> 3473468Sgblack@eecs.umich.eduvoid 34813582Sgabeblack@google.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val) 3492817Sksewell@umich.edu{ 3505715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3512817Sksewell@umich.edu 3529382SAli.Saidi@ARM.com conditionalSquash(); 3532817Sksewell@umich.edu} 3542817Sksewell@umich.edu 355