thread_context_impl.hh revision 12279
12817Sksewell@umich.edu/*
212279Snikos.nikoleris@arm.com * Copyright (c) 2010-2012, 2016-2017 ARM Limited
39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
47763SAli.Saidi@ARM.com * All rights reserved
57763SAli.Saidi@ARM.com *
67763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
77763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
87763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
97763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
107763SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
117763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
127763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
137763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
147763SAli.Saidi@ARM.com *
152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan
162817Sksewell@umich.edu * All rights reserved.
172817Sksewell@umich.edu *
182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are
202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
272817Sksewell@umich.edu * this software without specific prior written permission.
282817Sksewell@umich.edu *
292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402817Sksewell@umich.edu *
412817Sksewell@umich.edu * Authors: Kevin Lim
422817Sksewell@umich.edu *          Korey Sewell
432817Sksewell@umich.edu */
442817Sksewell@umich.edu
459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
469944Smatt.horsnell@ARM.com#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
479944Smatt.horsnell@ARM.com
488793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh"
496329Sgblack@eecs.umich.edu#include "arch/registers.hh"
506658Snate@binkert.org#include "config/the_isa.hh"
512817Sksewell@umich.edu#include "cpu/o3/thread_context.hh"
522834Sksewell@umich.edu#include "cpu/quiesce_event.hh"
538232Snate@binkert.org#include "debug/O3CPU.hh"
542817Sksewell@umich.edu
552817Sksewell@umich.edutemplate <class Impl>
568852Sandreas.hansson@arm.comFSTranslatingPortProxy&
578706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy()
582817Sksewell@umich.edu{
598706Sandreas.hansson@arm.com    return thread->getVirtProxy();
602817Sksewell@umich.edu}
612817Sksewell@umich.edu
622817Sksewell@umich.edutemplate <class Impl>
632817Sksewell@umich.eduvoid
642817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile()
652817Sksewell@umich.edu{
663126Sktlim@umich.edu    thread->dumpFuncProfile();
672817Sksewell@umich.edu}
682817Sksewell@umich.edu
692817Sksewell@umich.edutemplate <class Impl>
702817Sksewell@umich.eduvoid
712817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
722817Sksewell@umich.edu{
739441SAndreas.Sandberg@ARM.com    ::takeOverFrom(*this, *old_context);
749478Snilay@cs.wisc.edu    TheISA::Decoder *newDecoder = getDecoderPtr();
759478Snilay@cs.wisc.edu    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
769478Snilay@cs.wisc.edu    newDecoder->takeOverFrom(oldDecoder);
772817Sksewell@umich.edu
789441SAndreas.Sandberg@ARM.com    thread->kernelStats = old_context->getKernelStats();
799441SAndreas.Sandberg@ARM.com    thread->funcExeInst = old_context->readFuncExeInst();
802817Sksewell@umich.edu
819382SAli.Saidi@ARM.com    thread->noSquashFromTC = false;
822817Sksewell@umich.edu    thread->trapPending = false;
832817Sksewell@umich.edu}
842817Sksewell@umich.edu
852817Sksewell@umich.edutemplate <class Impl>
862817Sksewell@umich.eduvoid
8710407Smitch.hayenga@arm.comO3ThreadContext<Impl>::activate()
882817Sksewell@umich.edu{
892875Sksewell@umich.edu    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
905715Shsul@eecs.umich.edu            threadId());
912817Sksewell@umich.edu
922817Sksewell@umich.edu    if (thread->status() == ThreadContext::Active)
932817Sksewell@umich.edu        return;
942817Sksewell@umich.edu
957823Ssteve.reinhardt@amd.com    thread->lastActivate = curTick();
962817Sksewell@umich.edu    thread->setStatus(ThreadContext::Active);
972817Sksewell@umich.edu
982817Sksewell@umich.edu    // status() == Suspended
9910407Smitch.hayenga@arm.com    cpu->activateContext(thread->threadId());
1002817Sksewell@umich.edu}
1012817Sksewell@umich.edu
1022817Sksewell@umich.edutemplate <class Impl>
1032817Sksewell@umich.eduvoid
10410407Smitch.hayenga@arm.comO3ThreadContext<Impl>::suspend()
1052817Sksewell@umich.edu{
1062875Sksewell@umich.edu    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
1075715Shsul@eecs.umich.edu            threadId());
1082817Sksewell@umich.edu
1092817Sksewell@umich.edu    if (thread->status() == ThreadContext::Suspended)
1102817Sksewell@umich.edu        return;
1112817Sksewell@umich.edu
11212279Snikos.nikoleris@arm.com    if (cpu->isDraining()) {
11312279Snikos.nikoleris@arm.com        DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
11412279Snikos.nikoleris@arm.com        return;
11512279Snikos.nikoleris@arm.com    }
11612279Snikos.nikoleris@arm.com
1177823Ssteve.reinhardt@amd.com    thread->lastActivate = curTick();
1187823Ssteve.reinhardt@amd.com    thread->lastSuspend = curTick();
1198793Sgblack@eecs.umich.edu
1202817Sksewell@umich.edu    thread->setStatus(ThreadContext::Suspended);
1215715Shsul@eecs.umich.edu    cpu->suspendContext(thread->threadId());
1222817Sksewell@umich.edu}
1232817Sksewell@umich.edu
1242817Sksewell@umich.edutemplate <class Impl>
1252817Sksewell@umich.eduvoid
12610407Smitch.hayenga@arm.comO3ThreadContext<Impl>::halt()
1272817Sksewell@umich.edu{
12810407Smitch.hayenga@arm.com    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
1292817Sksewell@umich.edu
1302817Sksewell@umich.edu    if (thread->status() == ThreadContext::Halted)
1312817Sksewell@umich.edu        return;
1322817Sksewell@umich.edu
1332817Sksewell@umich.edu    thread->setStatus(ThreadContext::Halted);
1345715Shsul@eecs.umich.edu    cpu->haltContext(thread->threadId());
1352817Sksewell@umich.edu}
1362817Sksewell@umich.edu
1372817Sksewell@umich.edutemplate <class Impl>
1382817Sksewell@umich.eduvoid
1392817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name)
1402817Sksewell@umich.edu{
1418793Sgblack@eecs.umich.edu    if (FullSystem) {
14212181Sgabeblack@google.com        thread->kernelStats = new TheISA::Kernel::Statistics();
1438793Sgblack@eecs.umich.edu        thread->kernelStats->regStats(name + ".kern");
1448793Sgblack@eecs.umich.edu    }
1452817Sksewell@umich.edu}
1462817Sksewell@umich.edu
1472817Sksewell@umich.edutemplate <class Impl>
1482817Sksewell@umich.eduTick
1492817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate()
1502817Sksewell@umich.edu{
1512817Sksewell@umich.edu    return thread->lastActivate;
1522817Sksewell@umich.edu}
1532817Sksewell@umich.edu
1542817Sksewell@umich.edutemplate <class Impl>
1552817Sksewell@umich.eduTick
1562817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend()
1572817Sksewell@umich.edu{
1582817Sksewell@umich.edu    return thread->lastSuspend;
1592817Sksewell@umich.edu}
1602817Sksewell@umich.edu
1612817Sksewell@umich.edutemplate <class Impl>
1622817Sksewell@umich.eduvoid
1632817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear()
1643126Sktlim@umich.edu{
1653126Sktlim@umich.edu    thread->profileClear();
1663126Sktlim@umich.edu}
1672817Sksewell@umich.edu
1682817Sksewell@umich.edutemplate <class Impl>
1692817Sksewell@umich.eduvoid
1702817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample()
1713126Sktlim@umich.edu{
1723126Sktlim@umich.edu    thread->profileSample();
1733126Sktlim@umich.edu}
1742817Sksewell@umich.edu
1752817Sksewell@umich.edutemplate <class Impl>
1762817Sksewell@umich.eduvoid
1772817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
1782817Sksewell@umich.edu{
1798208SAli.Saidi@ARM.com    // Prevent squashing
1809382SAli.Saidi@ARM.com    thread->noSquashFromTC = true;
1818208SAli.Saidi@ARM.com    TheISA::copyRegs(tc, this);
1829382SAli.Saidi@ARM.com    thread->noSquashFromTC = false;
1832817Sksewell@umich.edu
1848793Sgblack@eecs.umich.edu    if (!FullSystem)
1858793Sgblack@eecs.umich.edu        this->thread->funcExeInst = tc->readFuncExeInst();
1862817Sksewell@umich.edu}
1872817Sksewell@umich.edu
1882817Sksewell@umich.edutemplate <class Impl>
1892817Sksewell@umich.eduvoid
1902817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs()
1917763SAli.Saidi@ARM.com{
1929384SAndreas.Sandberg@arm.com    cpu->isa[thread->threadId()]->clear();
1937763SAli.Saidi@ARM.com}
1942817Sksewell@umich.edu
1952817Sksewell@umich.edutemplate <class Impl>
1962817Sksewell@umich.eduuint64_t
1979426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
1982817Sksewell@umich.edu{
1995715Shsul@eecs.umich.edu    return cpu->readArchIntReg(reg_idx, thread->threadId());
2002817Sksewell@umich.edu}
2012817Sksewell@umich.edu
2022817Sksewell@umich.edutemplate <class Impl>
2032986Sgblack@eecs.umich.eduTheISA::FloatReg
2049426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
2052817Sksewell@umich.edu{
2066314Sgblack@eecs.umich.edu    return cpu->readArchFloatReg(reg_idx, thread->threadId());
2072817Sksewell@umich.edu}
2082817Sksewell@umich.edu
2092817Sksewell@umich.edutemplate <class Impl>
2102986Sgblack@eecs.umich.eduTheISA::FloatRegBits
2119426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
2122817Sksewell@umich.edu{
2135715Shsul@eecs.umich.edu    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
2142817Sksewell@umich.edu}
2152817Sksewell@umich.edu
2162817Sksewell@umich.edutemplate <class Impl>
21712109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecRegContainer&
21812109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
21912109SRekai.GonzalezAlberquilla@arm.com{
22012109SRekai.GonzalezAlberquilla@arm.com    return cpu->readArchVecReg(reg_id, thread->threadId());
22112109SRekai.GonzalezAlberquilla@arm.com}
22212109SRekai.GonzalezAlberquilla@arm.com
22312109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl>
22412109SRekai.GonzalezAlberquilla@arm.comTheISA::VecRegContainer&
22512109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
22612109SRekai.GonzalezAlberquilla@arm.com{
22712109SRekai.GonzalezAlberquilla@arm.com    return cpu->getWritableArchVecReg(reg_id, thread->threadId());
22812109SRekai.GonzalezAlberquilla@arm.com}
22912109SRekai.GonzalezAlberquilla@arm.com
23012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl>
23112109SRekai.GonzalezAlberquilla@arm.comconst TheISA::VecElem&
23212109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
23312109SRekai.GonzalezAlberquilla@arm.com                                           const ElemIndex& elemIndex) const
23412109SRekai.GonzalezAlberquilla@arm.com{
23512109SRekai.GonzalezAlberquilla@arm.com    return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
23612109SRekai.GonzalezAlberquilla@arm.com}
23712109SRekai.GonzalezAlberquilla@arm.com
23812109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl>
2399920Syasuko.eckert@amd.comTheISA::CCReg
2409920Syasuko.eckert@amd.comO3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
2419920Syasuko.eckert@amd.com{
2429920Syasuko.eckert@amd.com    return cpu->readArchCCReg(reg_idx, thread->threadId());
2439920Syasuko.eckert@amd.com}
2449920Syasuko.eckert@amd.com
2459920Syasuko.eckert@amd.comtemplate <class Impl>
2462817Sksewell@umich.eduvoid
2479426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
2482817Sksewell@umich.edu{
2495715Shsul@eecs.umich.edu    cpu->setArchIntReg(reg_idx, val, thread->threadId());
2502817Sksewell@umich.edu
2519382SAli.Saidi@ARM.com    conditionalSquash();
2522817Sksewell@umich.edu}
2532817Sksewell@umich.edu
2542817Sksewell@umich.edutemplate <class Impl>
2552817Sksewell@umich.eduvoid
2569426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
2572817Sksewell@umich.edu{
2586314Sgblack@eecs.umich.edu    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
2592817Sksewell@umich.edu
2609382SAli.Saidi@ARM.com    conditionalSquash();
2612817Sksewell@umich.edu}
2622817Sksewell@umich.edu
2632817Sksewell@umich.edutemplate <class Impl>
2642817Sksewell@umich.eduvoid
2659426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
2662817Sksewell@umich.edu{
2675715Shsul@eecs.umich.edu    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
2682817Sksewell@umich.edu
2699382SAli.Saidi@ARM.com    conditionalSquash();
2702817Sksewell@umich.edu}
2712817Sksewell@umich.edu
2722817Sksewell@umich.edutemplate <class Impl>
2732817Sksewell@umich.eduvoid
27412109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
27512109SRekai.GonzalezAlberquilla@arm.com{
27612109SRekai.GonzalezAlberquilla@arm.com    cpu->setArchVecReg(reg_idx, val, thread->threadId());
27712109SRekai.GonzalezAlberquilla@arm.com
27812109SRekai.GonzalezAlberquilla@arm.com    conditionalSquash();
27912109SRekai.GonzalezAlberquilla@arm.com}
28012109SRekai.GonzalezAlberquilla@arm.com
28112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl>
28212109SRekai.GonzalezAlberquilla@arm.comvoid
28312109SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
28412109SRekai.GonzalezAlberquilla@arm.com        const ElemIndex& elemIndex, const VecElem& val)
28512109SRekai.GonzalezAlberquilla@arm.com{
28612109SRekai.GonzalezAlberquilla@arm.com    cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
28712109SRekai.GonzalezAlberquilla@arm.com    conditionalSquash();
28812109SRekai.GonzalezAlberquilla@arm.com}
28912109SRekai.GonzalezAlberquilla@arm.com
29012109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl>
29112109SRekai.GonzalezAlberquilla@arm.comvoid
2929920Syasuko.eckert@amd.comO3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
2939920Syasuko.eckert@amd.com{
2949920Syasuko.eckert@amd.com    cpu->setArchCCReg(reg_idx, val, thread->threadId());
2959920Syasuko.eckert@amd.com
2969920Syasuko.eckert@amd.com    conditionalSquash();
2979920Syasuko.eckert@amd.com}
2989920Syasuko.eckert@amd.com
2999920Syasuko.eckert@amd.comtemplate <class Impl>
3009920Syasuko.eckert@amd.comvoid
3017720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
3022817Sksewell@umich.edu{
3037720Sgblack@eecs.umich.edu    cpu->pcState(val, thread->threadId());
3045258Sksewell@umich.edu
3059382SAli.Saidi@ARM.com    conditionalSquash();
3065258Sksewell@umich.edu}
3075258Sksewell@umich.edu
3088733Sgeoffrey.blake@arm.comtemplate <class Impl>
3098733Sgeoffrey.blake@arm.comvoid
3108733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
3118733Sgeoffrey.blake@arm.com{
3128733Sgeoffrey.blake@arm.com    cpu->pcState(val, thread->threadId());
3138733Sgeoffrey.blake@arm.com
3149382SAli.Saidi@ARM.com    conditionalSquash();
3158733Sgeoffrey.blake@arm.com}
3168733Sgeoffrey.blake@arm.com
3175258Sksewell@umich.edutemplate <class Impl>
31812106SRekai.GonzalezAlberquilla@arm.comRegId
31912106SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
3206313Sgblack@eecs.umich.edu{
32112106SRekai.GonzalezAlberquilla@arm.com    return cpu->isa[thread->threadId()]->flattenRegId(regId);
32210033SAli.Saidi@ARM.com}
32310033SAli.Saidi@ARM.com
32410033SAli.Saidi@ARM.comtemplate <class Impl>
3255258Sksewell@umich.eduvoid
3264172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
3272817Sksewell@umich.edu{
3285715Shsul@eecs.umich.edu    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
3292817Sksewell@umich.edu
3309382SAli.Saidi@ARM.com    conditionalSquash();
3312817Sksewell@umich.edu}
3322817Sksewell@umich.edu
3339944Smatt.horsnell@ARM.com#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
3342817Sksewell@umich.edutemplate <class Impl>
3353468Sgblack@eecs.umich.eduvoid
3368518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
3372817Sksewell@umich.edu{
3385715Shsul@eecs.umich.edu    cpu->setMiscReg(misc_reg, val, thread->threadId());
3392817Sksewell@umich.edu
3409382SAli.Saidi@ARM.com    conditionalSquash();
3412817Sksewell@umich.edu}
3422817Sksewell@umich.edu
343