thread_context.hh revision 9428:029dfe6324d3 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_THREAD_CONTEXT_HH__
44#define __CPU_O3_THREAD_CONTEXT_HH__
45
46#include "config/the_isa.hh"
47#include "cpu/o3/isa_specific.hh"
48#include "cpu/thread_context.hh"
49
50class EndQuiesceEvent;
51namespace Kernel {
52    class Statistics;
53}
54
55/**
56 * Derived ThreadContext class for use with the O3CPU.  It
57 * provides the interface for any external objects to access a
58 * single thread's state and some general CPU state.  Any time
59 * external objects try to update state through this interface,
60 * the CPU will create an event to squash all in-flight
61 * instructions in order to ensure state is maintained correctly.
62 * It must be defined specifically for the O3CPU because
63 * not all architectural state is located within the O3ThreadState
64 * (such as the commit PC, and registers), and specific actions
65 * must be taken when using this interface (such as squashing all
66 * in-flight instructions when doing a write to this interface).
67 */
68template <class Impl>
69class O3ThreadContext : public ThreadContext
70{
71  public:
72    typedef typename Impl::O3CPU O3CPU;
73
74   /** Pointer to the CPU. */
75    O3CPU *cpu;
76
77    /** Pointer to the thread state that this TC corrseponds to. */
78    O3ThreadState<Impl> *thread;
79
80    /** Returns a pointer to the ITB. */
81    TheISA::TLB *getITBPtr() { return cpu->itb; }
82
83    /** Returns a pointer to the DTB. */
84    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
85
86    CheckerCPU *getCheckerCpuPtr() { return NULL; }
87
88    TheISA::Decoder *
89    getDecoderPtr()
90    {
91        return cpu->fetch.decoder[thread->threadId()];
92    }
93
94    /** Returns a pointer to this CPU. */
95    virtual BaseCPU *getCpuPtr() { return cpu; }
96
97    /** Reads this CPU's ID. */
98    virtual int cpuId() { return cpu->cpuId(); }
99
100    virtual int contextId() { return thread->contextId(); }
101
102    virtual void setContextId(int id) { thread->setContextId(id); }
103
104    /** Returns this thread's ID number. */
105    virtual int threadId() { return thread->threadId(); }
106    virtual void setThreadId(int id) { return thread->setThreadId(id); }
107
108    /** Returns a pointer to the system. */
109    virtual System *getSystemPtr() { return cpu->system; }
110
111    /** Returns a pointer to this thread's kernel statistics. */
112    virtual TheISA::Kernel::Statistics *getKernelStats()
113    { return thread->kernelStats; }
114
115    /** Returns a pointer to this thread's process. */
116    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
117
118    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
119
120    virtual FSTranslatingPortProxy &getVirtProxy();
121
122    virtual void initMemProxies(ThreadContext *tc)
123    { thread->initMemProxies(tc); }
124
125    virtual SETranslatingPortProxy &getMemProxy()
126    { return thread->getMemProxy(); }
127
128    /** Returns this thread's status. */
129    virtual Status status() const { return thread->status(); }
130
131    /** Sets this thread's status. */
132    virtual void setStatus(Status new_status)
133    { thread->setStatus(new_status); }
134
135    /** Set the status to Active.  Optional delay indicates number of
136     * cycles to wait before beginning execution. */
137    virtual void activate(Cycles delay = Cycles(1));
138
139    /** Set the status to Suspended. */
140    virtual void suspend(Cycles delay = Cycles(0));
141
142    /** Set the status to Halted. */
143    virtual void halt(Cycles delay = Cycles(0));
144
145    /** Dumps the function profiling information.
146     * @todo: Implement.
147     */
148    virtual void dumpFuncProfile();
149
150    /** Takes over execution of a thread from another CPU. */
151    virtual void takeOverFrom(ThreadContext *old_context);
152
153    /** Registers statistics associated with this TC. */
154    virtual void regStats(const std::string &name);
155
156    /** Reads the last tick that this thread was activated on. */
157    virtual Tick readLastActivate();
158    /** Reads the last tick that this thread was suspended on. */
159    virtual Tick readLastSuspend();
160
161    /** Clears the function profiling information. */
162    virtual void profileClear();
163    /** Samples the function profiling information. */
164    virtual void profileSample();
165
166    /** Copies the architectural registers from another TC into this TC. */
167    virtual void copyArchRegs(ThreadContext *tc);
168
169    /** Resets all architectural registers to 0. */
170    virtual void clearArchRegs();
171
172    /** Reads an integer register. */
173    virtual uint64_t readIntReg(int reg_idx) {
174        return readIntRegFlat(flattenIntIndex(reg_idx));
175    }
176
177    virtual FloatReg readFloatReg(int reg_idx) {
178        return readFloatRegFlat(flattenFloatIndex(reg_idx));
179    }
180
181    virtual FloatRegBits readFloatRegBits(int reg_idx) {
182        return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
183    }
184
185    /** Sets an integer register to a value. */
186    virtual void setIntReg(int reg_idx, uint64_t val) {
187        setIntRegFlat(flattenIntIndex(reg_idx), val);
188    }
189
190    virtual void setFloatReg(int reg_idx, FloatReg val) {
191        setFloatRegFlat(flattenFloatIndex(reg_idx), val);
192    }
193
194    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
195        setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
196    }
197
198    /** Reads this thread's PC state. */
199    virtual TheISA::PCState pcState()
200    { return cpu->pcState(thread->threadId()); }
201
202    /** Sets this thread's PC state. */
203    virtual void pcState(const TheISA::PCState &val);
204
205    virtual void pcStateNoRecord(const TheISA::PCState &val);
206
207    /** Reads this thread's PC. */
208    virtual Addr instAddr()
209    { return cpu->instAddr(thread->threadId()); }
210
211    /** Reads this thread's next PC. */
212    virtual Addr nextInstAddr()
213    { return cpu->nextInstAddr(thread->threadId()); }
214
215    /** Reads this thread's next PC. */
216    virtual MicroPC microPC()
217    { return cpu->microPC(thread->threadId()); }
218
219    /** Reads a miscellaneous register. */
220    virtual MiscReg readMiscRegNoEffect(int misc_reg)
221    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
222
223    /** Reads a misc. register, including any side-effects the
224     * read might have as defined by the architecture. */
225    virtual MiscReg readMiscReg(int misc_reg)
226    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
227
228    /** Sets a misc. register. */
229    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
230
231    /** Sets a misc. register, including any side-effects the
232     * write might have as defined by the architecture. */
233    virtual void setMiscReg(int misc_reg, const MiscReg &val);
234
235    virtual int flattenIntIndex(int reg);
236    virtual int flattenFloatIndex(int reg);
237
238    /** Returns the number of consecutive store conditional failures. */
239    // @todo: Figure out where these store cond failures should go.
240    virtual unsigned readStCondFailures()
241    { return thread->storeCondFailures; }
242
243    /** Sets the number of consecutive store conditional failures. */
244    virtual void setStCondFailures(unsigned sc_failures)
245    { thread->storeCondFailures = sc_failures; }
246
247    // Only really makes sense for old CPU model.  Lots of code
248    // outside the CPU still checks this function, so it will
249    // always return false to keep everything working.
250    /** Checks if the thread is misspeculating.  Because it is
251     * very difficult to determine if the thread is
252     * misspeculating, this is set as false. */
253    virtual bool misspeculating() { return false; }
254
255    /** Executes a syscall in SE mode. */
256    virtual void syscall(int64_t callnum)
257    { return cpu->syscall(callnum, thread->threadId()); }
258
259    /** Reads the funcExeInst counter. */
260    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
261
262    /** Returns pointer to the quiesce event. */
263    virtual EndQuiesceEvent *getQuiesceEvent()
264    {
265        return this->thread->quiesceEvent;
266    }
267    /** check if the cpu is currently in state update mode and squash if not.
268     * This function will return true if a trap is pending or if a fault or
269     * similar is currently writing to the thread context and doesn't want
270     * reset all the state (see noSquashFromTC).
271     */
272    inline void conditionalSquash()
273    {
274        if (!thread->trapPending && !thread->noSquashFromTC)
275            cpu->squashFromTC(thread->threadId());
276    }
277
278    virtual uint64_t readIntRegFlat(int idx);
279    virtual void setIntRegFlat(int idx, uint64_t val);
280
281    virtual FloatReg readFloatRegFlat(int idx);
282    virtual void setFloatRegFlat(int idx, FloatReg val);
283
284    virtual FloatRegBits readFloatRegBitsFlat(int idx);
285    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
286};
287
288#endif
289