thread_context.hh revision 8808:8af87554ad7e 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "config/the_isa.hh"
35#include "cpu/o3/isa_specific.hh"
36#include "cpu/thread_context.hh"
37
38class EndQuiesceEvent;
39namespace Kernel {
40    class Statistics;
41};
42
43/**
44 * Derived ThreadContext class for use with the O3CPU.  It
45 * provides the interface for any external objects to access a
46 * single thread's state and some general CPU state.  Any time
47 * external objects try to update state through this interface,
48 * the CPU will create an event to squash all in-flight
49 * instructions in order to ensure state is maintained correctly.
50 * It must be defined specifically for the O3CPU because
51 * not all architectural state is located within the O3ThreadState
52 * (such as the commit PC, and registers), and specific actions
53 * must be taken when using this interface (such as squashing all
54 * in-flight instructions when doing a write to this interface).
55 */
56template <class Impl>
57class O3ThreadContext : public ThreadContext
58{
59  public:
60    typedef typename Impl::O3CPU O3CPU;
61
62   /** Pointer to the CPU. */
63    O3CPU *cpu;
64
65    /** Pointer to the thread state that this TC corrseponds to. */
66    O3ThreadState<Impl> *thread;
67
68    /** Returns a pointer to the ITB. */
69    TheISA::TLB *getITBPtr() { return cpu->itb; }
70
71    /** Returns a pointer to the DTB. */
72    TheISA::TLB *getDTBPtr() { return cpu->dtb; }
73
74    Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
75
76    /** Returns a pointer to this CPU. */
77    virtual BaseCPU *getCpuPtr() { return cpu; }
78
79    /** Reads this CPU's ID. */
80    virtual int cpuId() { return cpu->cpuId(); }
81
82    virtual int contextId() { return thread->contextId(); }
83
84    virtual void setContextId(int id) { thread->setContextId(id); }
85
86    /** Returns this thread's ID number. */
87    virtual int threadId() { return thread->threadId(); }
88    virtual void setThreadId(int id) { return thread->setThreadId(id); }
89
90    /** Returns a pointer to the system. */
91    virtual System *getSystemPtr() { return cpu->system; }
92
93    /** Returns a pointer to this thread's kernel statistics. */
94    virtual TheISA::Kernel::Statistics *getKernelStats()
95    { return thread->kernelStats; }
96
97    /** Returns a pointer to this thread's process. */
98    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
99
100    virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
101
102    virtual FSTranslatingPortProxy* getVirtProxy();
103
104    virtual void initMemProxies(ThreadContext *tc)
105    { thread->initMemProxies(tc); }
106
107    virtual SETranslatingPortProxy* getMemProxy()
108    { return thread->getMemProxy(); }
109
110    /** Returns this thread's status. */
111    virtual Status status() const { return thread->status(); }
112
113    /** Sets this thread's status. */
114    virtual void setStatus(Status new_status)
115    { thread->setStatus(new_status); }
116
117    /** Set the status to Active.  Optional delay indicates number of
118     * cycles to wait before beginning execution. */
119    virtual void activate(int delay = 1);
120
121    /** Set the status to Suspended. */
122    virtual void suspend(int delay = 0);
123
124    /** Set the status to Halted. */
125    virtual void halt(int delay = 0);
126
127    /** Dumps the function profiling information.
128     * @todo: Implement.
129     */
130    virtual void dumpFuncProfile();
131
132    /** Takes over execution of a thread from another CPU. */
133    virtual void takeOverFrom(ThreadContext *old_context);
134
135    /** Registers statistics associated with this TC. */
136    virtual void regStats(const std::string &name);
137
138    /** Serializes state. */
139    virtual void serialize(std::ostream &os);
140    /** Unserializes state. */
141    virtual void unserialize(Checkpoint *cp, const std::string &section);
142
143    /** Reads the last tick that this thread was activated on. */
144    virtual Tick readLastActivate();
145    /** Reads the last tick that this thread was suspended on. */
146    virtual Tick readLastSuspend();
147
148    /** Clears the function profiling information. */
149    virtual void profileClear();
150    /** Samples the function profiling information. */
151    virtual void profileSample();
152
153    /** Copies the architectural registers from another TC into this TC. */
154    virtual void copyArchRegs(ThreadContext *tc);
155
156    /** Resets all architectural registers to 0. */
157    virtual void clearArchRegs();
158
159    /** Reads an integer register. */
160    virtual uint64_t readIntReg(int reg_idx);
161
162    virtual FloatReg readFloatReg(int reg_idx);
163
164    virtual FloatRegBits readFloatRegBits(int reg_idx);
165
166    /** Sets an integer register to a value. */
167    virtual void setIntReg(int reg_idx, uint64_t val);
168
169    virtual void setFloatReg(int reg_idx, FloatReg val);
170
171    virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
172
173    /** Reads this thread's PC state. */
174    virtual TheISA::PCState pcState()
175    { return cpu->pcState(thread->threadId()); }
176
177    /** Sets this thread's PC state. */
178    virtual void pcState(const TheISA::PCState &val);
179
180    /** Reads this thread's PC. */
181    virtual Addr instAddr()
182    { return cpu->instAddr(thread->threadId()); }
183
184    /** Reads this thread's next PC. */
185    virtual Addr nextInstAddr()
186    { return cpu->nextInstAddr(thread->threadId()); }
187
188    /** Reads this thread's next PC. */
189    virtual MicroPC microPC()
190    { return cpu->microPC(thread->threadId()); }
191
192    /** Reads a miscellaneous register. */
193    virtual MiscReg readMiscRegNoEffect(int misc_reg)
194    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
195
196    /** Reads a misc. register, including any side-effects the
197     * read might have as defined by the architecture. */
198    virtual MiscReg readMiscReg(int misc_reg)
199    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
200
201    /** Sets a misc. register. */
202    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
203
204    /** Sets a misc. register, including any side-effects the
205     * write might have as defined by the architecture. */
206    virtual void setMiscReg(int misc_reg, const MiscReg &val);
207
208    virtual int flattenIntIndex(int reg);
209    virtual int flattenFloatIndex(int reg);
210
211    /** Returns the number of consecutive store conditional failures. */
212    // @todo: Figure out where these store cond failures should go.
213    virtual unsigned readStCondFailures()
214    { return thread->storeCondFailures; }
215
216    /** Sets the number of consecutive store conditional failures. */
217    virtual void setStCondFailures(unsigned sc_failures)
218    { thread->storeCondFailures = sc_failures; }
219
220    // Only really makes sense for old CPU model.  Lots of code
221    // outside the CPU still checks this function, so it will
222    // always return false to keep everything working.
223    /** Checks if the thread is misspeculating.  Because it is
224     * very difficult to determine if the thread is
225     * misspeculating, this is set as false. */
226    virtual bool misspeculating() { return false; }
227
228    /** Executes a syscall in SE mode. */
229    virtual void syscall(int64_t callnum)
230    { return cpu->syscall(callnum, thread->threadId()); }
231
232    /** Reads the funcExeInst counter. */
233    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
234
235    /** Returns pointer to the quiesce event. */
236    virtual EndQuiesceEvent *getQuiesceEvent()
237    {
238        return this->thread->quiesceEvent;
239    }
240
241};
242
243#endif
244