thread_context.hh revision 5714:76abee886def
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 32#define __CPU_O3_THREAD_CONTEXT_HH__ 33 34#include "cpu/thread_context.hh" 35#include "cpu/o3/isa_specific.hh" 36 37class EndQuiesceEvent; 38namespace Kernel { 39 class Statistics; 40}; 41 42class TranslatingPort; 43 44/** 45 * Derived ThreadContext class for use with the O3CPU. It 46 * provides the interface for any external objects to access a 47 * single thread's state and some general CPU state. Any time 48 * external objects try to update state through this interface, 49 * the CPU will create an event to squash all in-flight 50 * instructions in order to ensure state is maintained correctly. 51 * It must be defined specifically for the O3CPU because 52 * not all architectural state is located within the O3ThreadState 53 * (such as the commit PC, and registers), and specific actions 54 * must be taken when using this interface (such as squashing all 55 * in-flight instructions when doing a write to this interface). 56 */ 57template <class Impl> 58class O3ThreadContext : public ThreadContext 59{ 60 public: 61 typedef typename Impl::O3CPU O3CPU; 62 63 /** Pointer to the CPU. */ 64 O3CPU *cpu; 65 66 /** Pointer to the thread state that this TC corrseponds to. */ 67 O3ThreadState<Impl> *thread; 68 69 /** Returns a pointer to the ITB. */ 70 TheISA::ITB *getITBPtr() { return cpu->itb; } 71 72 /** Returns a pointer to the DTB. */ 73 TheISA::DTB *getDTBPtr() { return cpu->dtb; } 74 75 /** Returns a pointer to this CPU. */ 76 virtual BaseCPU *getCpuPtr() { return cpu; } 77 78 /** Reads this CPU's ID. */ 79 virtual int cpuId() { return cpu->cpuId(); } 80 81 virtual int contextId() { return thread->contextId(); } 82 83 virtual void setContextId(int id) { thread->setContextId(id); } 84 85#if FULL_SYSTEM 86 /** Returns a pointer to the system. */ 87 virtual System *getSystemPtr() { return cpu->system; } 88 89 /** Returns a pointer to physical memory. */ 90 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 91 92 /** Returns a pointer to this thread's kernel statistics. */ 93 virtual TheISA::Kernel::Statistics *getKernelStats() 94 { return thread->kernelStats; } 95 96 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 97 98 virtual VirtualPort *getVirtPort(); 99 100 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } 101#else 102 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 103 104 /** Returns a pointer to this thread's process. */ 105 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 106#endif 107 /** Returns this thread's status. */ 108 virtual Status status() const { return thread->status(); } 109 110 /** Sets this thread's status. */ 111 virtual void setStatus(Status new_status) 112 { thread->setStatus(new_status); } 113 114 /** Set the status to Active. Optional delay indicates number of 115 * cycles to wait before beginning execution. */ 116 virtual void activate(int delay = 1); 117 118 /** Set the status to Suspended. */ 119 virtual void suspend(int delay = 0); 120 121 /** Set the status to Unallocated. */ 122 virtual void deallocate(int delay = 0); 123 124 /** Set the status to Halted. */ 125 virtual void halt(int delay = 0); 126 127#if FULL_SYSTEM 128 /** Dumps the function profiling information. 129 * @todo: Implement. 130 */ 131 virtual void dumpFuncProfile(); 132#endif 133 /** Takes over execution of a thread from another CPU. */ 134 virtual void takeOverFrom(ThreadContext *old_context); 135 136 /** Registers statistics associated with this TC. */ 137 virtual void regStats(const std::string &name); 138 139 /** Serializes state. */ 140 virtual void serialize(std::ostream &os); 141 /** Unserializes state. */ 142 virtual void unserialize(Checkpoint *cp, const std::string §ion); 143 144#if FULL_SYSTEM 145 /** Reads the last tick that this thread was activated on. */ 146 virtual Tick readLastActivate(); 147 /** Reads the last tick that this thread was suspended on. */ 148 virtual Tick readLastSuspend(); 149 150 /** Clears the function profiling information. */ 151 virtual void profileClear(); 152 /** Samples the function profiling information. */ 153 virtual void profileSample(); 154#endif 155 /** Returns this thread's ID number. */ 156 virtual int getThreadNum() { return thread->readTid(); } 157 158 /** Returns the instruction this thread is currently committing. 159 * Only used when an instruction faults. 160 */ 161 virtual TheISA::MachInst getInst(); 162 163 /** Copies the architectural registers from another TC into this TC. */ 164 virtual void copyArchRegs(ThreadContext *tc); 165 166 /** Resets all architectural registers to 0. */ 167 virtual void clearArchRegs(); 168 169 /** Reads an integer register. */ 170 virtual uint64_t readIntReg(int reg_idx); 171 172 virtual FloatReg readFloatReg(int reg_idx, int width); 173 174 virtual FloatReg readFloatReg(int reg_idx); 175 176 virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 177 178 virtual FloatRegBits readFloatRegBits(int reg_idx); 179 180 /** Sets an integer register to a value. */ 181 virtual void setIntReg(int reg_idx, uint64_t val); 182 183 virtual void setFloatReg(int reg_idx, FloatReg val, int width); 184 185 virtual void setFloatReg(int reg_idx, FloatReg val); 186 187 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 188 189 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 190 191 /** Reads this thread's PC. */ 192 virtual uint64_t readPC() 193 { return cpu->readPC(thread->readTid()); } 194 195 /** Sets this thread's PC. */ 196 virtual void setPC(uint64_t val); 197 198 /** Reads this thread's next PC. */ 199 virtual uint64_t readNextPC() 200 { return cpu->readNextPC(thread->readTid()); } 201 202 /** Sets this thread's next PC. */ 203 virtual void setNextPC(uint64_t val); 204 205 virtual uint64_t readMicroPC() 206 { return cpu->readMicroPC(thread->readTid()); } 207 208 virtual void setMicroPC(uint64_t val); 209 210 virtual uint64_t readNextMicroPC() 211 { return cpu->readNextMicroPC(thread->readTid()); } 212 213 virtual void setNextMicroPC(uint64_t val); 214 215 /** Reads a miscellaneous register. */ 216 virtual MiscReg readMiscRegNoEffect(int misc_reg) 217 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } 218 219 /** Reads a misc. register, including any side-effects the 220 * read might have as defined by the architecture. */ 221 virtual MiscReg readMiscReg(int misc_reg) 222 { return cpu->readMiscReg(misc_reg, thread->readTid()); } 223 224 /** Sets a misc. register. */ 225 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 226 227 /** Sets a misc. register, including any side-effects the 228 * write might have as defined by the architecture. */ 229 virtual void setMiscReg(int misc_reg, const MiscReg &val); 230 231 /** Returns the number of consecutive store conditional failures. */ 232 // @todo: Figure out where these store cond failures should go. 233 virtual unsigned readStCondFailures() 234 { return thread->storeCondFailures; } 235 236 /** Sets the number of consecutive store conditional failures. */ 237 virtual void setStCondFailures(unsigned sc_failures) 238 { thread->storeCondFailures = sc_failures; } 239 240 // Only really makes sense for old CPU model. Lots of code 241 // outside the CPU still checks this function, so it will 242 // always return false to keep everything working. 243 /** Checks if the thread is misspeculating. Because it is 244 * very difficult to determine if the thread is 245 * misspeculating, this is set as false. */ 246 virtual bool misspeculating() { return false; } 247 248#if !FULL_SYSTEM 249 /** Gets a syscall argument by index. */ 250 virtual IntReg getSyscallArg(int i); 251 252 /** Sets a syscall argument. */ 253 virtual void setSyscallArg(int i, IntReg val); 254 255 /** Sets the syscall return value. */ 256 virtual void setSyscallReturn(SyscallReturn return_value); 257 258 /** Executes a syscall in SE mode. */ 259 virtual void syscall(int64_t callnum) 260 { return cpu->syscall(callnum, thread->readTid()); } 261 262 /** Reads the funcExeInst counter. */ 263 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 264#else 265 /** Returns pointer to the quiesce event. */ 266 virtual EndQuiesceEvent *getQuiesceEvent() 267 { 268 return this->thread->quiesceEvent; 269 } 270#endif 271 272 virtual uint64_t readNextNPC() 273 { 274 return this->cpu->readNextNPC(this->thread->readTid()); 275 } 276 277 virtual void setNextNPC(uint64_t val) 278 { 279#if THE_ISA == ALPHA_ISA 280 panic("Not supported on Alpha!"); 281#endif 282 this->cpu->setNextNPC(val, this->thread->readTid()); 283 } 284 285 /** This function exits the thread context in the CPU and returns 286 * 1 if the CPU has no more active threads (meaning it's OK to exit); 287 * Used in syscall-emulation mode when a thread executes the 'exit' 288 * syscall. 289 */ 290 virtual int exit() 291 { 292 this->deallocate(); 293 294 // If there are still threads executing in the system 295 if (this->cpu->numActiveThreads()) 296 return 0; // don't exit simulation 297 else 298 return 1; // exit simulation 299 } 300}; 301 302#endif 303