thread_context.hh revision 2817:273f7fb94f83
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 33#define __CPU_O3_THREAD_CONTEXT_HH__ 34 35#include "cpu/o3/isa_specific.hh" 36 37/** 38 * Derived ThreadContext class for use with the O3CPU. It 39 * provides the interface for any external objects to access a 40 * single thread's state and some general CPU state. Any time 41 * external objects try to update state through this interface, 42 * the CPU will create an event to squash all in-flight 43 * instructions in order to ensure state is maintained correctly. 44 * It must be defined specifically for the O3CPU because 45 * not all architectural state is located within the O3ThreadState 46 * (such as the commit PC, and registers), and specific actions 47 * must be taken when using this interface (such as squashing all 48 * in-flight instructions when doing a write to this interface). 49 */ 50template <class Impl> 51class O3ThreadContext : public ThreadContext 52{ 53 public: 54 typedef typename Impl::O3CPU O3CPU; 55 56 /** Pointer to the CPU. */ 57 O3CPU *cpu; 58 59 /** Pointer to the thread state that this TC corrseponds to. */ 60 O3ThreadState<Impl> *thread; 61 62 /** Returns a pointer to this CPU. */ 63 virtual BaseCPU *getCpuPtr() { return cpu; } 64 65 /** Sets this CPU's ID. */ 66 virtual void setCpuId(int id) { cpu->setCpuId(id); } 67 68 /** Reads this CPU's ID. */ 69 virtual int readCpuId() { return cpu->readCpuId(); } 70 71#if FULL_SYSTEM 72 /** Returns a pointer to the system. */ 73 virtual System *getSystemPtr() { return cpu->system; } 74 75 /** Returns a pointer to physical memory. */ 76 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 77 78 /** Returns a pointer to this thread's kernel statistics. */ 79 virtual Kernel::Statistics *getKernelStats() 80 { return thread->kernelStats; } 81 82 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 83 84 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL); 85 86 void delVirtPort(VirtualPort *vp); 87#else 88 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 89 90 /** Returns a pointer to this thread's process. */ 91 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 92#endif 93 /** Returns this thread's status. */ 94 virtual Status status() const { return thread->status(); } 95 96 /** Sets this thread's status. */ 97 virtual void setStatus(Status new_status) 98 { thread->setStatus(new_status); } 99 100 /** Set the status to Active. Optional delay indicates number of 101 * cycles to wait before beginning execution. */ 102 virtual void activate(int delay = 1); 103 104 /** Set the status to Suspended. */ 105 virtual void suspend(); 106 107 /** Set the status to Unallocated. */ 108 virtual void deallocate(); 109 110 /** Set the status to Halted. */ 111 virtual void halt(); 112 113#if FULL_SYSTEM 114 /** Dumps the function profiling information. 115 * @todo: Implement. 116 */ 117 virtual void dumpFuncProfile(); 118#endif 119 /** Takes over execution of a thread from another CPU. */ 120 virtual void takeOverFrom(ThreadContext *old_context); 121 122 /** Registers statistics associated with this TC. */ 123 virtual void regStats(const std::string &name); 124 125 /** Serializes state. */ 126 virtual void serialize(std::ostream &os); 127 /** Unserializes state. */ 128 virtual void unserialize(Checkpoint *cp, const std::string §ion); 129 130#if FULL_SYSTEM 131 /** Reads the last tick that this thread was activated on. */ 132 virtual Tick readLastActivate(); 133 /** Reads the last tick that this thread was suspended on. */ 134 virtual Tick readLastSuspend(); 135 136 /** Clears the function profiling information. */ 137 virtual void profileClear(); 138 /** Samples the function profiling information. */ 139 virtual void profileSample(); 140#endif 141 /** Returns this thread's ID number. */ 142 virtual int getThreadNum() { return thread->readTid(); } 143 144 /** Returns the instruction this thread is currently committing. 145 * Only used when an instruction faults. 146 */ 147 virtual TheISA::MachInst getInst(); 148 149 /** Copies the architectural registers from another TC into this TC. */ 150 virtual void copyArchRegs(ThreadContext *tc); 151 152 /** Resets all architectural registers to 0. */ 153 virtual void clearArchRegs(); 154 155 /** Reads an integer register. */ 156 virtual uint64_t readIntReg(int reg_idx); 157 158 virtual FloatReg readFloatReg(int reg_idx, int width); 159 160 virtual FloatReg readFloatReg(int reg_idx); 161 162 virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 163 164 virtual FloatRegBits readFloatRegBits(int reg_idx); 165 166 /** Sets an integer register to a value. */ 167 virtual void setIntReg(int reg_idx, uint64_t val); 168 169 virtual void setFloatReg(int reg_idx, FloatReg val, int width); 170 171 virtual void setFloatReg(int reg_idx, FloatReg val); 172 173 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 174 175 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 176 177 /** Reads this thread's PC. */ 178 virtual uint64_t readPC() 179 { return cpu->readPC(thread->readTid()); } 180 181 /** Sets this thread's PC. */ 182 virtual void setPC(uint64_t val); 183 184 /** Reads this thread's next PC. */ 185 virtual uint64_t readNextPC() 186 { return cpu->readNextPC(thread->readTid()); } 187 188 /** Sets this thread's next PC. */ 189 virtual void setNextPC(uint64_t val); 190 191 /** Reads a miscellaneous register. */ 192 virtual MiscReg readMiscReg(int misc_reg) 193 { return cpu->readMiscReg(misc_reg, thread->readTid()); } 194 195 /** Reads a misc. register, including any side-effects the 196 * read might have as defined by the architecture. */ 197 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 198 { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } 199 200 /** Sets a misc. register. */ 201 virtual Fault setMiscReg(int misc_reg, const MiscReg &val); 202 203 /** Sets a misc. register, including any side-effects the 204 * write might have as defined by the architecture. */ 205 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); 206 207 /** Returns the number of consecutive store conditional failures. */ 208 // @todo: Figure out where these store cond failures should go. 209 virtual unsigned readStCondFailures() 210 { return thread->storeCondFailures; } 211 212 /** Sets the number of consecutive store conditional failures. */ 213 virtual void setStCondFailures(unsigned sc_failures) 214 { thread->storeCondFailures = sc_failures; } 215 216 // Only really makes sense for old CPU model. Lots of code 217 // outside the CPU still checks this function, so it will 218 // always return false to keep everything working. 219 /** Checks if the thread is misspeculating. Because it is 220 * very difficult to determine if the thread is 221 * misspeculating, this is set as false. */ 222 virtual bool misspeculating() { return false; } 223 224#if !FULL_SYSTEM 225 /** Gets a syscall argument by index. */ 226 virtual IntReg getSyscallArg(int i); 227 228 /** Sets a syscall argument. */ 229 virtual void setSyscallArg(int i, IntReg val); 230 231 /** Sets the syscall return value. */ 232 virtual void setSyscallReturn(SyscallReturn return_value); 233 234 /** Executes a syscall in SE mode. */ 235 virtual void syscall(int64_t callnum) 236 { return cpu->syscall(callnum, thread->readTid()); } 237 238 /** Reads the funcExeInst counter. */ 239 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 240#endif 241}; 242 243#endif 244