thread_context.hh revision 13905:5cf30883255c
12SN/A/* 21762SN/A * Copyright (c) 2011-2012, 2016-2018 ARM Limited 32SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42SN/A * All rights reserved 52SN/A * 62SN/A * The license below extends only to copyright in the software and shall 72SN/A * not be construed as granting a license to any other intellectual 82SN/A * property including but not limited to intellectual property relating 92SN/A * to a hardware implementation of the functionality of the software 102SN/A * licensed hereunder. You may use the software subject to the license 112SN/A * terms below provided that you ensure that this notice is replicated 122SN/A * unmodified and in its entirety in all distributions of the software, 132SN/A * modified or unmodified, in source code or in binary form. 142SN/A * 152SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32456SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37148SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3856SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395889Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40441SN/A * 4156SN/A * Authors: Kevin Lim 4256SN/A */ 4356SN/A 44441SN/A#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 45433SN/A#define __CPU_O3_THREAD_CONTEXT_HH__ 462SN/A 472SN/A#include "config/the_isa.hh" 482SN/A#include "cpu/o3/isa_specific.hh" 49729SN/A#include "cpu/thread_context.hh" 50388SN/A 515887Snate@binkert.orgclass EndQuiesceEvent; 525887Snate@binkert.orgnamespace Kernel { 535887Snate@binkert.org class Statistics; 545887Snate@binkert.org} 555887Snate@binkert.org 56388SN/A/** 575887Snate@binkert.org * Derived ThreadContext class for use with the O3CPU. It 585887Snate@binkert.org * provides the interface for any external objects to access a 59388SN/A * single thread's state and some general CPU state. Any time 60388SN/A * external objects try to update state through this interface, 615887Snate@binkert.org * the CPU will create an event to squash all in-flight 625887Snate@binkert.org * instructions in order to ensure state is maintained correctly. 63441SN/A * It must be defined specifically for the O3CPU because 645887Snate@binkert.org * not all architectural state is located within the O3ThreadState 655887Snate@binkert.org * (such as the commit PC, and registers), and specific actions 66441SN/A * must be taken when using this interface (such as squashing all 67441SN/A * in-flight instructions when doing a write to this interface). 68388SN/A */ 695886Snate@binkert.orgtemplate <class Impl> 70388SN/Aclass O3ThreadContext : public ThreadContext 715887Snate@binkert.org{ 725887Snate@binkert.org public: 735887Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 745887Snate@binkert.org 755887Snate@binkert.org /** Pointer to the CPU. */ 765887Snate@binkert.org O3CPU *cpu; 775887Snate@binkert.org 785887Snate@binkert.org /** Pointer to the thread state that this TC corrseponds to. */ 795887Snate@binkert.org O3ThreadState<Impl> *thread; 805887Snate@binkert.org 815887Snate@binkert.org /** Returns a pointer to the ITB. */ 82388SN/A BaseTLB *getITBPtr() override { return cpu->itb; } 83388SN/A 84388SN/A /** Returns a pointer to the DTB. */ 855889Snate@binkert.org BaseTLB *getDTBPtr() override { return cpu->dtb; } 865889Snate@binkert.org 875889Snate@binkert.org CheckerCPU *getCheckerCpuPtr() override { return NULL; } 885889Snate@binkert.org 895889Snate@binkert.org TheISA::ISA * 905889Snate@binkert.org getIsaPtr() override 915886Snate@binkert.org { 92388SN/A return cpu->isa[thread->threadId()]; 935886Snate@binkert.org } 94388SN/A 95388SN/A TheISA::Decoder * 965886Snate@binkert.org getDecoderPtr() override 975886Snate@binkert.org { 98388SN/A return cpu->fetch.decoder[thread->threadId()]; 995887Snate@binkert.org } 1005887Snate@binkert.org 1015887Snate@binkert.org /** Returns a pointer to this CPU. */ 102388SN/A BaseCPU *getCpuPtr() override { return cpu; } 103388SN/A 1045886Snate@binkert.org /** Reads this CPU's ID. */ 1055886Snate@binkert.org int cpuId() const override { return cpu->cpuId(); } 1065886Snate@binkert.org 1075887Snate@binkert.org /** Reads this CPU's Socket ID. */ 1085887Snate@binkert.org uint32_t socketId() const override { return cpu->socketId(); } 1095887Snate@binkert.org 1105886Snate@binkert.org ContextID contextId() const override { return thread->contextId(); } 1115886Snate@binkert.org 1125889Snate@binkert.org void setContextId(ContextID id) override { thread->setContextId(id); } 1135889Snate@binkert.org 1145889Snate@binkert.org /** Returns this thread's ID number. */ 1155889Snate@binkert.org int threadId() const override { return thread->threadId(); } 1166026Snate@binkert.org void setThreadId(int id) override { return thread->setThreadId(id); } 1176026Snate@binkert.org 1186026Snate@binkert.org /** Returns a pointer to the system. */ 1196026Snate@binkert.org System *getSystemPtr() override { return cpu->system; } 1206026Snate@binkert.org 1216026Snate@binkert.org /** Returns a pointer to this thread's kernel statistics. */ 1226026Snate@binkert.org ::Kernel::Statistics * 1236026Snate@binkert.org getKernelStats() override 1245889Snate@binkert.org { 1255889Snate@binkert.org return thread->kernelStats; 1265889Snate@binkert.org } 1275889Snate@binkert.org 1285886Snate@binkert.org /** Returns a pointer to this thread's process. */ 1295889Snate@binkert.org Process *getProcessPtr() override { return thread->getProcessPtr(); } 130582SN/A 1315889Snate@binkert.org void setProcessPtr(Process *p) override { thread->setProcessPtr(p); } 1325889Snate@binkert.org 1335889Snate@binkert.org PortProxy &getPhysProxy() override { return thread->getPhysProxy(); } 134582SN/A 135582SN/A FSTranslatingPortProxy &getVirtProxy() override; 1365886Snate@binkert.org 137388SN/A void 138388SN/A initMemProxies(ThreadContext *tc) override 139388SN/A { 1406026Snate@binkert.org thread->initMemProxies(tc); 1416026Snate@binkert.org } 1426026Snate@binkert.org 1436026Snate@binkert.org SETranslatingPortProxy & 1446026Snate@binkert.org getMemProxy() override 1456026Snate@binkert.org { 1466026Snate@binkert.org return thread->getMemProxy(); 1476026Snate@binkert.org } 1486026Snate@binkert.org 1496026Snate@binkert.org /** Returns this thread's status. */ 1506026Snate@binkert.org Status status() const override { return thread->status(); } 1516026Snate@binkert.org 1526026Snate@binkert.org /** Sets this thread's status. */ 1536026Snate@binkert.org void 1546026Snate@binkert.org setStatus(Status new_status) override 1556026Snate@binkert.org { 1566026Snate@binkert.org thread->setStatus(new_status); 1576026Snate@binkert.org } 1582SN/A 1595886Snate@binkert.org /** Set the status to Active. */ 1602SN/A void activate() override; 161388SN/A 162388SN/A /** Set the status to Suspended. */ 1632SN/A void suspend() override; 1642SN/A 1652SN/A /** Set the status to Halted. */ 1662SN/A void halt() override; 1672SN/A 1682SN/A /** Dumps the function profiling information. 1692SN/A * @todo: Implement. 1705599Snate@binkert.org */ 1715599Snate@binkert.org void dumpFuncProfile() override; 1722SN/A 1732SN/A /** Takes over execution of a thread from another CPU. */ 1742SN/A void takeOverFrom(ThreadContext *old_context) override; 1752SN/A 1762SN/A /** Registers statistics associated with this TC. */ 1772SN/A void regStats(const std::string &name) override; 1782SN/A 1792SN/A /** Reads the last tick that this thread was activated on. */ 1802SN/A Tick readLastActivate() override; 1812SN/A /** Reads the last tick that this thread was suspended on. */ 1822SN/A Tick readLastSuspend() override; 1832SN/A 184388SN/A /** Clears the function profiling information. */ 1855886Snate@binkert.org void profileClear() override; 1862SN/A /** Samples the function profiling information. */ 1876000Snate@binkert.org void profileSample() override; 188582SN/A 189695SN/A /** Copies the architectural registers from another TC into this TC. */ 190388SN/A void copyArchRegs(ThreadContext *tc) override; 191388SN/A 192388SN/A /** Resets all architectural registers to 0. */ 193388SN/A void clearArchRegs() override; 1942SN/A 195434SN/A /** Reads an integer register. */ 196388SN/A RegVal 197388SN/A readReg(RegIndex reg_idx) 198388SN/A { 1992SN/A return readIntRegFlat(flattenRegId(RegId(IntRegClass, 200388SN/A reg_idx)).index()); 2012SN/A } 2022SN/A RegVal 2036001Snate@binkert.org readIntReg(RegIndex reg_idx) const override 2046001Snate@binkert.org { 2056001Snate@binkert.org return readIntRegFlat(flattenRegId(RegId(IntRegClass, 2066001Snate@binkert.org reg_idx)).index()); 2076001Snate@binkert.org } 2086001Snate@binkert.org 2096128Snate@binkert.org RegVal 2106001Snate@binkert.org readFloatReg(RegIndex reg_idx) const override 2116001Snate@binkert.org { 2126001Snate@binkert.org return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 2136001Snate@binkert.org reg_idx)).index()); 2146001Snate@binkert.org } 2156001Snate@binkert.org 2166001Snate@binkert.org const VecRegContainer & 2176001Snate@binkert.org readVecReg(const RegId& id) const override 2186001Snate@binkert.org { 2196128Snate@binkert.org return readVecRegFlat(flattenRegId(id).index()); 2206001Snate@binkert.org } 2216001Snate@binkert.org 2226001Snate@binkert.org /** 2236001Snate@binkert.org * Read vector register operand for modification, hierarchical indexing. 2246001Snate@binkert.org */ 2256001Snate@binkert.org VecRegContainer & 2266001Snate@binkert.org getWritableVecReg(const RegId& id) override 2276001Snate@binkert.org { 2286001Snate@binkert.org return getWritableVecRegFlat(flattenRegId(id).index()); 2296128Snate@binkert.org } 2306001Snate@binkert.org 2316001Snate@binkert.org /** Vector Register Lane Interfaces. */ 2326001Snate@binkert.org /** @{ */ 2336001Snate@binkert.org /** Reads source vector 8bit operand. */ 2346001Snate@binkert.org ConstVecLane8 2356001Snate@binkert.org readVec8BitLaneReg(const RegId& id) const override 2366001Snate@binkert.org { 2376001Snate@binkert.org return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 238695SN/A id.elemIndex()); 239388SN/A } 240388SN/A 241388SN/A /** Reads source vector 16bit operand. */ 242388SN/A ConstVecLane16 243388SN/A readVec16BitLaneReg(const RegId& id) const override 244388SN/A { 245388SN/A return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 246388SN/A id.elemIndex()); 247388SN/A } 248388SN/A 249388SN/A /** Reads source vector 32bit operand. */ 250388SN/A ConstVecLane32 251388SN/A readVec32BitLaneReg(const RegId& id) const override 252388SN/A { 253388SN/A return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 254388SN/A id.elemIndex()); 255388SN/A } 256388SN/A 257388SN/A /** Reads source vector 64bit operand. */ 258388SN/A ConstVecLane64 259388SN/A readVec64BitLaneReg(const RegId& id) const override 260388SN/A { 261388SN/A return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 262388SN/A id.elemIndex()); 263695SN/A } 264388SN/A 265388SN/A /** Write a lane of the destination vector register. */ 266388SN/A void 267388SN/A setVecLane(const RegId& reg, 268388SN/A const LaneData<LaneSize::Byte>& val) override 269388SN/A { 270142SN/A return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 2716000Snate@binkert.org } 2726000Snate@binkert.org void 2736000Snate@binkert.org setVecLane(const RegId& reg, 2746000Snate@binkert.org const LaneData<LaneSize::TwoByte>& val) override 2756000Snate@binkert.org { 2766000Snate@binkert.org return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 2776000Snate@binkert.org } 2786000Snate@binkert.org void 2796000Snate@binkert.org setVecLane(const RegId& reg, 2806000Snate@binkert.org const LaneData<LaneSize::FourByte>& val) override 2816000Snate@binkert.org { 2826000Snate@binkert.org return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 2836000Snate@binkert.org } 2846000Snate@binkert.org void 2856000Snate@binkert.org setVecLane(const RegId& reg, 2866000Snate@binkert.org const LaneData<LaneSize::EightByte>& val) override 2876000Snate@binkert.org { 2886000Snate@binkert.org return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 2896000Snate@binkert.org } 2906000Snate@binkert.org /** @} */ 2916000Snate@binkert.org 2926000Snate@binkert.org const VecElem & 2936000Snate@binkert.org readVecElem(const RegId& reg) const override 2946000Snate@binkert.org { 2956000Snate@binkert.org return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 2966000Snate@binkert.org } 2976000Snate@binkert.org 2986000Snate@binkert.org const VecPredRegContainer & 2996000Snate@binkert.org readVecPredReg(const RegId& id) const override 3006000Snate@binkert.org { 3016000Snate@binkert.org return readVecPredRegFlat(flattenRegId(id).index()); 3026000Snate@binkert.org } 3036000Snate@binkert.org 3046000Snate@binkert.org VecPredRegContainer& 3056000Snate@binkert.org getWritableVecPredReg(const RegId& id) override 3066000Snate@binkert.org { 3076000Snate@binkert.org return getWritableVecPredRegFlat(flattenRegId(id).index()); 3086000Snate@binkert.org } 3096000Snate@binkert.org 3106000Snate@binkert.org RegVal 3116000Snate@binkert.org readCCReg(RegIndex reg_idx) const override 3126000Snate@binkert.org { 3136000Snate@binkert.org return readCCRegFlat(flattenRegId(RegId(CCRegClass, 3146000Snate@binkert.org reg_idx)).index()); 3156001Snate@binkert.org } 3162SN/A 3175887Snate@binkert.org /** Sets an integer register to a value. */ 318695SN/A void 3195887Snate@binkert.org setIntReg(RegIndex reg_idx, RegVal val) override 3205887Snate@binkert.org { 3215886Snate@binkert.org setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 3225886Snate@binkert.org } 3235886Snate@binkert.org 3245889Snate@binkert.org void 325695SN/A setFloatReg(RegIndex reg_idx, RegVal val) override 326695SN/A { 3275599Snate@binkert.org setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 3285887Snate@binkert.org reg_idx)).index(), val); 3295886Snate@binkert.org } 3305886Snate@binkert.org 3315886Snate@binkert.org void 332695SN/A setVecReg(const RegId& reg, const VecRegContainer& val) override 333695SN/A { 3345887Snate@binkert.org setVecRegFlat(flattenRegId(reg).index(), val); 335695SN/A } 3366001Snate@binkert.org 3376001Snate@binkert.org void 3386001Snate@binkert.org setVecElem(const RegId& reg, const VecElem& val) override 3396001Snate@binkert.org { 3406001Snate@binkert.org setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 341695SN/A } 3426001Snate@binkert.org 3436001Snate@binkert.org void 3446001Snate@binkert.org setVecPredReg(const RegId& reg, 3456001Snate@binkert.org const VecPredRegContainer& val) override 3466001Snate@binkert.org { 3476001Snate@binkert.org setVecPredRegFlat(flattenRegId(reg).index(), val); 3486001Snate@binkert.org } 3496001Snate@binkert.org 3506001Snate@binkert.org void 351695SN/A setCCReg(RegIndex reg_idx, RegVal val) override 3522SN/A { 3532SN/A setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 354695SN/A } 3552SN/A 356456SN/A /** Reads this thread's PC state. */ 357695SN/A TheISA::PCState 358456SN/A pcState() const override 3595887Snate@binkert.org { 3605887Snate@binkert.org return cpu->pcState(thread->threadId()); 361695SN/A } 3625886Snate@binkert.org 3635886Snate@binkert.org /** Sets this thread's PC state. */ 364695SN/A void pcState(const TheISA::PCState &val) override; 365695SN/A 366695SN/A void pcStateNoRecord(const TheISA::PCState &val) override; 367695SN/A 368456SN/A /** Reads this thread's PC. */ 369456SN/A Addr 370456SN/A instAddr() const override 371394SN/A { 372148SN/A return cpu->instAddr(thread->threadId()); 373148SN/A } 374148SN/A 375148SN/A /** Reads this thread's next PC. */ 376729SN/A Addr 377 nextInstAddr() const override 378 { 379 return cpu->nextInstAddr(thread->threadId()); 380 } 381 382 /** Reads this thread's next PC. */ 383 MicroPC 384 microPC() const override 385 { 386 return cpu->microPC(thread->threadId()); 387 } 388 389 /** Reads a miscellaneous register. */ 390 RegVal 391 readMiscRegNoEffect(RegIndex misc_reg) const override 392 { 393 return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); 394 } 395 396 /** Reads a misc. register, including any side-effects the 397 * read might have as defined by the architecture. */ 398 RegVal 399 readMiscReg(RegIndex misc_reg) override 400 { 401 return cpu->readMiscReg(misc_reg, thread->threadId()); 402 } 403 404 /** Sets a misc. register. */ 405 void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override; 406 407 /** Sets a misc. register, including any side-effects the 408 * write might have as defined by the architecture. */ 409 void setMiscReg(RegIndex misc_reg, RegVal val) override; 410 411 RegId flattenRegId(const RegId& regId) const override; 412 413 /** Returns the number of consecutive store conditional failures. */ 414 // @todo: Figure out where these store cond failures should go. 415 unsigned 416 readStCondFailures() const override 417 { 418 return thread->storeCondFailures; 419 } 420 421 /** Sets the number of consecutive store conditional failures. */ 422 void 423 setStCondFailures(unsigned sc_failures) override 424 { 425 thread->storeCondFailures = sc_failures; 426 } 427 428 /** Executes a syscall in SE mode. */ 429 void 430 syscall(int64_t callnum, Fault *fault) override 431 { 432 return cpu->syscall(callnum, thread->threadId(), fault); 433 } 434 435 /** Reads the funcExeInst counter. */ 436 Counter readFuncExeInst() const override { return thread->funcExeInst; } 437 438 /** Returns pointer to the quiesce event. */ 439 EndQuiesceEvent * 440 getQuiesceEvent() override 441 { 442 return this->thread->quiesceEvent; 443 } 444 /** check if the cpu is currently in state update mode and squash if not. 445 * This function will return true if a trap is pending or if a fault or 446 * similar is currently writing to the thread context and doesn't want 447 * reset all the state (see noSquashFromTC). 448 */ 449 inline void 450 conditionalSquash() 451 { 452 if (!thread->trapPending && !thread->noSquashFromTC) 453 cpu->squashFromTC(thread->threadId()); 454 } 455 456 RegVal readIntRegFlat(RegIndex idx) const override; 457 void setIntRegFlat(RegIndex idx, RegVal val) override; 458 459 RegVal readFloatRegFlat(RegIndex idx) const override; 460 void setFloatRegFlat(RegIndex idx, RegVal val) override; 461 462 const VecRegContainer& readVecRegFlat(RegIndex idx) const override; 463 /** Read vector register operand for modification, flat indexing. */ 464 VecRegContainer& getWritableVecRegFlat(RegIndex idx) override; 465 void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override; 466 467 template <typename VecElem> 468 VecLaneT<VecElem, true> 469 readVecLaneFlat(RegIndex idx, int lId) const 470 { 471 return cpu->template readArchVecLane<VecElem>(idx, lId, 472 thread->threadId()); 473 } 474 475 template <typename LD> 476 void 477 setVecLaneFlat(int idx, int lId, const LD& val) 478 { 479 cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 480 } 481 482 const VecElem &readVecElemFlat(RegIndex idx, 483 const ElemIndex& elemIndex) const override; 484 void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 485 const VecElem& val) override; 486 487 const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override; 488 VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override; 489 void setVecPredRegFlat(RegIndex idx, 490 const VecPredRegContainer& val) override; 491 492 RegVal readCCRegFlat(RegIndex idx) const override; 493 void setCCRegFlat(RegIndex idx, RegVal val) override; 494}; 495 496#endif 497