thread_context.hh revision 13865:cca49fc49c57 
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    BaseTLB *getITBPtr() override { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    BaseTLB *getDTBPtr() override { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
88
89    TheISA::ISA *
90    getIsaPtr() override
91    {
92        return cpu->isa[thread->threadId()];
93    }
94
95    TheISA::Decoder *
96    getDecoderPtr() override
97    {
98        return cpu->fetch.decoder[thread->threadId()];
99    }
100
101    /** Returns a pointer to this CPU. */
102    BaseCPU *getCpuPtr() override { return cpu; }
103
104    /** Reads this CPU's ID. */
105    int cpuId() const override { return cpu->cpuId(); }
106
107    /** Reads this CPU's Socket ID. */
108    uint32_t socketId() const override { return cpu->socketId(); }
109
110    ContextID contextId() const override { return thread->contextId(); }
111
112    void setContextId(ContextID id) override { thread->setContextId(id); }
113
114    /** Returns this thread's ID number. */
115    int threadId() const override { return thread->threadId(); }
116    void setThreadId(int id) override { return thread->setThreadId(id); }
117
118    /** Returns a pointer to the system. */
119    System *getSystemPtr() override { return cpu->system; }
120
121    /** Returns a pointer to this thread's kernel statistics. */
122    TheISA::Kernel::Statistics *
123    getKernelStats() override
124    {
125        return thread->kernelStats;
126    }
127
128    /** Returns a pointer to this thread's process. */
129    Process *getProcessPtr() override { return thread->getProcessPtr(); }
130
131    void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
132
133    PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
134
135    FSTranslatingPortProxy &getVirtProxy() override;
136
137    void
138    initMemProxies(ThreadContext *tc) override
139    {
140        thread->initMemProxies(tc);
141    }
142
143    SETranslatingPortProxy &
144    getMemProxy() override
145    {
146        return thread->getMemProxy();
147    }
148
149    /** Returns this thread's status. */
150    Status status() const override { return thread->status(); }
151
152    /** Sets this thread's status. */
153    void
154    setStatus(Status new_status) override
155    {
156        thread->setStatus(new_status);
157    }
158
159    /** Set the status to Active. */
160    void activate() override;
161
162    /** Set the status to Suspended. */
163    void suspend() override;
164
165    /** Set the status to Halted. */
166    void halt() override;
167
168    /** Dumps the function profiling information.
169     * @todo: Implement.
170     */
171    void dumpFuncProfile() override;
172
173    /** Takes over execution of a thread from another CPU. */
174    void takeOverFrom(ThreadContext *old_context) override;
175
176    /** Registers statistics associated with this TC. */
177    void regStats(const std::string &name) override;
178
179    /** Reads the last tick that this thread was activated on. */
180    Tick readLastActivate() override;
181    /** Reads the last tick that this thread was suspended on. */
182    Tick readLastSuspend() override;
183
184    /** Clears the function profiling information. */
185    void profileClear() override;
186    /** Samples the function profiling information. */
187    void profileSample() override;
188
189    /** Copies the architectural registers from another TC into this TC. */
190    void copyArchRegs(ThreadContext *tc) override;
191
192    /** Resets all architectural registers to 0. */
193    void clearArchRegs() override;
194
195    /** Reads an integer register. */
196    RegVal
197    readReg(RegIndex reg_idx)
198    {
199        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
200                                                 reg_idx)).index());
201    }
202    RegVal
203    readIntReg(RegIndex reg_idx) const override
204    {
205        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
206                                                 reg_idx)).index());
207    }
208
209    RegVal
210    readFloatReg(RegIndex reg_idx) const override
211    {
212        return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
213                                             reg_idx)).index());
214    }
215
216    const VecRegContainer &
217    readVecReg(const RegId& id) const override
218    {
219        return readVecRegFlat(flattenRegId(id).index());
220    }
221
222    /**
223     * Read vector register operand for modification, hierarchical indexing.
224     */
225    VecRegContainer &
226    getWritableVecReg(const RegId& id) override
227    {
228        return getWritableVecRegFlat(flattenRegId(id).index());
229    }
230
231    /** Vector Register Lane Interfaces. */
232    /** @{ */
233    /** Reads source vector 8bit operand. */
234    ConstVecLane8
235    readVec8BitLaneReg(const RegId& id) const override
236    {
237        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
238                    id.elemIndex());
239    }
240
241    /** Reads source vector 16bit operand. */
242    ConstVecLane16
243    readVec16BitLaneReg(const RegId& id) const override
244    {
245        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
246                    id.elemIndex());
247    }
248
249    /** Reads source vector 32bit operand. */
250    ConstVecLane32
251    readVec32BitLaneReg(const RegId& id) const override
252    {
253        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
254                    id.elemIndex());
255    }
256
257    /** Reads source vector 64bit operand. */
258    ConstVecLane64
259    readVec64BitLaneReg(const RegId& id) const override
260    {
261        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
262                    id.elemIndex());
263    }
264
265    /** Write a lane of the destination vector register. */
266    void
267    setVecLane(const RegId& reg,
268               const LaneData<LaneSize::Byte>& val) override
269    {
270        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
271    }
272    void
273    setVecLane(const RegId& reg,
274               const LaneData<LaneSize::TwoByte>& val) override
275    {
276        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
277    }
278    void
279    setVecLane(const RegId& reg,
280               const LaneData<LaneSize::FourByte>& val) override
281    {
282        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
283    }
284    void
285    setVecLane(const RegId& reg,
286               const LaneData<LaneSize::EightByte>& val) override
287    {
288        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
289    }
290    /** @} */
291
292    const VecElem &
293    readVecElem(const RegId& reg) const override
294    {
295        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
296    }
297
298    const VecPredRegContainer &
299    readVecPredReg(const RegId& id) const override
300    {
301        return readVecPredRegFlat(flattenRegId(id).index());
302    }
303
304    VecPredRegContainer&
305    getWritableVecPredReg(const RegId& id) override
306    {
307        return getWritableVecPredRegFlat(flattenRegId(id).index());
308    }
309
310    RegVal
311    readCCReg(RegIndex reg_idx) const override
312    {
313        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
314                                                 reg_idx)).index());
315    }
316
317    /** Sets an integer register to a value. */
318    void
319    setIntReg(RegIndex reg_idx, RegVal val) override
320    {
321        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
322    }
323
324    void
325    setFloatReg(RegIndex reg_idx, RegVal val) override
326    {
327        setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
328                                           reg_idx)).index(), val);
329    }
330
331    void
332    setVecReg(const RegId& reg, const VecRegContainer& val) override
333    {
334        setVecRegFlat(flattenRegId(reg).index(), val);
335    }
336
337    void
338    setVecElem(const RegId& reg, const VecElem& val) override
339    {
340        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
341    }
342
343    void
344    setVecPredReg(const RegId& reg,
345                  const VecPredRegContainer& val) override
346    {
347        setVecPredRegFlat(flattenRegId(reg).index(), val);
348    }
349
350    void
351    setCCReg(RegIndex reg_idx, RegVal val) override
352    {
353        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
354    }
355
356    /** Reads this thread's PC state. */
357    TheISA::PCState
358    pcState() const override
359    {
360        return cpu->pcState(thread->threadId());
361    }
362
363    /** Sets this thread's PC state. */
364    void pcState(const TheISA::PCState &val) override;
365
366    void pcStateNoRecord(const TheISA::PCState &val) override;
367
368    /** Reads this thread's PC. */
369    Addr
370    instAddr() const override
371    {
372        return cpu->instAddr(thread->threadId());
373    }
374
375    /** Reads this thread's next PC. */
376    Addr
377    nextInstAddr() const override
378    {
379        return cpu->nextInstAddr(thread->threadId());
380    }
381
382    /** Reads this thread's next PC. */
383    MicroPC
384    microPC() const override
385    {
386        return cpu->microPC(thread->threadId());
387    }
388
389    /** Reads a miscellaneous register. */
390    RegVal
391    readMiscRegNoEffect(RegIndex misc_reg) const override
392    {
393        return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
394    }
395
396    /** Reads a misc. register, including any side-effects the
397     * read might have as defined by the architecture. */
398    RegVal
399    readMiscReg(RegIndex misc_reg) override
400    {
401        return cpu->readMiscReg(misc_reg, thread->threadId());
402    }
403
404    /** Sets a misc. register. */
405    void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
406
407    /** Sets a misc. register, including any side-effects the
408     * write might have as defined by the architecture. */
409    void setMiscReg(RegIndex misc_reg, RegVal val) override;
410
411    RegId flattenRegId(const RegId& regId) const override;
412
413    /** Returns the number of consecutive store conditional failures. */
414    // @todo: Figure out where these store cond failures should go.
415    unsigned
416    readStCondFailures() const override
417    {
418        return thread->storeCondFailures;
419    }
420
421    /** Sets the number of consecutive store conditional failures. */
422    void
423    setStCondFailures(unsigned sc_failures) override
424    {
425        thread->storeCondFailures = sc_failures;
426    }
427
428    /** Executes a syscall in SE mode. */
429    void
430    syscall(int64_t callnum, Fault *fault) override
431    {
432        return cpu->syscall(callnum, thread->threadId(), fault);
433    }
434
435    /** Reads the funcExeInst counter. */
436    Counter readFuncExeInst() const override { return thread->funcExeInst; }
437
438    /** Returns pointer to the quiesce event. */
439    EndQuiesceEvent *
440    getQuiesceEvent() override
441    {
442        return this->thread->quiesceEvent;
443    }
444    /** check if the cpu is currently in state update mode and squash if not.
445     * This function will return true if a trap is pending or if a fault or
446     * similar is currently writing to the thread context and doesn't want
447     * reset all the state (see noSquashFromTC).
448     */
449    inline void
450    conditionalSquash()
451    {
452        if (!thread->trapPending && !thread->noSquashFromTC)
453            cpu->squashFromTC(thread->threadId());
454    }
455
456    RegVal readIntRegFlat(RegIndex idx) const override;
457    void setIntRegFlat(RegIndex idx, RegVal val) override;
458
459    RegVal readFloatRegFlat(RegIndex idx) const override;
460    void setFloatRegFlat(RegIndex idx, RegVal val) override;
461
462    const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
463    /** Read vector register operand for modification, flat indexing. */
464    VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
465    void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
466
467    template <typename VecElem>
468    VecLaneT<VecElem, true>
469    readVecLaneFlat(RegIndex idx, int lId) const
470    {
471        return cpu->template readArchVecLane<VecElem>(idx, lId,
472                thread->threadId());
473    }
474
475    template <typename LD>
476    void
477    setVecLaneFlat(int idx, int lId, const LD& val)
478    {
479        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
480    }
481
482    const VecElem &readVecElemFlat(RegIndex idx,
483                                   const ElemIndex& elemIndex) const override;
484    void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
485                        const VecElem& val) override;
486
487    const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
488    VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
489    void setVecPredRegFlat(RegIndex idx,
490                           const VecPredRegContainer& val) override;
491
492    RegVal readCCRegFlat(RegIndex idx) const override;
493    void setCCRegFlat(RegIndex idx, RegVal val) override;
494};
495
496#endif
497