thread_context.hh revision 13693:85fa3a41014b
12SN/A/* 21458SN/A * Copyright (c) 2011-2012, 2016-2018 ARM Limited 32SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42SN/A * All rights reserved 52SN/A * 62SN/A * The license below extends only to copyright in the software and shall 72SN/A * not be construed as granting a license to any other intellectual 82SN/A * property including but not limited to intellectual property relating 92SN/A * to a hardware implementation of the functionality of the software 102SN/A * licensed hereunder. You may use the software subject to the license 112SN/A * terms below provided that you ensure that this notice is replicated 122SN/A * unmodified and in its entirety in all distributions of the software, 132SN/A * modified or unmodified, in source code or in binary form. 142SN/A * 152SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321147SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331147SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352037SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362037SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372428SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382972Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391858SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4056SN/A * 412SN/A * Authors: Kevin Lim 422107SN/A */ 432SN/A 442972Sgblack@eecs.umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452972Sgblack@eecs.umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462972Sgblack@eecs.umich.edu 472238SN/A#include "config/the_isa.hh" 482238SN/A#include "cpu/o3/isa_specific.hh" 492972Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 502972Sgblack@eecs.umich.edu 512238SN/Aclass EndQuiesceEvent; 522972Sgblack@eecs.umich.edunamespace Kernel { 532238SN/A class Statistics; 542972Sgblack@eecs.umich.edu} 552972Sgblack@eecs.umich.edu 562972Sgblack@eecs.umich.edu/** 572972Sgblack@eecs.umich.edu * Derived ThreadContext class for use with the O3CPU. It 582972Sgblack@eecs.umich.edu * provides the interface for any external objects to access a 592972Sgblack@eecs.umich.edu * single thread's state and some general CPU state. Any time 602972Sgblack@eecs.umich.edu * external objects try to update state through this interface, 612972Sgblack@eecs.umich.edu * the CPU will create an event to squash all in-flight 622972Sgblack@eecs.umich.edu * instructions in order to ensure state is maintained correctly. 632972Sgblack@eecs.umich.edu * It must be defined specifically for the O3CPU because 642972Sgblack@eecs.umich.edu * not all architectural state is located within the O3ThreadState 652972Sgblack@eecs.umich.edu * (such as the commit PC, and registers), and specific actions 662238SN/A * must be taken when using this interface (such as squashing all 672972Sgblack@eecs.umich.edu * in-flight instructions when doing a write to this interface). 682238SN/A */ 692972Sgblack@eecs.umich.edutemplate <class Impl> 702972Sgblack@eecs.umich.educlass O3ThreadContext : public ThreadContext 712972Sgblack@eecs.umich.edu{ 722972Sgblack@eecs.umich.edu public: 732972Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 742972Sgblack@eecs.umich.edu 752972Sgblack@eecs.umich.edu /** Pointer to the CPU. */ 762972Sgblack@eecs.umich.edu O3CPU *cpu; 772972Sgblack@eecs.umich.edu 782972Sgblack@eecs.umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792972Sgblack@eecs.umich.edu O3ThreadState<Impl> *thread; 802972Sgblack@eecs.umich.edu 812972Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 822972Sgblack@eecs.umich.edu BaseTLB *getITBPtr() override { return cpu->itb; } 832972Sgblack@eecs.umich.edu 842972Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 852972Sgblack@eecs.umich.edu BaseTLB *getDTBPtr() override { return cpu->dtb; } 862972Sgblack@eecs.umich.edu 872972Sgblack@eecs.umich.edu CheckerCPU *getCheckerCpuPtr() override { return NULL; } 882972Sgblack@eecs.umich.edu 892972Sgblack@eecs.umich.edu TheISA::ISA * 902972Sgblack@eecs.umich.edu getIsaPtr() override 912972Sgblack@eecs.umich.edu { 922972Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()]; 932972Sgblack@eecs.umich.edu } 942972Sgblack@eecs.umich.edu 952972Sgblack@eecs.umich.edu TheISA::Decoder * 962972Sgblack@eecs.umich.edu getDecoderPtr() override 972972Sgblack@eecs.umich.edu { 982972Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 992972Sgblack@eecs.umich.edu } 1002972Sgblack@eecs.umich.edu 1012972Sgblack@eecs.umich.edu /** Returns a pointer to this CPU. */ 1022972Sgblack@eecs.umich.edu virtual BaseCPU *getCpuPtr() override { return cpu; } 1032972Sgblack@eecs.umich.edu 1042972Sgblack@eecs.umich.edu /** Reads this CPU's ID. */ 1052972Sgblack@eecs.umich.edu virtual int cpuId() const override { return cpu->cpuId(); } 1062972Sgblack@eecs.umich.edu 1072972Sgblack@eecs.umich.edu /** Reads this CPU's Socket ID. */ 1082972Sgblack@eecs.umich.edu virtual uint32_t socketId() const override { return cpu->socketId(); } 1092972Sgblack@eecs.umich.edu 1102972Sgblack@eecs.umich.edu virtual ContextID 1112972Sgblack@eecs.umich.edu contextId() const override { return thread->contextId(); } 1122972Sgblack@eecs.umich.edu 1132972Sgblack@eecs.umich.edu virtual void setContextId(int id) override { thread->setContextId(id); } 1142972Sgblack@eecs.umich.edu 1152972Sgblack@eecs.umich.edu /** Returns this thread's ID number. */ 1162972Sgblack@eecs.umich.edu virtual int threadId() const override 1172972Sgblack@eecs.umich.edu { return thread->threadId(); } 1182972Sgblack@eecs.umich.edu virtual void setThreadId(int id) override 1192972Sgblack@eecs.umich.edu { return thread->setThreadId(id); } 1202972Sgblack@eecs.umich.edu 1212972Sgblack@eecs.umich.edu /** Returns a pointer to the system. */ 1222972Sgblack@eecs.umich.edu virtual System *getSystemPtr() override { return cpu->system; } 1232972Sgblack@eecs.umich.edu 1242972Sgblack@eecs.umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1252972Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() override 1262972Sgblack@eecs.umich.edu { return thread->kernelStats; } 1272972Sgblack@eecs.umich.edu 1282972Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1292972Sgblack@eecs.umich.edu virtual Process *getProcessPtr() override 1302972Sgblack@eecs.umich.edu { return thread->getProcessPtr(); } 1312972Sgblack@eecs.umich.edu 1322972Sgblack@eecs.umich.edu virtual void setProcessPtr(Process *p) override 1332972Sgblack@eecs.umich.edu { thread->setProcessPtr(p); } 1342972Sgblack@eecs.umich.edu 1352972Sgblack@eecs.umich.edu virtual PortProxy &getPhysProxy() override 1362238SN/A { return thread->getPhysProxy(); } 1372238SN/A 1382238SN/A virtual FSTranslatingPortProxy &getVirtProxy() override; 1392512SN/A 1402972Sgblack@eecs.umich.edu virtual void initMemProxies(ThreadContext *tc) override 1412972Sgblack@eecs.umich.edu { thread->initMemProxies(tc); } 1422972Sgblack@eecs.umich.edu 1432972Sgblack@eecs.umich.edu virtual SETranslatingPortProxy &getMemProxy() override 1442972Sgblack@eecs.umich.edu { return thread->getMemProxy(); } 1452972Sgblack@eecs.umich.edu 1462972Sgblack@eecs.umich.edu /** Returns this thread's status. */ 1472972Sgblack@eecs.umich.edu virtual Status status() const override { return thread->status(); } 1482972Sgblack@eecs.umich.edu 1492972Sgblack@eecs.umich.edu /** Sets this thread's status. */ 1502972Sgblack@eecs.umich.edu virtual void setStatus(Status new_status) override 1512972Sgblack@eecs.umich.edu { thread->setStatus(new_status); } 1522972Sgblack@eecs.umich.edu 1532972Sgblack@eecs.umich.edu /** Set the status to Active. */ 1542972Sgblack@eecs.umich.edu virtual void activate() override; 1552972Sgblack@eecs.umich.edu 1562972Sgblack@eecs.umich.edu /** Set the status to Suspended. */ 1572972Sgblack@eecs.umich.edu virtual void suspend() override; 1582972Sgblack@eecs.umich.edu 1592972Sgblack@eecs.umich.edu /** Set the status to Halted. */ 1602972Sgblack@eecs.umich.edu virtual void halt() override; 1612972Sgblack@eecs.umich.edu 1622972Sgblack@eecs.umich.edu /** Dumps the function profiling information. 1632972Sgblack@eecs.umich.edu * @todo: Implement. 1642972Sgblack@eecs.umich.edu */ 1652972Sgblack@eecs.umich.edu virtual void dumpFuncProfile() override; 1662972Sgblack@eecs.umich.edu 1672972Sgblack@eecs.umich.edu /** Takes over execution of a thread from another CPU. */ 1682972Sgblack@eecs.umich.edu virtual void takeOverFrom(ThreadContext *old_context) override; 1692972Sgblack@eecs.umich.edu 1702972Sgblack@eecs.umich.edu /** Registers statistics associated with this TC. */ 1712972Sgblack@eecs.umich.edu virtual void regStats(const std::string &name) override; 1722972Sgblack@eecs.umich.edu 1732972Sgblack@eecs.umich.edu /** Reads the last tick that this thread was activated on. */ 1742972Sgblack@eecs.umich.edu virtual Tick readLastActivate() override; 1752972Sgblack@eecs.umich.edu /** Reads the last tick that this thread was suspended on. */ 1762972Sgblack@eecs.umich.edu virtual Tick readLastSuspend() override; 1772972Sgblack@eecs.umich.edu 1782972Sgblack@eecs.umich.edu /** Clears the function profiling information. */ 1792972Sgblack@eecs.umich.edu virtual void profileClear() override; 1802972Sgblack@eecs.umich.edu /** Samples the function profiling information. */ 1812972Sgblack@eecs.umich.edu virtual void profileSample() override; 1822972Sgblack@eecs.umich.edu 1832972Sgblack@eecs.umich.edu /** Copies the architectural registers from another TC into this TC. */ 1842972Sgblack@eecs.umich.edu virtual void copyArchRegs(ThreadContext *tc) override; 1852972Sgblack@eecs.umich.edu 1862972Sgblack@eecs.umich.edu /** Resets all architectural registers to 0. */ 1872972Sgblack@eecs.umich.edu virtual void clearArchRegs() override; 1882972Sgblack@eecs.umich.edu 1892972Sgblack@eecs.umich.edu /** Reads an integer register. */ 1902972Sgblack@eecs.umich.edu virtual RegVal 1912972Sgblack@eecs.umich.edu readReg(int reg_idx) 1922972Sgblack@eecs.umich.edu { 1932972Sgblack@eecs.umich.edu return readIntRegFlat(flattenRegId(RegId(IntRegClass, 1942972Sgblack@eecs.umich.edu reg_idx)).index()); 1952972Sgblack@eecs.umich.edu } 1962972Sgblack@eecs.umich.edu virtual RegVal 1972972Sgblack@eecs.umich.edu readIntReg(int reg_idx) override 1982972Sgblack@eecs.umich.edu { 1992972Sgblack@eecs.umich.edu return readIntRegFlat(flattenRegId(RegId(IntRegClass, 2002972Sgblack@eecs.umich.edu reg_idx)).index()); 2012972Sgblack@eecs.umich.edu } 2022972Sgblack@eecs.umich.edu 2032972Sgblack@eecs.umich.edu virtual RegVal 2042972Sgblack@eecs.umich.edu readFloatReg(int reg_idx) override 2052972Sgblack@eecs.umich.edu { 2062972Sgblack@eecs.umich.edu return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 2072972Sgblack@eecs.umich.edu reg_idx)).index()); 2082972Sgblack@eecs.umich.edu } 2092972Sgblack@eecs.umich.edu 2102972Sgblack@eecs.umich.edu virtual const VecRegContainer & 2112972Sgblack@eecs.umich.edu readVecReg(const RegId& id) const override 2122972Sgblack@eecs.umich.edu { 2132972Sgblack@eecs.umich.edu return readVecRegFlat(flattenRegId(id).index()); 2142972Sgblack@eecs.umich.edu } 2152972Sgblack@eecs.umich.edu 2162972Sgblack@eecs.umich.edu /** 2172972Sgblack@eecs.umich.edu * Read vector register operand for modification, hierarchical indexing. 2182972Sgblack@eecs.umich.edu */ 2192972Sgblack@eecs.umich.edu virtual VecRegContainer & 2202972Sgblack@eecs.umich.edu getWritableVecReg(const RegId& id) override 2212972Sgblack@eecs.umich.edu { 2222972Sgblack@eecs.umich.edu return getWritableVecRegFlat(flattenRegId(id).index()); 2232972Sgblack@eecs.umich.edu } 2242972Sgblack@eecs.umich.edu 2252972Sgblack@eecs.umich.edu /** Vector Register Lane Interfaces. */ 2262972Sgblack@eecs.umich.edu /** @{ */ 2272972Sgblack@eecs.umich.edu /** Reads source vector 8bit operand. */ 2282972Sgblack@eecs.umich.edu virtual ConstVecLane8 2292972Sgblack@eecs.umich.edu readVec8BitLaneReg(const RegId& id) const override 2302972Sgblack@eecs.umich.edu { 2312512SN/A return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 2322512SN/A id.elemIndex()); 2332972Sgblack@eecs.umich.edu } 2342512SN/A 2352972Sgblack@eecs.umich.edu /** Reads source vector 16bit operand. */ 2362972Sgblack@eecs.umich.edu virtual ConstVecLane16 2372972Sgblack@eecs.umich.edu readVec16BitLaneReg(const RegId& id) const override 2382972Sgblack@eecs.umich.edu { 2392972Sgblack@eecs.umich.edu return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 2402SN/A id.elemIndex()); 2412972Sgblack@eecs.umich.edu } 2422972Sgblack@eecs.umich.edu 2432972Sgblack@eecs.umich.edu /** Reads source vector 32bit operand. */ 2442449SN/A virtual ConstVecLane32 2452972Sgblack@eecs.umich.edu readVec32BitLaneReg(const RegId& id) const override 2462972Sgblack@eecs.umich.edu { 2472227SN/A return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 2482972Sgblack@eecs.umich.edu id.elemIndex()); 2492SN/A } 2502972Sgblack@eecs.umich.edu 2512972Sgblack@eecs.umich.edu /** Reads source vector 64bit operand. */ 2522972Sgblack@eecs.umich.edu virtual ConstVecLane64 2532972Sgblack@eecs.umich.edu readVec64BitLaneReg(const RegId& id) const override 2542972Sgblack@eecs.umich.edu { 2552972Sgblack@eecs.umich.edu return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 2562972Sgblack@eecs.umich.edu id.elemIndex()); 2572972Sgblack@eecs.umich.edu } 2582972Sgblack@eecs.umich.edu 2592972Sgblack@eecs.umich.edu /** Write a lane of the destination vector register. */ 2602972Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2612972Sgblack@eecs.umich.edu const LaneData<LaneSize::Byte>& val) override 2622972Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2632972Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2642972Sgblack@eecs.umich.edu const LaneData<LaneSize::TwoByte>& val) override 2652972Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2662972Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2672972Sgblack@eecs.umich.edu const LaneData<LaneSize::FourByte>& val) override 2682972Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2692972Sgblack@eecs.umich.edu virtual void setVecLane(const RegId& reg, 2702972Sgblack@eecs.umich.edu const LaneData<LaneSize::EightByte>& val) override 2712972Sgblack@eecs.umich.edu { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 2722972Sgblack@eecs.umich.edu /** @} */ 2732972Sgblack@eecs.umich.edu 2742972Sgblack@eecs.umich.edu virtual const VecElem& readVecElem(const RegId& reg) const override { 2752972Sgblack@eecs.umich.edu return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 2762972Sgblack@eecs.umich.edu } 2772972Sgblack@eecs.umich.edu 2782972Sgblack@eecs.umich.edu virtual const VecPredRegContainer& 2792972Sgblack@eecs.umich.edu readVecPredReg(const RegId& id) const override { 2802972Sgblack@eecs.umich.edu return readVecPredRegFlat(flattenRegId(id).index()); 2812972Sgblack@eecs.umich.edu } 2822972Sgblack@eecs.umich.edu 2832972Sgblack@eecs.umich.edu virtual VecPredRegContainer& 2842972Sgblack@eecs.umich.edu getWritableVecPredReg(const RegId& id) override { 2852972Sgblack@eecs.umich.edu return getWritableVecPredRegFlat(flattenRegId(id).index()); 2862972Sgblack@eecs.umich.edu } 2872972Sgblack@eecs.umich.edu 2882972Sgblack@eecs.umich.edu virtual RegVal 2892972Sgblack@eecs.umich.edu readCCReg(int reg_idx) override 2902264SN/A { 2912107SN/A return readCCRegFlat(flattenRegId(RegId(CCRegClass, 2921147SN/A reg_idx)).index()); 293 } 294 295 /** Sets an integer register to a value. */ 296 virtual void 297 setIntReg(int reg_idx, RegVal val) override 298 { 299 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 300 } 301 302 virtual void 303 setFloatReg(int reg_idx, RegVal val) override 304 { 305 setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 306 reg_idx)).index(), val); 307 } 308 309 virtual void 310 setVecReg(const RegId& reg, const VecRegContainer& val) override 311 { 312 setVecRegFlat(flattenRegId(reg).index(), val); 313 } 314 315 virtual void 316 setVecElem(const RegId& reg, const VecElem& val) override 317 { 318 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 319 } 320 321 virtual void 322 setVecPredReg(const RegId& reg, 323 const VecPredRegContainer& val) override 324 { 325 setVecPredRegFlat(flattenRegId(reg).index(), val); 326 } 327 328 virtual void 329 setCCReg(int reg_idx, RegVal val) override 330 { 331 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 332 } 333 334 /** Reads this thread's PC state. */ 335 virtual TheISA::PCState pcState() override 336 { return cpu->pcState(thread->threadId()); } 337 338 /** Sets this thread's PC state. */ 339 virtual void pcState(const TheISA::PCState &val) override; 340 341 virtual void pcStateNoRecord(const TheISA::PCState &val) override; 342 343 /** Reads this thread's PC. */ 344 virtual Addr instAddr() override 345 { return cpu->instAddr(thread->threadId()); } 346 347 /** Reads this thread's next PC. */ 348 virtual Addr nextInstAddr() override 349 { return cpu->nextInstAddr(thread->threadId()); } 350 351 /** Reads this thread's next PC. */ 352 virtual MicroPC microPC() override 353 { return cpu->microPC(thread->threadId()); } 354 355 /** Reads a miscellaneous register. */ 356 virtual RegVal readMiscRegNoEffect(int misc_reg) const override 357 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 358 359 /** Reads a misc. register, including any side-effects the 360 * read might have as defined by the architecture. */ 361 virtual RegVal readMiscReg(int misc_reg) override 362 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 363 364 /** Sets a misc. register. */ 365 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; 366 367 /** Sets a misc. register, including any side-effects the 368 * write might have as defined by the architecture. */ 369 virtual void setMiscReg(int misc_reg, RegVal val) override; 370 371 virtual RegId flattenRegId(const RegId& regId) const override; 372 373 /** Returns the number of consecutive store conditional failures. */ 374 // @todo: Figure out where these store cond failures should go. 375 virtual unsigned readStCondFailures() override 376 { return thread->storeCondFailures; } 377 378 /** Sets the number of consecutive store conditional failures. */ 379 virtual void setStCondFailures(unsigned sc_failures) override 380 { thread->storeCondFailures = sc_failures; } 381 382 /** Executes a syscall in SE mode. */ 383 virtual void syscall(int64_t callnum, Fault *fault) override 384 { return cpu->syscall(callnum, thread->threadId(), fault); } 385 386 /** Reads the funcExeInst counter. */ 387 virtual Counter readFuncExeInst() override { return thread->funcExeInst; } 388 389 /** Returns pointer to the quiesce event. */ 390 virtual EndQuiesceEvent * 391 getQuiesceEvent() override 392 { 393 return this->thread->quiesceEvent; 394 } 395 /** check if the cpu is currently in state update mode and squash if not. 396 * This function will return true if a trap is pending or if a fault or 397 * similar is currently writing to the thread context and doesn't want 398 * reset all the state (see noSquashFromTC). 399 */ 400 inline void 401 conditionalSquash() 402 { 403 if (!thread->trapPending && !thread->noSquashFromTC) 404 cpu->squashFromTC(thread->threadId()); 405 } 406 407 virtual RegVal readIntRegFlat(int idx) override; 408 virtual void setIntRegFlat(int idx, RegVal val) override; 409 410 virtual RegVal readFloatRegFlat(int idx) override; 411 virtual void setFloatRegFlat(int idx, RegVal val) override; 412 413 virtual const VecRegContainer& readVecRegFlat(int idx) const override; 414 /** Read vector register operand for modification, flat indexing. */ 415 virtual VecRegContainer& getWritableVecRegFlat(int idx) override; 416 virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; 417 418 template <typename VecElem> 419 VecLaneT<VecElem, true> 420 readVecLaneFlat(int idx, int lId) const 421 { 422 return cpu->template readArchVecLane<VecElem>(idx, lId, 423 thread->threadId()); 424 } 425 426 template <typename LD> 427 void setVecLaneFlat(int idx, int lId, const LD& val) 428 { 429 cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 430 } 431 432 virtual const VecElem& readVecElemFlat( 433 const RegIndex& idx, 434 const ElemIndex& elemIndex) const override; 435 virtual void setVecElemFlat( 436 const RegIndex& idx, 437 const ElemIndex& elemIdx, const VecElem& val) override; 438 439 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 440 const override; 441 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 442 virtual void setVecPredRegFlat(int idx, 443 const VecPredRegContainer& val) override; 444 445 virtual RegVal readCCRegFlat(int idx) override; 446 virtual void setCCRegFlat(int idx, RegVal val) override; 447}; 448 449#endif 450