thread_context.hh revision 13693:85fa3a41014b 
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    BaseTLB *getITBPtr() override { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    BaseTLB *getDTBPtr() override { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
88
89    TheISA::ISA *
90    getIsaPtr() override
91    {
92        return cpu->isa[thread->threadId()];
93    }
94
95    TheISA::Decoder *
96    getDecoderPtr() override
97    {
98        return cpu->fetch.decoder[thread->threadId()];
99    }
100
101    /** Returns a pointer to this CPU. */
102    virtual BaseCPU *getCpuPtr() override { return cpu; }
103
104    /** Reads this CPU's ID. */
105    virtual int cpuId() const override { return cpu->cpuId(); }
106
107    /** Reads this CPU's Socket ID. */
108    virtual uint32_t socketId() const override { return cpu->socketId(); }
109
110    virtual ContextID
111    contextId() const override { return thread->contextId(); }
112
113    virtual void setContextId(int id) override { thread->setContextId(id); }
114
115    /** Returns this thread's ID number. */
116    virtual int threadId() const override
117    { return thread->threadId(); }
118    virtual void setThreadId(int id) override
119    { return thread->setThreadId(id); }
120
121    /** Returns a pointer to the system. */
122    virtual System *getSystemPtr() override { return cpu->system; }
123
124    /** Returns a pointer to this thread's kernel statistics. */
125    virtual TheISA::Kernel::Statistics *getKernelStats() override
126    { return thread->kernelStats; }
127
128    /** Returns a pointer to this thread's process. */
129    virtual Process *getProcessPtr() override
130    { return thread->getProcessPtr(); }
131
132    virtual void setProcessPtr(Process *p) override
133    { thread->setProcessPtr(p); }
134
135    virtual PortProxy &getPhysProxy() override
136    { return thread->getPhysProxy(); }
137
138    virtual FSTranslatingPortProxy &getVirtProxy() override;
139
140    virtual void initMemProxies(ThreadContext *tc) override
141    { thread->initMemProxies(tc); }
142
143    virtual SETranslatingPortProxy &getMemProxy() override
144    { return thread->getMemProxy(); }
145
146    /** Returns this thread's status. */
147    virtual Status status() const override { return thread->status(); }
148
149    /** Sets this thread's status. */
150    virtual void setStatus(Status new_status) override
151    { thread->setStatus(new_status); }
152
153    /** Set the status to Active. */
154    virtual void activate() override;
155
156    /** Set the status to Suspended. */
157    virtual void suspend() override;
158
159    /** Set the status to Halted. */
160    virtual void halt() override;
161
162    /** Dumps the function profiling information.
163     * @todo: Implement.
164     */
165    virtual void dumpFuncProfile() override;
166
167    /** Takes over execution of a thread from another CPU. */
168    virtual void takeOverFrom(ThreadContext *old_context) override;
169
170    /** Registers statistics associated with this TC. */
171    virtual void regStats(const std::string &name) override;
172
173    /** Reads the last tick that this thread was activated on. */
174    virtual Tick readLastActivate() override;
175    /** Reads the last tick that this thread was suspended on. */
176    virtual Tick readLastSuspend() override;
177
178    /** Clears the function profiling information. */
179    virtual void profileClear() override;
180    /** Samples the function profiling information. */
181    virtual void profileSample() override;
182
183    /** Copies the architectural registers from another TC into this TC. */
184    virtual void copyArchRegs(ThreadContext *tc) override;
185
186    /** Resets all architectural registers to 0. */
187    virtual void clearArchRegs() override;
188
189    /** Reads an integer register. */
190    virtual RegVal
191    readReg(int reg_idx)
192    {
193        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
194                                                 reg_idx)).index());
195    }
196    virtual RegVal
197    readIntReg(int reg_idx) override
198    {
199        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
200                                                 reg_idx)).index());
201    }
202
203    virtual RegVal
204    readFloatReg(int reg_idx) override
205    {
206        return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
207                                             reg_idx)).index());
208    }
209
210    virtual const VecRegContainer &
211    readVecReg(const RegId& id) const override
212    {
213        return readVecRegFlat(flattenRegId(id).index());
214    }
215
216    /**
217     * Read vector register operand for modification, hierarchical indexing.
218     */
219    virtual VecRegContainer &
220    getWritableVecReg(const RegId& id) override
221    {
222        return getWritableVecRegFlat(flattenRegId(id).index());
223    }
224
225    /** Vector Register Lane Interfaces. */
226    /** @{ */
227    /** Reads source vector 8bit operand. */
228    virtual ConstVecLane8
229    readVec8BitLaneReg(const RegId& id) const override
230    {
231        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
232                    id.elemIndex());
233    }
234
235    /** Reads source vector 16bit operand. */
236    virtual ConstVecLane16
237    readVec16BitLaneReg(const RegId& id) const override
238    {
239        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
240                    id.elemIndex());
241    }
242
243    /** Reads source vector 32bit operand. */
244    virtual ConstVecLane32
245    readVec32BitLaneReg(const RegId& id) const override
246    {
247        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
248                    id.elemIndex());
249    }
250
251    /** Reads source vector 64bit operand. */
252    virtual ConstVecLane64
253    readVec64BitLaneReg(const RegId& id) const override
254    {
255        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
256                    id.elemIndex());
257    }
258
259    /** Write a lane of the destination vector register. */
260    virtual void setVecLane(const RegId& reg,
261            const LaneData<LaneSize::Byte>& val) override
262    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
263    virtual void setVecLane(const RegId& reg,
264            const LaneData<LaneSize::TwoByte>& val) override
265    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
266    virtual void setVecLane(const RegId& reg,
267            const LaneData<LaneSize::FourByte>& val) override
268    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
269    virtual void setVecLane(const RegId& reg,
270            const LaneData<LaneSize::EightByte>& val) override
271    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
272    /** @} */
273
274    virtual const VecElem& readVecElem(const RegId& reg) const override {
275        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
276    }
277
278    virtual const VecPredRegContainer&
279    readVecPredReg(const RegId& id) const override {
280        return readVecPredRegFlat(flattenRegId(id).index());
281    }
282
283    virtual VecPredRegContainer&
284    getWritableVecPredReg(const RegId& id) override {
285        return getWritableVecPredRegFlat(flattenRegId(id).index());
286    }
287
288    virtual RegVal
289    readCCReg(int reg_idx) override
290    {
291        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
292                                                 reg_idx)).index());
293    }
294
295    /** Sets an integer register to a value. */
296    virtual void
297    setIntReg(int reg_idx, RegVal val) override
298    {
299        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
300    }
301
302    virtual void
303    setFloatReg(int reg_idx, RegVal val) override
304    {
305        setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
306                                           reg_idx)).index(), val);
307    }
308
309    virtual void
310    setVecReg(const RegId& reg, const VecRegContainer& val) override
311    {
312        setVecRegFlat(flattenRegId(reg).index(), val);
313    }
314
315    virtual void
316    setVecElem(const RegId& reg, const VecElem& val) override
317    {
318        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
319    }
320
321    virtual void
322    setVecPredReg(const RegId& reg,
323                  const VecPredRegContainer& val) override
324    {
325        setVecPredRegFlat(flattenRegId(reg).index(), val);
326    }
327
328    virtual void
329    setCCReg(int reg_idx, RegVal val) override
330    {
331        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
332    }
333
334    /** Reads this thread's PC state. */
335    virtual TheISA::PCState pcState() override
336    { return cpu->pcState(thread->threadId()); }
337
338    /** Sets this thread's PC state. */
339    virtual void pcState(const TheISA::PCState &val) override;
340
341    virtual void pcStateNoRecord(const TheISA::PCState &val) override;
342
343    /** Reads this thread's PC. */
344    virtual Addr instAddr() override
345    { return cpu->instAddr(thread->threadId()); }
346
347    /** Reads this thread's next PC. */
348    virtual Addr nextInstAddr() override
349    { return cpu->nextInstAddr(thread->threadId()); }
350
351    /** Reads this thread's next PC. */
352    virtual MicroPC microPC() override
353    { return cpu->microPC(thread->threadId()); }
354
355    /** Reads a miscellaneous register. */
356    virtual RegVal readMiscRegNoEffect(int misc_reg) const override
357    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
358
359    /** Reads a misc. register, including any side-effects the
360     * read might have as defined by the architecture. */
361    virtual RegVal readMiscReg(int misc_reg) override
362    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
363
364    /** Sets a misc. register. */
365    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override;
366
367    /** Sets a misc. register, including any side-effects the
368     * write might have as defined by the architecture. */
369    virtual void setMiscReg(int misc_reg, RegVal val) override;
370
371    virtual RegId flattenRegId(const RegId& regId) const override;
372
373    /** Returns the number of consecutive store conditional failures. */
374    // @todo: Figure out where these store cond failures should go.
375    virtual unsigned readStCondFailures() override
376    { return thread->storeCondFailures; }
377
378    /** Sets the number of consecutive store conditional failures. */
379    virtual void setStCondFailures(unsigned sc_failures) override
380    { thread->storeCondFailures = sc_failures; }
381
382    /** Executes a syscall in SE mode. */
383    virtual void syscall(int64_t callnum, Fault *fault) override
384    { return cpu->syscall(callnum, thread->threadId(), fault); }
385
386    /** Reads the funcExeInst counter. */
387    virtual Counter readFuncExeInst() override { return thread->funcExeInst; }
388
389    /** Returns pointer to the quiesce event. */
390    virtual EndQuiesceEvent *
391    getQuiesceEvent() override
392    {
393        return this->thread->quiesceEvent;
394    }
395    /** check if the cpu is currently in state update mode and squash if not.
396     * This function will return true if a trap is pending or if a fault or
397     * similar is currently writing to the thread context and doesn't want
398     * reset all the state (see noSquashFromTC).
399     */
400    inline void
401    conditionalSquash()
402    {
403        if (!thread->trapPending && !thread->noSquashFromTC)
404            cpu->squashFromTC(thread->threadId());
405    }
406
407    virtual RegVal readIntRegFlat(int idx) override;
408    virtual void setIntRegFlat(int idx, RegVal val) override;
409
410    virtual RegVal readFloatRegFlat(int idx) override;
411    virtual void setFloatRegFlat(int idx, RegVal val) override;
412
413    virtual const VecRegContainer& readVecRegFlat(int idx) const override;
414    /** Read vector register operand for modification, flat indexing. */
415    virtual VecRegContainer& getWritableVecRegFlat(int idx) override;
416    virtual void setVecRegFlat(int idx, const VecRegContainer& val) override;
417
418    template <typename VecElem>
419    VecLaneT<VecElem, true>
420    readVecLaneFlat(int idx, int lId) const
421    {
422        return cpu->template readArchVecLane<VecElem>(idx, lId,
423                thread->threadId());
424    }
425
426    template <typename LD>
427    void setVecLaneFlat(int idx, int lId, const LD& val)
428    {
429        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
430    }
431
432    virtual const VecElem& readVecElemFlat(
433        const RegIndex& idx,
434        const ElemIndex& elemIndex) const override;
435    virtual void setVecElemFlat(
436        const RegIndex& idx,
437        const ElemIndex& elemIdx, const VecElem& val) override;
438
439    virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
440        const override;
441    virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override;
442    virtual void setVecPredRegFlat(int idx,
443                                   const VecPredRegContainer& val) override;
444
445    virtual RegVal readCCRegFlat(int idx) override;
446    virtual void setCCRegFlat(int idx, RegVal val) override;
447};
448
449#endif
450