thread_context.hh revision 13628
1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 45#define __CPU_O3_THREAD_CONTEXT_HH__ 46 47#include "config/the_isa.hh" 48#include "cpu/o3/isa_specific.hh" 49#include "cpu/thread_context.hh" 50 51class EndQuiesceEvent; 52namespace Kernel { 53 class Statistics; 54} 55 56/** 57 * Derived ThreadContext class for use with the O3CPU. It 58 * provides the interface for any external objects to access a 59 * single thread's state and some general CPU state. Any time 60 * external objects try to update state through this interface, 61 * the CPU will create an event to squash all in-flight 62 * instructions in order to ensure state is maintained correctly. 63 * It must be defined specifically for the O3CPU because 64 * not all architectural state is located within the O3ThreadState 65 * (such as the commit PC, and registers), and specific actions 66 * must be taken when using this interface (such as squashing all 67 * in-flight instructions when doing a write to this interface). 68 */ 69template <class Impl> 70class O3ThreadContext : public ThreadContext 71{ 72 public: 73 typedef typename Impl::O3CPU O3CPU; 74 75 /** Pointer to the CPU. */ 76 O3CPU *cpu; 77 78 /** Pointer to the thread state that this TC corrseponds to. */ 79 O3ThreadState<Impl> *thread; 80 81 /** Returns a pointer to the ITB. */ 82 BaseTLB *getITBPtr() override { return cpu->itb; } 83 84 /** Returns a pointer to the DTB. */ 85 BaseTLB *getDTBPtr() override { return cpu->dtb; } 86 87 CheckerCPU *getCheckerCpuPtr() override { return NULL; } 88 89 TheISA::Decoder * 90 getDecoderPtr() override 91 { 92 return cpu->fetch.decoder[thread->threadId()]; 93 } 94 95 /** Returns a pointer to this CPU. */ 96 virtual BaseCPU *getCpuPtr() override { return cpu; } 97 98 /** Reads this CPU's ID. */ 99 virtual int cpuId() const override { return cpu->cpuId(); } 100 101 /** Reads this CPU's Socket ID. */ 102 virtual uint32_t socketId() const override { return cpu->socketId(); } 103 104 virtual ContextID 105 contextId() const override { return thread->contextId(); } 106 107 virtual void setContextId(int id) override { thread->setContextId(id); } 108 109 /** Returns this thread's ID number. */ 110 virtual int threadId() const override 111 { return thread->threadId(); } 112 virtual void setThreadId(int id) override 113 { return thread->setThreadId(id); } 114 115 /** Returns a pointer to the system. */ 116 virtual System *getSystemPtr() override { return cpu->system; } 117 118 /** Returns a pointer to this thread's kernel statistics. */ 119 virtual TheISA::Kernel::Statistics *getKernelStats() override 120 { return thread->kernelStats; } 121 122 /** Returns a pointer to this thread's process. */ 123 virtual Process *getProcessPtr() override 124 { return thread->getProcessPtr(); } 125 126 virtual void setProcessPtr(Process *p) override 127 { thread->setProcessPtr(p); } 128 129 virtual PortProxy &getPhysProxy() override 130 { return thread->getPhysProxy(); } 131 132 virtual FSTranslatingPortProxy &getVirtProxy() override; 133 134 virtual void initMemProxies(ThreadContext *tc) override 135 { thread->initMemProxies(tc); } 136 137 virtual SETranslatingPortProxy &getMemProxy() override 138 { return thread->getMemProxy(); } 139 140 /** Returns this thread's status. */ 141 virtual Status status() const override { return thread->status(); } 142 143 /** Sets this thread's status. */ 144 virtual void setStatus(Status new_status) override 145 { thread->setStatus(new_status); } 146 147 /** Set the status to Active. */ 148 virtual void activate() override; 149 150 /** Set the status to Suspended. */ 151 virtual void suspend() override; 152 153 /** Set the status to Halted. */ 154 virtual void halt() override; 155 156 /** Dumps the function profiling information. 157 * @todo: Implement. 158 */ 159 virtual void dumpFuncProfile() override; 160 161 /** Takes over execution of a thread from another CPU. */ 162 virtual void takeOverFrom(ThreadContext *old_context) override; 163 164 /** Registers statistics associated with this TC. */ 165 virtual void regStats(const std::string &name) override; 166 167 /** Reads the last tick that this thread was activated on. */ 168 virtual Tick readLastActivate() override; 169 /** Reads the last tick that this thread was suspended on. */ 170 virtual Tick readLastSuspend() override; 171 172 /** Clears the function profiling information. */ 173 virtual void profileClear() override; 174 /** Samples the function profiling information. */ 175 virtual void profileSample() override; 176 177 /** Copies the architectural registers from another TC into this TC. */ 178 virtual void copyArchRegs(ThreadContext *tc) override; 179 180 /** Resets all architectural registers to 0. */ 181 virtual void clearArchRegs() override; 182 183 /** Reads an integer register. */ 184 virtual RegVal 185 readReg(int reg_idx) 186 { 187 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 188 reg_idx)).index()); 189 } 190 virtual RegVal 191 readIntReg(int reg_idx) override 192 { 193 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 194 reg_idx)).index()); 195 } 196 197 virtual RegVal 198 readFloatReg(int reg_idx) override 199 { 200 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 201 reg_idx)).index()); 202 } 203 204 virtual const VecRegContainer & 205 readVecReg(const RegId& id) const override 206 { 207 return readVecRegFlat(flattenRegId(id).index()); 208 } 209 210 /** 211 * Read vector register operand for modification, hierarchical indexing. 212 */ 213 virtual VecRegContainer & 214 getWritableVecReg(const RegId& id) override 215 { 216 return getWritableVecRegFlat(flattenRegId(id).index()); 217 } 218 219 /** Vector Register Lane Interfaces. */ 220 /** @{ */ 221 /** Reads source vector 8bit operand. */ 222 virtual ConstVecLane8 223 readVec8BitLaneReg(const RegId& id) const override 224 { 225 return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 226 id.elemIndex()); 227 } 228 229 /** Reads source vector 16bit operand. */ 230 virtual ConstVecLane16 231 readVec16BitLaneReg(const RegId& id) const override 232 { 233 return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 234 id.elemIndex()); 235 } 236 237 /** Reads source vector 32bit operand. */ 238 virtual ConstVecLane32 239 readVec32BitLaneReg(const RegId& id) const override 240 { 241 return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 242 id.elemIndex()); 243 } 244 245 /** Reads source vector 64bit operand. */ 246 virtual ConstVecLane64 247 readVec64BitLaneReg(const RegId& id) const override 248 { 249 return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 250 id.elemIndex()); 251 } 252 253 /** Write a lane of the destination vector register. */ 254 virtual void setVecLane(const RegId& reg, 255 const LaneData<LaneSize::Byte>& val) override 256 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 257 virtual void setVecLane(const RegId& reg, 258 const LaneData<LaneSize::TwoByte>& val) override 259 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 260 virtual void setVecLane(const RegId& reg, 261 const LaneData<LaneSize::FourByte>& val) override 262 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 263 virtual void setVecLane(const RegId& reg, 264 const LaneData<LaneSize::EightByte>& val) override 265 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 266 /** @} */ 267 268 virtual const VecElem& readVecElem(const RegId& reg) const override { 269 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 270 } 271 272 virtual const VecPredRegContainer& 273 readVecPredReg(const RegId& id) const override { 274 return readVecPredRegFlat(flattenRegId(id).index()); 275 } 276 277 virtual VecPredRegContainer& 278 getWritableVecPredReg(const RegId& id) override { 279 return getWritableVecPredRegFlat(flattenRegId(id).index()); 280 } 281 282 virtual RegVal 283 readCCReg(int reg_idx) override 284 { 285 return readCCRegFlat(flattenRegId(RegId(CCRegClass, 286 reg_idx)).index()); 287 } 288 289 /** Sets an integer register to a value. */ 290 virtual void 291 setIntReg(int reg_idx, RegVal val) override 292 { 293 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 294 } 295 296 virtual void 297 setFloatReg(int reg_idx, RegVal val) override 298 { 299 setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 300 reg_idx)).index(), val); 301 } 302 303 virtual void 304 setVecReg(const RegId& reg, const VecRegContainer& val) override 305 { 306 setVecRegFlat(flattenRegId(reg).index(), val); 307 } 308 309 virtual void 310 setVecElem(const RegId& reg, const VecElem& val) override 311 { 312 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 313 } 314 315 virtual void 316 setVecPredReg(const RegId& reg, 317 const VecPredRegContainer& val) override 318 { 319 setVecPredRegFlat(flattenRegId(reg).index(), val); 320 } 321 322 virtual void 323 setCCReg(int reg_idx, RegVal val) override 324 { 325 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 326 } 327 328 /** Reads this thread's PC state. */ 329 virtual TheISA::PCState pcState() override 330 { return cpu->pcState(thread->threadId()); } 331 332 /** Sets this thread's PC state. */ 333 virtual void pcState(const TheISA::PCState &val) override; 334 335 virtual void pcStateNoRecord(const TheISA::PCState &val) override; 336 337 /** Reads this thread's PC. */ 338 virtual Addr instAddr() override 339 { return cpu->instAddr(thread->threadId()); } 340 341 /** Reads this thread's next PC. */ 342 virtual Addr nextInstAddr() override 343 { return cpu->nextInstAddr(thread->threadId()); } 344 345 /** Reads this thread's next PC. */ 346 virtual MicroPC microPC() override 347 { return cpu->microPC(thread->threadId()); } 348 349 /** Reads a miscellaneous register. */ 350 virtual RegVal readMiscRegNoEffect(int misc_reg) const override 351 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 352 353 /** Reads a misc. register, including any side-effects the 354 * read might have as defined by the architecture. */ 355 virtual RegVal readMiscReg(int misc_reg) override 356 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 357 358 /** Sets a misc. register. */ 359 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; 360 361 /** Sets a misc. register, including any side-effects the 362 * write might have as defined by the architecture. */ 363 virtual void setMiscReg(int misc_reg, RegVal val) override; 364 365 virtual RegId flattenRegId(const RegId& regId) const override; 366 367 /** Returns the number of consecutive store conditional failures. */ 368 // @todo: Figure out where these store cond failures should go. 369 virtual unsigned readStCondFailures() override 370 { return thread->storeCondFailures; } 371 372 /** Sets the number of consecutive store conditional failures. */ 373 virtual void setStCondFailures(unsigned sc_failures) override 374 { thread->storeCondFailures = sc_failures; } 375 376 /** Executes a syscall in SE mode. */ 377 virtual void syscall(int64_t callnum, Fault *fault) override 378 { return cpu->syscall(callnum, thread->threadId(), fault); } 379 380 /** Reads the funcExeInst counter. */ 381 virtual Counter readFuncExeInst() override { return thread->funcExeInst; } 382 383 /** Returns pointer to the quiesce event. */ 384 virtual EndQuiesceEvent * 385 getQuiesceEvent() override 386 { 387 return this->thread->quiesceEvent; 388 } 389 /** check if the cpu is currently in state update mode and squash if not. 390 * This function will return true if a trap is pending or if a fault or 391 * similar is currently writing to the thread context and doesn't want 392 * reset all the state (see noSquashFromTC). 393 */ 394 inline void 395 conditionalSquash() 396 { 397 if (!thread->trapPending && !thread->noSquashFromTC) 398 cpu->squashFromTC(thread->threadId()); 399 } 400 401 virtual RegVal readIntRegFlat(int idx) override; 402 virtual void setIntRegFlat(int idx, RegVal val) override; 403 404 virtual RegVal readFloatRegFlat(int idx) override; 405 virtual void setFloatRegFlat(int idx, RegVal val) override; 406 407 virtual const VecRegContainer& readVecRegFlat(int idx) const override; 408 /** Read vector register operand for modification, flat indexing. */ 409 virtual VecRegContainer& getWritableVecRegFlat(int idx) override; 410 virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; 411 412 template <typename VecElem> 413 VecLaneT<VecElem, true> 414 readVecLaneFlat(int idx, int lId) const 415 { 416 return cpu->template readArchVecLane<VecElem>(idx, lId, 417 thread->threadId()); 418 } 419 420 template <typename LD> 421 void setVecLaneFlat(int idx, int lId, const LD& val) 422 { 423 cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 424 } 425 426 virtual const VecElem& readVecElemFlat( 427 const RegIndex& idx, 428 const ElemIndex& elemIndex) const override; 429 virtual void setVecElemFlat( 430 const RegIndex& idx, 431 const ElemIndex& elemIdx, const VecElem& val) override; 432 433 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 434 const override; 435 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 436 virtual void setVecPredRegFlat(int idx, 437 const VecPredRegContainer& val) override; 438 439 virtual RegVal readCCRegFlat(int idx) override; 440 virtual void setCCRegFlat(int idx, RegVal val) override; 441}; 442 443#endif 444