thread_context.hh revision 13500:6e0a2a7c6d8c 
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    BaseTLB *getITBPtr() { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    BaseTLB *getDTBPtr() { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() { return NULL; }
88
89    TheISA::Decoder *
90    getDecoderPtr()
91    {
92        return cpu->fetch.decoder[thread->threadId()];
93    }
94
95    /** Returns a pointer to this CPU. */
96    virtual BaseCPU *getCpuPtr() { return cpu; }
97
98    /** Reads this CPU's ID. */
99    virtual int cpuId() const { return cpu->cpuId(); }
100
101    /** Reads this CPU's Socket ID. */
102    virtual uint32_t socketId() const { return cpu->socketId(); }
103
104    virtual ContextID contextId() const { return thread->contextId(); }
105
106    virtual void setContextId(int id) { thread->setContextId(id); }
107
108    /** Returns this thread's ID number. */
109    virtual int threadId() const { return thread->threadId(); }
110    virtual void setThreadId(int id) { return thread->setThreadId(id); }
111
112    /** Returns a pointer to the system. */
113    virtual System *getSystemPtr() { return cpu->system; }
114
115    /** Returns a pointer to this thread's kernel statistics. */
116    virtual TheISA::Kernel::Statistics *getKernelStats()
117    { return thread->kernelStats; }
118
119    /** Returns a pointer to this thread's process. */
120    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
121
122    virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); }
123
124    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
125
126    virtual FSTranslatingPortProxy &getVirtProxy();
127
128    virtual void initMemProxies(ThreadContext *tc)
129    { thread->initMemProxies(tc); }
130
131    virtual SETranslatingPortProxy &getMemProxy()
132    { return thread->getMemProxy(); }
133
134    /** Returns this thread's status. */
135    virtual Status status() const { return thread->status(); }
136
137    /** Sets this thread's status. */
138    virtual void setStatus(Status new_status)
139    { thread->setStatus(new_status); }
140
141    /** Set the status to Active. */
142    virtual void activate();
143
144    /** Set the status to Suspended. */
145    virtual void suspend();
146
147    /** Set the status to Halted. */
148    virtual void halt();
149
150    /** Dumps the function profiling information.
151     * @todo: Implement.
152     */
153    virtual void dumpFuncProfile();
154
155    /** Takes over execution of a thread from another CPU. */
156    virtual void takeOverFrom(ThreadContext *old_context);
157
158    /** Registers statistics associated with this TC. */
159    virtual void regStats(const std::string &name);
160
161    /** Reads the last tick that this thread was activated on. */
162    virtual Tick readLastActivate();
163    /** Reads the last tick that this thread was suspended on. */
164    virtual Tick readLastSuspend();
165
166    /** Clears the function profiling information. */
167    virtual void profileClear();
168    /** Samples the function profiling information. */
169    virtual void profileSample();
170
171    /** Copies the architectural registers from another TC into this TC. */
172    virtual void copyArchRegs(ThreadContext *tc);
173
174    /** Resets all architectural registers to 0. */
175    virtual void clearArchRegs();
176
177    /** Reads an integer register. */
178    virtual uint64_t readReg(int reg_idx) {
179        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
180                                                 reg_idx)).index());
181    }
182    virtual uint64_t readIntReg(int reg_idx) {
183        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
184                                                 reg_idx)).index());
185    }
186
187    virtual FloatRegBits readFloatRegBits(int reg_idx) {
188        return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
189                                                 reg_idx)).index());
190    }
191
192    virtual const VecRegContainer& readVecReg(const RegId& id) const {
193        return readVecRegFlat(flattenRegId(id).index());
194    }
195
196    /**
197     * Read vector register operand for modification, hierarchical indexing.
198     */
199    virtual VecRegContainer& getWritableVecReg(const RegId& id) {
200        return getWritableVecRegFlat(flattenRegId(id).index());
201    }
202
203    /** Vector Register Lane Interfaces. */
204    /** @{ */
205    /** Reads source vector 8bit operand. */
206    virtual ConstVecLane8
207    readVec8BitLaneReg(const RegId& id) const
208    {
209        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
210                    id.elemIndex());
211    }
212
213    /** Reads source vector 16bit operand. */
214    virtual ConstVecLane16
215    readVec16BitLaneReg(const RegId& id) const
216    {
217        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
218                    id.elemIndex());
219    }
220
221    /** Reads source vector 32bit operand. */
222    virtual ConstVecLane32
223    readVec32BitLaneReg(const RegId& id) const
224    {
225        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
226                    id.elemIndex());
227    }
228
229    /** Reads source vector 64bit operand. */
230    virtual ConstVecLane64
231    readVec64BitLaneReg(const RegId& id) const
232    {
233        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
234                    id.elemIndex());
235    }
236
237    /** Write a lane of the destination vector register. */
238    virtual void setVecLane(const RegId& reg,
239            const LaneData<LaneSize::Byte>& val)
240    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
241    virtual void setVecLane(const RegId& reg,
242            const LaneData<LaneSize::TwoByte>& val)
243    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
244    virtual void setVecLane(const RegId& reg,
245            const LaneData<LaneSize::FourByte>& val)
246    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
247    virtual void setVecLane(const RegId& reg,
248            const LaneData<LaneSize::EightByte>& val)
249    { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
250    /** @} */
251
252    virtual const VecElem& readVecElem(const RegId& reg) const {
253        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
254    }
255
256    virtual CCReg readCCReg(int reg_idx) {
257        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
258                                                 reg_idx)).index());
259    }
260
261    /** Sets an integer register to a value. */
262    virtual void setIntReg(int reg_idx, uint64_t val) {
263        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
264    }
265
266    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
267        setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
268                                               reg_idx)).index(), val);
269    }
270
271    virtual void setVecReg(const RegId& reg, const VecRegContainer& val) {
272        setVecRegFlat(flattenRegId(reg).index(), val);
273    }
274
275    virtual void setVecElem(const RegId& reg, const VecElem& val) {
276        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
277    }
278
279    virtual void setCCReg(int reg_idx, CCReg val) {
280        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
281    }
282
283    /** Reads this thread's PC state. */
284    virtual TheISA::PCState pcState()
285    { return cpu->pcState(thread->threadId()); }
286
287    /** Sets this thread's PC state. */
288    virtual void pcState(const TheISA::PCState &val);
289
290    virtual void pcStateNoRecord(const TheISA::PCState &val);
291
292    /** Reads this thread's PC. */
293    virtual Addr instAddr()
294    { return cpu->instAddr(thread->threadId()); }
295
296    /** Reads this thread's next PC. */
297    virtual Addr nextInstAddr()
298    { return cpu->nextInstAddr(thread->threadId()); }
299
300    /** Reads this thread's next PC. */
301    virtual MicroPC microPC()
302    { return cpu->microPC(thread->threadId()); }
303
304    /** Reads a miscellaneous register. */
305    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
306    { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
307
308    /** Reads a misc. register, including any side-effects the
309     * read might have as defined by the architecture. */
310    virtual MiscReg readMiscReg(int misc_reg)
311    { return cpu->readMiscReg(misc_reg, thread->threadId()); }
312
313    /** Sets a misc. register. */
314    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
315
316    /** Sets a misc. register, including any side-effects the
317     * write might have as defined by the architecture. */
318    virtual void setMiscReg(int misc_reg, const MiscReg &val);
319
320    virtual RegId flattenRegId(const RegId& regId) const;
321
322    /** Returns the number of consecutive store conditional failures. */
323    // @todo: Figure out where these store cond failures should go.
324    virtual unsigned readStCondFailures()
325    { return thread->storeCondFailures; }
326
327    /** Sets the number of consecutive store conditional failures. */
328    virtual void setStCondFailures(unsigned sc_failures)
329    { thread->storeCondFailures = sc_failures; }
330
331    /** Executes a syscall in SE mode. */
332    virtual void syscall(int64_t callnum, Fault *fault)
333    { return cpu->syscall(callnum, thread->threadId(), fault); }
334
335    /** Reads the funcExeInst counter. */
336    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
337
338    /** Returns pointer to the quiesce event. */
339    virtual EndQuiesceEvent *getQuiesceEvent()
340    {
341        return this->thread->quiesceEvent;
342    }
343    /** check if the cpu is currently in state update mode and squash if not.
344     * This function will return true if a trap is pending or if a fault or
345     * similar is currently writing to the thread context and doesn't want
346     * reset all the state (see noSquashFromTC).
347     */
348    inline void conditionalSquash()
349    {
350        if (!thread->trapPending && !thread->noSquashFromTC)
351            cpu->squashFromTC(thread->threadId());
352    }
353
354    virtual uint64_t readIntRegFlat(int idx);
355    virtual void setIntRegFlat(int idx, uint64_t val);
356
357    virtual FloatRegBits readFloatRegBitsFlat(int idx);
358    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
359
360    virtual const VecRegContainer& readVecRegFlat(int idx) const;
361    /** Read vector register operand for modification, flat indexing. */
362    virtual VecRegContainer& getWritableVecRegFlat(int idx);
363    virtual void setVecRegFlat(int idx, const VecRegContainer& val);
364
365    template <typename VecElem>
366    VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const
367    {
368        return cpu->template readArchVecLane<VecElem>(idx, lId,
369                thread->threadId());
370    }
371
372    template <typename LD>
373    void setVecLaneFlat(int idx, int lId, const LD& val)
374    {
375        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
376    }
377
378    virtual const VecElem& readVecElemFlat(const RegIndex& idx,
379                                           const ElemIndex& elemIndex) const;
380    virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
381                                const VecElem& val);
382
383    virtual CCReg readCCRegFlat(int idx);
384    virtual void setCCRegFlat(int idx, CCReg val);
385};
386
387#endif
388